Abstract: A source-voltage-operated circuit having: an electric power source; an operated circuit section operated according to a voltage supplied by the electric power source; a control-voltage-supplying circuit section for deriving a voltage higher than the voltage supplied by the electric power source from the operated circuit section to rectify the derived voltage and output the resultant voltage as an operating voltage; and a control circuit section operated according to the operating voltage for controlling the operation of the operated circuit section and stopping the operation of the operated circuit section when the operating voltage is decreased to a given reset voltage or below.

Abstract: A current/charge-voltage converter having an operational amplifier and a first capacitor connected between the input terminal and the output terminal of the operational amplifier, comprising a first switch which has one end connected to this input terminal, a first signal source that generates control signals for the first switch, a second capacitor connected to the first capacitor, and a second signal source connected to the other terminal of the second capacitor.

Abstract: A high-density DDR-1/DDR-2 compatible SDRAM chip with a reduced output circuit area is provided. When the SDRAM is a DDR1 SDRAM, an output signal output from an output circuit (14) is output to an output terminal (17) as a main output signal. When the SDRAM is a DDR2 SDRAM, an output signal output from an output circuit (15) is output to the output terminal (17) as the main output signal and, at the same time, the output signal output from the output circuit (14) is output as a sub-output signal to perform operation for adjusting the slew rate or the amount of output current of the main output signal or for adjusting the impedance of the output terminal as viewed from an external point.

Abstract: Disclosed is a portable terminal that includes an external device interface unit, a memory unit, a main controller, and a power supply unit. The external device interface unit provides a connection between the portable terminal and an external device, includes ports outputting control signals and electric power for operating the external device, and controls an operation of the external device. The memory unit stores downloaded information for operating the external device that is connected to the portable terminal through the external device interface unit. The main controller generates an external device control signal based on the operation information stored in the memory unit, and transmits the external device control signal to the external device interface unit. The power supply unit provides power for driving the external device through the external device interface unit.

Abstract: A selection circuit having a comparator with comparator inputs connected to first and second voltage inputs), respectively, and a comparator output connected to a control input of a first controllable switch and an inverter. The selection circuit also has a second controllable switch having a second control input connected to the inverter. The first voltage input is connectable to a selection circuit output by the first controllable switch and the second voltage input is connectable to the selection circuit output by the second controllable switch. The inverter has a power supply connector connected to the first voltage input and the comparator has a power supply connector connected to the second voltage input.

Abstract: A first MOS-on-NWELL device is formed on a substrate and has its pickup terminals optionally connected together. A second MOS-on-NWELL device is formed on the substrate and has its pickup terminals optionally connected together. A gate of the first MOS-on-NWELL device is connected to the pickup terminals of the second MOS-on-NWELL device. A gate of the second MOS-on-NWELL device is connected to the pickup terminals of the first MOS-on-NWELL device. A first PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A second PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A gate of the first PMOS transistor is connected to the source and drain terminals of the second PMOS transistor. A gate of the second PMOS transistor is connected to the source and drain terminals of the first PMOS transistor.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: A current compensation circuit for use with a current mirror circuit is disclosed. The current mirror circuit has a current path defined by a first programmable current mirror stage driving a first fanout current mirror stage. The first programmable current mirror stage includes at least one transistor with a channel length exhibiting a first channel length modulation factor ?1. The first fanout current mirror stage connects to a supply voltage source. The current compensation circuit comprises a supply voltage current mirror coupled to the supply voltage source and has a current output coupled to the current path. The compensation circuit further includes a second programmable current mirror coupled in series to the supply voltage current mirror and including at least one transistor with a channel length exhibiting a channel length modulation factor ?2. The second channel length modulation factor ?2 is larger than the first channel length modulation factor ?1.

Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Abstract: A bias generator that automatically adjusts its slew rate is disclosed to generate an output bias current and adjust the output bias current according to the frequency of a clock signal. The slew rate of the amplifier is thus controlled to save power. It includes: a current mirror for receiving a feedback voltage and generating an output bias current; a storage capacitor with a first end and a second end and the latter being coupled to the ground; a charging switch coupled between the output of the current mirror and the first end of the storage capacitor; a discharging switch coupled between the first end of the storage capacitor and the ground; a comparator whose input is coupled to the first end of the storage capacitor and a reference voltage; and a feedback unit coupled to the output of the comparator for outputting a feedback voltage to the current mirror.

Abstract: The invention relates to a method and an apparatus for producing a reference voltage that is applied to reference voltage inputs on receiver units in order to discriminate between the logic states of a data signal that is transmitted to a receiver end. A transmission device transmits, in addition to the data signal, a clock signal to the receiver end. The receiver end has, on the output side of a receiver unit that receives the clock signal, an integrator that integrates the clock signal and produces the reference voltage from the integrated value.

Abstract: A driver circuit that allows high-speed switching when the reference current (I) is small. The driver circuit includes a drive current generation circuit (220) for supplying to a first node (232) a drive current based on a binary data signal (DATA); a current mirror circuit (240) for conducting through a second node (234) a current (mI) having a magnitude of the current flowing through the first node (232), multiplied by a predetermined current mirror ratio (m); and a pre-bias circuit (260) for supplying a first pre-bias current (Ib1) to the first node (232) and supplying a second pre-bias current (Ib2) having a magnitude of the first pre-bias current (Ib1), multiplied by said current mirror ratio (m), to the second node (234).

Abstract: A biasing circuit for a CMOS passive mixer core to stabilize its conversion gain, linearity and noise figure. The RF inputs are fed differentially from the two RF ports, the LO inputs are fed differentially from the two LO ports, and the IF outputs are obtained at the two IF ports. The biasing circuit comprises a reference current derived from the bandgap voltage and a n-channel MOSFET transistor. The conversion gain is stabilized by keeping the Vgs?Vth value of the passive mixer core almost constant at all process corners, temperature and power supply changes. This is achieved by implementing Vs in such a way that it will increase the same amount as VDD decreases, and that Vs will decrease the same amount as Vth increases.

Abstract: A powergating circuit includes an MOS circuit such as a memory circuit having a first power terminal and a second power terminal, a P-channel transistor having a drain coupled to the first power terminal of the MOS circuit, and an N-channel transistor having a drain coupled to the second power terminal of the MOS circuit. In order to minimize leakage current and resultant power dissipation a negative VGS voltage is established in the transistors during a standby mode and a boosted VGS voltage is established in the transistors during an active mode.

Abstract: A voltage detection unit generates a detection voltage signal representative of a potential difference caused by a current to be detected. A reference current generation unit generates a first reference current and a second reference current having a linear relationship therebetween. In response to the detection voltage signal and the first reference current, a transfer unit determines a first operation voltage. Furthermore, the transfer unit determines a second operation voltage and a transfer current in response to the first operation voltage and the second reference current. The second operation voltage is substantially equal to the first operation voltage. A detection current signal having a linear relationship with the current to be detected is generated through subtracting at least the second reference current from the transfer current.

Abstract: Methods and circuits for minimizing or eliminating the effect of trimming circuits in a voltage generating circuit are provided. In general, the effects of channel resistance of switches of the trimming circuit are reduced by utilizing switches in series with the output, rather than in parallel with resistors, as in conventional trimming circuits. Because the switches are not in parallel with the resistors, when the switches are turned on, no channel resistance is added to the effective resistance controlled by the trimming circuit.

Abstract: NMOS composite device Vds bootstrappers that mitigate the effects of decreased power supply rejection and increased channel length modulation in minimum or short channel length devices. The NMOS composite devices have a native or at least a low threshold device over a short channel device, with the gate of the native or low threshold device being controlled responsive to the input or output of the short channel device to clamp the drain—source voltage of the short channel device while holding the short channel device in saturation. In one embodiment, a native device is used, with the gate or the native device being connected to the gate of the short channel device. Other embodiments, including embodiments in the form of source followers having enhanced linearity are disclosed.

Abstract: A first conductive transistor having a high threshold value and a second conductive transistor having a low threshold value are connected in series between a first actual power supply line supplying a power supply voltage and a virtual power supply line connected to a power supply pin of a circuit block constituted of transistors having a low threshold value. The first and second conductive transistors have polarities which are opposite to each other. A power control circuit turns on the first and second conductive transistors while the circuit block is in operation and turning off the first and second conductive transistors while the circuit block is not in operation. Therefore, subthreshold currents of the first and second conductive transistors can be suppressed. As a result of this, it is possible to reduce power consumption of the semiconductor integrated circuit during its standby period.

Abstract: A constant current source with threshold voltage and channel length modulation comprises a set of cascade transistors and a compensation circuit electrically connected to the set of cascade transistors so as to form a feedback circuit, in which the set of cascade transistors including a first MOS transistor and a second MOS transistor, and the compensation circuit comprises a third MOS transistor, a fourth MOS transistor, a sixth MOS transistor and a seventh MOS transistor. The gate terminal of the third MOS transistor is connected to the gate terminal of the second MOS transistor. The fourth MOS transistor is connected to the third MOS transistor in serial, and the gate terminal of the fourth MOS transistor is connected to the gate terminal of the first MOS transistor, and the second terminal of the fourth MOS transistor is connected to a current-supplying circuit.

Abstract: An IC device has a MOSFET serving as a power switch, a condenser connected between a first input terminal of the IC and the gate of the MOSFET, and a ferroelectric condenser connected between a second input terminal of the IC and the gate of the MOSFET. A prescribed voltage having a predetermined polarity is applied across the first and the second input terminals to generate a remanent polarization oriented in a specific direction in the ferroelectric condenser, thereby raising the threshold voltage of the MOSFET to a higher level than its original level. The power switching MOSFET is fabricated in the same manufacturing process as for other circuit blocks of the IC device such that it has substantially the same threshold voltage as that of the MOSFETs in other circuit blocks.

Abstract: A voltage detection circuit. A second NMOS transistor has a gate coupled to the gate of a first NMOS transistor. A comparator has input terminals, and an output terminal. A first resistor is coupled between the first input terminal and the source of the first NMOS transistor, a second resistor is coupled to the comparator and the first resistor, a third resistor is coupled between the second resistor and the comparator, and a fourth resistor is coupled between the second and third resistors, and ground. A first PMOS transistor has a gate coupled to the gates of the first and second NMOS transistors. A second PMOS transistor has a connected gate and drain, a source coupled to the gates of first and second NMOS transistors, a drain coupled to ground, and an n-well directly connected to the gates of the first and second NMOS transistors.

Abstract: Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.

Abstract: A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source. Isolation between load circuits coupled to the first and second bias sources is thus enhanced while providing low noise, stable operation.

Abstract: A method and system of fractional biasing of semiconductors. A small negative voltage is applied to the back of a semiconductor wafer or device. An operating voltage is applied to the semiconductor. Operating characteristics of the semiconductor are enhanced by application of a fractional bias.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequencing problems provide an interim voltage during power-on sequences in order to prevent over-voltage conditions across IC terminals. Voltages at first and second terminals of a circuit are monitored and an interim voltage to the second terminal is provided when the voltage at the first terminal exceeds a first threshold and a voltage at the second terminal is below a second threshold. The interim voltage protects the circuit from excessive voltage differences across the first and second terminals during power-on sequences, and is deactivated during normal operation so as not to draw excessive current. The method/system helps to insure that multi-supply dependent logic and/or other circuitry does not receive inappropriate voltage levels, and thus helps to insure that lower voltage level based circuitry is not damaged during power-up, transients, and/or glitches.

Abstract: An integrated circuit comprises a biasing circuit for maintaining the transconductance of a Gm cell constant. The integrated circuit comprises an on-chip constant voltage source and an on-chip constant current source. The on-chip constant current source has a connection for an external resistance, the value of the external resistance determining the current generated by the constant current source. The biasing circuit comprises means for providing a first fraction (?) of the current generated by the on-chip current source to bias the output of the Gm cell, and means for providing a second fraction (?) of the voltage generated by the on-chip voltage source to bias the input of the Gm cell. The transconductance of the Gm cell is controlled to be equal to the ratio of said fraction of the current generated by the on-chip current source to said fraction of the voltage generated by the on-chip voltage source.

Abstract: In an up-converter feed forward control of the output current is effected by rendering the conduction time of the switching element proportional to Vout/Vin2. This control is fast and avoids interference and loss of efficiency.

Abstract: An integrated circuit has a voltage divider that is configured to save current. The circuit includes a capacitor that is inventively connected to a potential sink or potential source by way of a charge branch even when the voltage divider is inactive. The capacitor is thus held at a charge state that corresponds to the charge state given an active voltage divider. The voltage divider thus becomes functional in a shorter time following activation, because the capacitor does not require recharging.

Abstract: A method and apparatus for generating a reference voltage potential, also known as an input switching reference, using differential clock signals or other differential signals that ideally have a 180 degree phase shift is provided. The differential signals are generated by a transmitting circuit. The reference voltage potential is dependent on the differential signals. The voltage potentials of the differential signals are averaged and low-pass filtered. Comparators in a receiving circuit compare an input signal's voltage potential to the reference voltage potential to determine if the transmitted input signal is a binary one or binary zero.

Abstract: The invention relates to a voltage regulating circuit arrangement for converting a first voltage (VEXT) applied to an input of said voltage regulating circuit arrangement into a second voltage (VBLH) that may be tapped at an output of said voltage regulating circuit arrangement, wherein, when said first voltage (VEXT) falls below a threshold value (VEXT_THRESHOLD), the first voltage (VEXT) applied to the input of said voltage regulating circuit arrangement is connected through to said output of said voltage regulating circuit arrangement.

Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch, having a first terminal coupled to two or more voltage sources, with each voltage source providing a distinct voltage level representing a logic high level. The circuit includes first circuitry, having an output coupled to the switch for initially placing a first voltage across the switch representative of a logic low level. The circuit further includes second circuitry having an input coupled to the switch for sensing a voltage differential appearing across the switch and an output for indicating whether the voltage appearing across the switch is at any voltage representative of the logic high level, the second circuitry being controlled to selectively eliminate static current drawn by the circuit based upon the value of the output of the second circuitry.

Abstract: In a packaged integrated circuit, the package inductance limits the rate at which off-chip current may be varied in response to a change in on-chip current demand of the integrated circuit. The present invention provides an on-chip voltage regulator circuit for regulating multi-cycle voltage fluctuations of an integrated circuit associated with changes in current demand of the integrated circuit. The voltage regulator sources current to prevent an undervoltage conditions and sinks current to prevent an overvoltage condition.

Abstract: System for a current source with enhanced output impedance. A preferred embodiment comprises a cascode current source arranged in a current mirror configuration (such as current source 600) with a pair of level shifters arranged in a source-follower configuration (such as level shifters 505 and 510). The level shifters reduce the compliance voltage of the current source, permitting use in low voltage applications.

Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch. The circuit may include a first circuit for temporarily driving the second terminal of the switch to a second logic level. A second circuit, coupled to the switch, senses a voltage level of the second terminal of the switch and generates an output signal representative of the voltage sensed. A sequential logic circuit is responsive to the output signal of the second circuit so as to maintain a logic value representative of the switch having been closed.

Abstract: A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.

Abstract: A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: A switching regulator circuit is arranged to provide a constant current to a load. The switching regulator circuit is operated in discontinuous current mode such that an inductor stores energy in a first part of an oscillation cycle, and discharges in a second part of the cycle. The trigger mechanism for the oscillator is disabled when the charged inductor couples energy to the load, and enabled after the inductor is detected as discharged. The energy stored in the inductor is proportional to the square of the on-time associated with switching regulator. Constant voltage load devices such as LEDs for a display can be driven by the switching regulator in an open-loop mode such that the current in the load devices is a linear function of the on-time.

Abstract: The apparatus for generating a driving voltage for a sense amplifier has at least voltage output means, and first and second core voltage step-up means. The voltage output means outputs a voltage for driving the sense amplifier to a node. Each of the first and second core voltage step-up means are connected between a power supply and the node. The first and second core voltage step-up means are turned on in sequence to elevate the voltage level of the node connected with the sense amplifier up to the level of the power supply. This enhances the performance of the sense amplifier as well as the execute detection amplification in a short time period. The first and second core voltage step-up means are turned on in sequence to elevate the core voltage as the driving voltage, reducing the power noise. Each core voltage step-up driver may be installed in each bank to reduce power consumption.

Abstract: A buck converter is disclosed which prevents a voltage drop below a desired voltage when a load change occurs. The buck converter generates an override signal to turn on one or more switch devices in the circuitry. The effect of the override signal is to provide a sudden increase in the current supplied to a load, preventing the output voltage from dropping below the predetermined level. Sensing circuitry within the buck converter detects a voltage drop at the load, causing the override signal to be generated. The override signal may be a continuous signal or a one-shot pulse. Additional current sensing circuitry and the switch history of the buck converter determines the duration of the override signal for one embodiment and the number of switches activated within the buck converter.

Abstract: An electronic system with semiconductor components allows electronic circuits with conventional semiconductor components to be used, having minimal supply voltages to guarantee stable operation, lowering said minimum supply voltages. The range of supply voltages of such a circuit for which operation is stable can be extended towards low values by the effect of mutual compensation of the respective behaviors of said semiconductor components in their respective transition regions.

Abstract: An ultracapacitor based power storage device suitable for use in hybrid fuel cell systems and other power systems includes circuitry for simulating the response of a battery. A voltage current limiting circuit may be employed with a variety of electrical storage devices, for example, ultracapacitors and batteries.

Abstract: A semiconductor integrated circuit including a non-abrupt switching mechanism for a sleep transistor of a power gate structure to reduce ground bounce is provided. The semiconductor integrated circuit comprises a supply voltage line; a ground voltage line; a virtual ground voltage line; a logic circuit coupled to the supply voltage line and the virtual ground voltage line; at least one sleep transistor for controlling current flow to the logic circuit, the sleep transistor being coupled to the virtual ground voltage line and the ground voltage line; and a non-abrupt switching circuit for sequentially controlling the sleep transistor. The switching mechanism reduces the magnitude of voltage glitches on the power and ground rails as well as the minimum time required to stabilize power and ground.

Abstract: A means of high speed switching of a current source is accomplished by switching the source of the output current source transistor while employing circuitry to limit the movement of the source. The primary capacitance is the source diode, and the charge for this comes from a power rail. This results in both a reduction of and a good match of transients coupling to the output. Circuitry is also added to compensate for any current remaining when the current source is switched off.

Abstract: The present invention provides a balance apparatus for line input capacitors. A programmable N-current-sink is connected in parallel to a high-side capacitor, and a programmable P-current-sink is connected in parallel to a low-side capacitor. A resistor network is coupled between the high-side capacitor and the low-side capacitor to generate a differential voltage. The differential voltage is the voltage difference of the high side capacitor and the low side capacitor. When the voltage of the high-side capacitor is higher than the voltage of the low-side capacitor, the programmable N-current-sink will sink an N-current that is proportional to the differential voltage. If the voltage of the low-side capacitor is higher than the voltage of the high-side capacitor, the programmable P-current-sink will sink a P-current that is also proportional to the differential voltage. When the differential voltage is small, both the N-current-sink and the P-current-sink will be turned off to reduce power consumption.

Abstract: Connected to a power element having a first electrode, a second electrode, and a control electrode, a power element protection circuit detects a voltage between the first and second electrodes of the power element and the current flowing through the power element, then logarithmically converts a current proportional to the detected voltage and a current proportional to the detected current individually, then adds the results together, then subtracts a predetermined value from the sum, then antilogarithmically converts the result with an antilogarithmic converter, and then limits the driving of the power element based on the output of the antilogarithmic converter.

Abstract: The invention concerns an integrated circuit comprising means of delivering, on at least one output, a predetermined output voltage representative of a logic level, means of distributing a mains voltage and means of generating an internal voltage reference lower than the mains voltage, comprising means of connecting the mains voltage to the output and means of limiting and/or detecting the voltage at the output at the predetermined output voltage value, taking into account the reference voltage.

Abstract: A first bias voltage to be applied to a drain portion of a MOS transistor and a pulse voltage pulsating with a predetermined potential difference are being generated by an apparatus incorporating the MOS transistor. Voltage generation means generates a second bias voltage to be applied to a gate portion of the MOS transistor, based on a value of the predetermined potential difference of the pulse voltage generated in the apparatus incorporating the MOS transistor, a value of the first bias voltage generated in the apparatus incorporating the MOS transistor, and a channel potential of a channel portion provided beneath the gate portion of the MOS transistor. Superposition means generate a voltage to be applied to the gate portion of the MOS transistor by superposing the pulse voltage onto the second bias voltage generated by the voltage generation means.

Abstract: A circuit that allows selection of a power source among a plurality of power sources is disclosed. In an embodiment, either one or both voltage sources Vaux and Vapp may be available in a system. If both sources are available, then the circuit enables the system to use source Vaux. However, if only one of the two sources is available, then the circuit enables the system to use that available source.

Abstract: A voltage generation circuit for generating a read-back voltage in response to a supply voltage and a reference voltage. The voltage generation circuit includes a comparator configured to receive the supply voltage and the reference voltage. The voltage generation circuit activates a select signal if the supply voltage has a predetermined relationship with respect to the reference voltage, and de-activates the select signal if the supply voltage does not exhibit the predetermined relationship with respect to the reference voltage. An adjustable voltage divider circuit is coupled to receive the supply voltage and the select signal. The adjustable voltage divider circuit is configured in response to the select signal to provide an output voltage that is a first percentage of the supply voltage if the select signal is activated, and provide an output voltage that is a second percentage of the supply voltage if the select signal is de-activated.