Abstract: A negative voltage generating circuit includes a pulse generator U1, a switch, a resistor, a first capacitor, a first diode, a second diode, and a second capacitor. The pulse generator includes a positive voltage input pin coupled to a power supply, an oscillating output pin, and a negative voltage input pin. The switch includes a first terminal coupled to the oscillating output pin, a second terminal coupled to one terminal of the first capacitor, and coupled to the power supply via the resistor, and a third terminal being grounded. Another terminal of the first capacitor is coupled to the anode of the fist diode and the cathode of the second diode. The cathode of the first diode is grounded. The anode of the second diode is coupled to the positive voltage input pin of the pulse generator, and is coupled to ground via the second capacitor.

Abstract: In one embodiment, a method is provided for preventing reverse input current from flowing into a power source.

Abstract: A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.

Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.

Abstract: An apparatus comprises at least one input connection, at least one output connection, at least one control connection, a voltage converter circuit having an input coupled to the control connection and an output, wherein the voltage converter circuit is configured to provide a voltage at its output that is greater than a voltage present at its input, and at least one switch circuit coupled to the input connection, the output connection, and the output of the voltage converter circuit. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by the voltage converter output. Power to the voltage converter circuit is provided via the control connection, and power to the switch circuit is provided via the output of the voltage converter circuit.

Abstract: A method for providing power to a boost device in a high-speed cable connected between a transmitting data source device and a receiving data sink device is described. The method comprises receiving differential data signals from the data source device in a differential input circuit of the boost device; boosting at least one of the received differential data signals into a boosted differential data signal; transmitting the boosted differential data signal from a differential output circuit of the boost device to the receiving data sink device; and obtaining power to operate at least some of the circuitry of the boost device from the data sink device through its connection with the differential output circuit, for example, providing at least some of the power to operate the processing block. A corresponding high-speed cable is also described.

Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Abstract: A system and method for power control for ASIC device is disclosed. According to an embodiment, the present invention provides a system for adjusting power consumption of an application specific integrated circuit (ASIC) device. The system includes a first buffer that is configured to receive and store data. For example, the first buffer can be characterized by a first buffer level. The method also includes a controller configured to generate a control signal. According to an embodiment, the controller is coupled to the first buffer. The system additionally includes a power supply component, which is configured to receive the control signal and to provide at least at a first voltage and a second voltage. For example, the first voltage and the second voltage are different.

Abstract: An internal voltage generation apparatus for a semiconductor device is disclosed. The internal voltage generation apparatus includes a power-up detector for receiving an external supply voltage and generating a power-up signal, an internal voltage generator for generating a plurality of internal voltages, and an initial level holder including a plurality of transistors for supplying the external supply voltage to the internal voltage generator in response to the power-up signal, and a plurality of passive elements connected in parallel with the transistors, respectively.

Abstract: Circuit topologies and control methods for a power converter and are described.

Abstract: When the fan inserted in the fan header is a 4-pin fan, the control chip outputs PWM signals with different duty factors to the control pin of the fan header, to automatically change the rotary speed of the 4-pin fan. When the fan inserted in the fan header is a 3-pin fan, the control chip outputs the PWM signals whose duty factor changes with temperature of a chip under the fan to control the first power source to provide a voltage to the adjusting circuit. The adjusting circuit rectifies the voltage output from the first power source as an analog voltage signal to the control circuit. The control circuit controls the third power source to output a changeable driving voltage to the power pin of the fan header to control the rotary speed of the 3-pin fan.

Abstract: A system and method for fabricating a self-powering integrated circuit chip having an integrated circuit, which may be a MEMS or CMOS device or the like and a thin film photovoltaic cell stack overlayed thereupon or on the opposite side of the substrate on which the IC is manufactured upon.

Abstract: An integrated circuit (IC) includes at least one programmable digital logic cell that includes first dedicated digital logic cell having a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor configured to perform at least one digital logical function. The first dedicated digital logic cell includes a plurality of nodes including at least one input node and at least one output node that reflects performance of a digital logical function. Programmable tuning circuitry includes at least one tuning input and at least one tuning circuit output. Circuitry for coupling or decoupling the tuning input or tuning circuit output to at least one of the plurality of nodes of the first dedicated digital logical cell is provided, wherein the coupling or decoupling is operable to change the processing speed for the first reprogrammable digital logic cell.

Abstract: A power switch circuit includes a first switch transistor connected to a main power supply, which supplies a first voltage, a second switch transistor connected in series to the first switch transistor and to a backup power supply, which supplies a second voltage. A switch control unit controls activation and deactivation of the first and second switch transistors so that either one of a voltage corresponding to the first voltage and a voltage corresponding to the second voltage is selectively output to a connection node between the first and second transistors. The first switch transistor includes a first diode, which is formed so that a direction from the main power supply toward the connection node defines a forward direction, and a second diode, which is formed so that a direction from the connection node toward the backup power supply defines a forward direction.

Abstract: The internal voltage generation circuit includes an internal voltage enable signal generation unit generating an internal voltage enable signal whose enable pulse width is controlled according to an external voltage. An internal voltage generation unit generates an internal voltage corresponding to a reference voltage according to the internal voltage enable signal. The internal voltage generation circuit generates an internal voltage according to an internal voltage enable signal whose enable pulse width is controlled in response to an external voltage, and thus current consumption is improved, and the internal voltage generation circuit provides a stable internal voltage.

Abstract: A system for activating and deactivating a hardware device including a first stage electronic deactivation unit operative, responsive to a deactivation request, to perform a first deactivation operation including deactivation of a first portion of the hardware device having low wake-up latency at a first time, a second stage electronic deactivation unit including a breaking distance timer activated subsequently to the deactivation request and operative to deactivate a second portion of the hardware device having high wake-up latency at a subsequent second time separated from the first time, and a power management system including a power source and a power supply regulator operative to control the supply of power in accordance with a selectable one of a plurality of regulator settings, selected using a hardware setting selector. Responsive to a wakeup event, the first portion of the hardware device is reactivated and the breaking distance timer is deactivated.

Abstract: An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval.

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

Abstract: A reservoir capacitor array circuit capable of allowing an internal voltage to be maintained stably, comprises a plurality of reservoir capacitors, each of the reservoir capacitors including a switch element which is connected between a power source voltage and a prescribed node and switched in response to a test enable signal which is enabled depending on a test mode signal or whether the fuse is cut or not, and a capacitor connected between the node and a ground voltage.

Abstract: A reference voltage generating circuit includes a resistance dividing circuit formed with resistors connected in series.

Abstract: An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage. A pump stage selector selects the number of charge pump stages to be coupled between an input and output terminal of the variable stage charge pump. The pump stage selector may control a plurality of switches to select the number of stages. For example, two stages may be coupled in parallel and the parallel combination coupled in series to a third stage, resulting in a two stage charge pump. For a three stage charge pump, all three stages are coupled in series.

Abstract: Provided are a clock detector and a bias current control circuit. The clock detector outputs a digital code corresponding to the frequency of an input clock, and the bias current control circuit controls a bias current supplied to an analog circuit according to the digital code output from the clock detector. Accordingly, when the clock detector and the bias current control circuit are used, it is possible to minimize the power consumption of an analog circuit by controlling a bias current supplied to an analog circuit according to a digital code corresponding to the frequency of an input clock.

Abstract: In a power supply apparatus for performing constant current driving of a light emitting diode which is a load circuit, a constant current circuit is disposed on a path for driving the load circuit. A charge pump circuit which is a voltage generating circuit outputs a driving voltage to the light emitting diode. A monitoring circuit monitors the voltage across the two ends of the constant current circuit. This monitoring circuit includes a voltage source which generates a threshold voltage that follows the fluctuation of the voltage at which the constant current circuit can operate stably, compares the voltage across the two ends of the constant current circuit and the threshold voltage generated by the voltage source, and outputs a comparison result Vs to a control unit. The control unit controls the charge pump circuit on the basis of the output of the monitoring circuit.

Abstract: The self-powered detection device comprises at least a non-volatile memory cell (24) and a sensor (16) which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, the memory cell being arranged for storing, by using the electrical power of said electrical stimulus pulse, at least a bit of information relative to the detection by the sensor of at least a first physical or chemical action or phenomenon applied to it with at least a given strength or intensity. The non-volatile memory cell is formed by a FET transistor (T1) having a control gate, a first diffusion (DRN) defining a first input and a second diffusion (SRC) defining a second input.

Abstract: A semiconductor device includes an internal circuit configured to receive a first power supply voltage applied via a first power input terminal through a first power supply path and receive an internal power supply voltage to perform a predetermined circuit operation and an internal power supply voltage generator configured to receive a second power supply voltage for a power circuit applied via a second power input terminal through a second power supply path and generate the internal power supply voltage, wherein the second power supply path is separated from the first power supply path.

Abstract: A semiconductor device includes a semiconductor element including a current mirror circuit, a parasitic resistance formed at the current mirror circuit, and a connection terminal electrically connected to a part of the current mirror circuit via an electric conductor including a bonding wire, the connection terminal being configured to perform input and output relative to an outside of the semiconductor device; wherein a resistance value of the bonding wire is controlled so that a shift of an output electric current of the current mirror circuit based on the parasitic resistance is corrected.

Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.

Abstract: A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of clock domains. Each hardware performance monitor is associated with one of the plurality of clock domains and provides a signal that measures a performance of its respective clock domain temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and used in an advanced power controller to provide adaptive voltage scaling for the integrated circuit system.

Abstract: Systems and methods for providing bias currents to multiple analog circuits are disclosed. An integrated circuit comprises a calibration circuit which compares a high tolerance external component to a plurality of internal components manufactured to span the variability of the process, voltage and temperature. The best fitting internal component is communicated to bias circuits which can select an internal component from a local plurality of internal components with matching desired characteristics. In this manner, analog circuits can be locally biased with the tolerance usually associated with a high tolerance external reference component, without the necessity for a local external reference component.

Abstract: A differential stage circuit is disclosed, which includes a differential circuit, a current source coupled to supply, when activated, an operating current to the differential circuit, and a control circuit coupled to control activation and deactivation of the current source. The differential stage circuit further includes a compensation circuit configured to supply a compensation pulse to the current source when the current source is activated.

Abstract: A High-Definition Multimedia Interface (HDMI) cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An internal voltage adjusting circuit of a semiconductor memory device processes a period from activation to deactivation of a reset bar signal by dividing the period into a first period to a third period. In the first period, a peripheral circuit voltage is stabilized to a lowest value to suppress power consumption. In the second period in which a power source voltage is stabilized, the peripheral circuit voltage is set to a highest value to read out optimum internal voltage values from a fuse circuit in a stable manner. In the third period after reading out the optimum internal voltage values, the peripheral circuit voltage is returned to the lowest value to suppress the power consumption. When the reset bar signal is deactivated, the peripheral circuit voltage is set based on the optimum internal voltage values read out from the fuse circuit.

Abstract: The present invention includes systems, methods and apparatus for continuously, independently and in some cases remotely monitoring the operation of a current interrupter used to test a cathodic protection system, or the cathodic protection system itself, for verification of proper operation. Embodiments of the invention include electronic devices that may be temporarily attached to a current interrupter that is being used to test a cathodic protection system, or directly to the cathodic protection system itself. Embodiments of the invention monitor the activity of an interrupter by sampling the output (voltage and time) to identify the cycle(s) of the interrupter. The invention provides truly independent verification since it does not need to know in advance the sequence or cycle times of the current interrupter being monitored. The information obtained by the invention is output so that it may be provided to a user, displayed, downloaded or stored for future reference.

Abstract: A voltage divider of a voltage regulator system is disclosed utilizing divided diffused resistors. In one embodiment, a feed-forward capacitor network is connected across the resistors and the voltage divider output. The feed-forward capacitor network allows the output to rise and fall quickly with a change in the voltage divider input. Accordingly, an improved frequency response should be obtained utilizing divided diffused resistors.

Abstract: A light-emitting device driving circuit capable of reliably performing emission control on a light-emitting device of a low emission threshold (about 10 mA or less) and capable of correcting a distortion due to the Early effect of a transistor in the drive current supplied to the light emitting device. The light limiting device driving circuit includes a current control unit (101) which controls the value of a main current based on a control voltage, a bias current source (CC1) for subtracting a bias current from the main current, and a switching unit (103) which controls emission of light from the light-emitting device by switching, based on the drive signal, a current obtained by subtracting the bias current from the main current or a current based on the current obtained by the subtraction.

Abstract: A level shift output circuit includes a level shifter interconnecting first and second power supplies that supply first and second voltages, the second being lower than the first voltage. The circuit outputs complimentary first and second output signals responsive to complimentary first and second input signals. High breakdown voltage inverters interconnect the first and second power supplies, and are configured to output a third output signal responsive to a first control signal and the first output signal from the level shifter and output a fourth output signal which is complimentary with the third output signal, responsive to a second control signal complimentary with the first control signal, and the second output signal. P-type transistors interconnect the first power supply and a power supply output node, and respectively supply the first voltage to the power supply output node in response to the fourth output signals from the high breakdown voltage inverters.

Abstract: A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input/output ring voltage. An algorithm produces a specific sequence of pulses of varying width such that the voltage or current delivered to the load from the system plant closely resembles a critical damped step response. The specific pulse width modulation sequence controls a plant that provides a near critical damped step response in one embodiment without a feed-forward or feedback loop physically embodied in the control system thereby reducing the parts cost or control semiconductor production yield cost while enhancing noise immunity and long term reliability of the control system.

Abstract: An integrated circuit with a configurable portion, such as an input/output port, that can be placed in a default configuration prior to actual configuration of the integrated circuit. An external terminal that serves as an output during normal operation is coupled, after power-on of the integrated circuit, to a comparator that senses the voltage level at that external terminal. If the external terminal is at a particular level, a multiplexer is controlled to ignore the state of the normal configuration memory, and to place the configurable input/output port into a default protocol.

Abstract: A bulk bias voltage generating device is configured to generate a first bulk bias voltage in a deep power down mode and a second bulk bias voltage in a normal mode. The first bulk bias voltage comprises an internal voltage level, and the second bulk bias voltage comprises an external voltage level.

Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.

Abstract: An apparatus comprises a voltage regulator including an high side switching transistor and a low side switching transistor. An high side drive controls operation of the high side switching transistor. A low side driver controls operation of the low side switching transistor. A bootstrap capacitor provides an operating voltage to the high side switching driver. The bootstrap capacitor is charged to a predetermined level responsive to a supply voltage. A low side driver drives the low side switching transistor according to a process that charges the bootstrap capacitor to the predetermined level. The process turns on the low side switching transistor for a first predetermined number of cycles and turns off the low side switching transistor for a second predetermined number of cycles. The process is repeated for a predetermined number of times during startup of the voltage regulator when a prebias load is applied to the voltage regulator.

Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Abstract: A device with an in package power supply may be utilized to supply power to other components. As a result, the overall system size may be reduced and economies may be achieved.

Abstract: A High Definition Multimedia Interface (HDMI) cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. A Mobile High-Definition Link (MHL) cable carries high speed data which are multiplexed to achieve smaller connectors with fewer pins. A MHL-to-HDMI cable is proposed which includes an embedded MHL to HDMI format conversion device for demultiplexing the received MHL-formatted signal and outputting an HDMI-formatted signal. The embedded device is powered by a combination of power sources, the power being harvested from the high-speed HDMI signals themselves.

Abstract: Provided is a multi-chip system. The multi-chip system includes a plurality of chips and a power sequence controller. The power sequence controller supplies a plurality of external power voltages to the plurality of chips according to a predetermined sequence.

Abstract: Improved process variation sensors and techniques are disclosed, wherein both global and local variations associated with transistors on an integrated circuit can be monitored. For example, respective circuits for sensing a global process variation, a local process variation between neighboring negative-channel type transistors, and a local process variation between neighboring positive-channel type transistors are disclosed.

Abstract: In accordance with an example embodiment of the present invention, a device comprising one or more porous graphene layers, the or each graphene porous layer comprising a multiplicity of pores. The device may form at least part of a flexible and/or stretchable, and or transparent electronic device.

Abstract: A method and system to facilitate configurable input/output (I/O) termination voltage reference in a transmitter or receiver. In one embodiment of the invention, the transmitter and receiver, each has a termination circuit to select a suitable termination reference voltage based on the desired coupling type. In one embodiment of the invention, the transmitter has a termination circuit coupled with a transmission driver and the transmitter selects only one of a supply voltage, a ground voltage and a half supply voltage as a termination voltage reference of the transmission driver. The receiver has a termination circuit to select either a supply voltage or a ground voltage as a termination voltage reference of the receiver.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: A memory system includes: a high-voltage-supply booster circuit for driving an access control circuit from a low voltage for memory access to a high voltage for memory access by supplying electric charge that is stored in advance to an access control circuit in response to an access start request for a memory cell array; and a low-voltage-supply booster circuit for absorbing excess electric charge when the access control circuit is switched from the high voltage to the low voltage in response to an access end request for the memory cell array.