Abstract: Disclosed herein are a common mode filter capable of implementing high inductance without deterioration of a moisture resistance load, and a method of manufacturing the same. The common mode filter includes: a magnetic substrate; an insulating layer disposed on the magnetic substrate; and a coil electrode layer disposed in the insulating layer, wherein the magnetic substrate has a groove part formed at an edge of an upper surface thereof, and a material of the insulating layer is filled into the groove part.

Abstract: Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch.

Abstract: An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.

Abstract: A method for manufacturing a peripheral circuit of a touch panel includes: printing a radiation curable conductive material on a substrate having a transparent conductive pattern; irradiating the radiation curable conductive material with a radiated ray, in order to cure parts of the radiation curable conductive material; and removing uncured parts of the radiation curable conductive material, in order to form the peripheral circuit.

Abstract: The power conversion apparatus includes an inverter circuit which converts a DC current into an AC current and have a U-phase, V-phase, and w-phase power semiconductor modules, and a capacitor module for smoothing the DC current. Each of the power semiconductor modules is configured separately and connected to a first bus bar. The first bus bar is configured with a first positive side bus bar, a first negative side bus bar, and a first insulation member arranged between the first positive side bus bar and the first negative side bus bar. The first bus bar includes a first to third terminals to which the U-phase, V-phase, and W-phase power semiconductor modules are connected, respectively, and a fourth terminal connected to a terminal of the second bus bar protruding from a surface of sealing material of a second bus bar.

Abstract: A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.

Abstract: A wiring board includes a substrate having an opening portion, multiple electronic devices positioned in the opening portion such that the electronic devices are arrayed in the lateral direction of each of the electronic devices, and an insulation layer formed on the substrate such that the insulation layer covers the electronic devices in the opening portion of the substrate. The substrate has a wall surface defining the opening portion and formed such that the opening portion is partially partitioned and the electronic devices are kept from making contact with each other.

Abstract: A display module 1 of the present invention includes a first board 3, a second board 4, a base film 5, and a circuit member 2. The first board 3 and the second board 4 are bonded together to face with each other. The base film 5 is provided between the first board 3 and the second board 4 and extends outwardly from an end of the first board 3. The base film 5 has an insulating property and the extended portion is bent to an outer surface side of one of the first board 3 and the second board 4. The circuit member 2 is formed on the base film 5.

Abstract: Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed.

Abstract: In a terminal plate circuit in which the bottom surface of the diode is attached to the surface of the terminal plate with solder so as to dissipate the heat of the diode, heat transfer from the diode to the terminal plate is facilitated by removing the air bubbles in the solder during the soldering. A terminal plate circuit configured in such a manner that a metal part of a bottom surface of a diode of surface mounting type is soldered onto a surface of a terminal plate that is larger than the metal part, characterized in that streaks consisting of a plurality of lines that do not intersect with each other are formed on the surface of the terminal plate onto which the diode is to be soldered, whereby air bubbles generated within the solder during the soldering are let to escape from a lower surface of the diode to outside through the streaks. This terminal plate circuit is suitable for the use in a terminal box for solar cell panel.

Abstract: In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Abstract: In a mechanical quantity measuring device (1) having a sensor chip (2) which outputs a sense output (S) corresponding to a mechanical quantity acting on the object to be measured (4), and a flexible wiring board (3) which supports the sensor chip (2) and has a wire (6) to lead out the sense output (S) to outside, and in which in measuring the mechanical quantity, the sensor chip (2) and the flexible wiring board (3) are attached to the object to be measured (4), a cutout (5) is provided on the flexible wiring board (3) near the sensor chip (2) and on the side where the wire (6) is arranged for the sensor chip (2). Thus, change in the sense output (S) with time can be restrained.

Abstract: A semiconductor apparatus includes a test voltage application unit, a first pad and a second pad. The test voltage application unit is configured to apply a test voltage to first and second TSVs in response to a test mode signal. The first pad is configured to output a first test signal outputted from the first TSV. And the second pad is configured to output a second test signal outputted from the second TSV.

Abstract: The multi wireless charging apparatus of the present invention includes a control unit generally controlling a wireless charging procedure; a plurality of wireless charging units electrically connected to the control unit; and folding units connecting between the wireless charging units, the folding units each having a void therein, which passes through both lateral surfaces thereof, and thereby to be folded up or down. Also, in the multi wireless charging apparatus of the present invention, each of the wireless charging units includes a shielding film made of a conductive material, such as conductive paste or ferrite, and formed on a lower surface thereof, for electromagnetic field shielding.

Abstract: A wiring board includes a first wiring line and a second wiring line formed on a substrate, a first land and a second land respectively formed at a connection portion of the first wiring line and the second wiring line. A second wiring line has a longer wiring length than the first wiring line. The land is structured with a wiring pattern of a single wiring line. The wiring board also includes a first pad electrode and a second pad electrode respectively formed on the first land and a second land through an insulating film, a first interlayer connection via and a interlayer connection via embedded in the insulating film and electrically connecting the land to the pad electrode. And a wiring length of the wiring pattern of the first land is longer than the wiring length of the wiring pattern of the second land.

Abstract: An input device includes a flexible base, a sensor member that is provided on the surface of the flexible base and can detect the operation position of a finger, connection portions that are provided on a back of the flexible base, a printed circuit board of which an area is smaller than the area of the flexible base and which includes terminal portions on the surface thereof facing the back, and an electronic component that is mounted on a surface of the printed circuit board opposite to the surface of the printed circuit board on which the terminal portions are provided and is electrically connected to the terminal portions. The flexible base and the printed circuit board are bonded to each other with an adhesion layer interposed therebetween so that the connection portions come into contact with the terminal portions.

Abstract: An LTCC carrier composed of thermosetting polymer, woven glass fiber and ceramic has gold over nickel contact pads on top and bottom surfaces and conductive vias therethrough between aligned pairs of top and bottom pads. The vias prevent undesirable inductive paths from limiting high frequency operation of the circuitry. Solder deposits on the top pads attach the LTCC component, which is further secured to the carrier by epoxy, thus improving resistance to thermal stress and mechanical shock. A slot through the carrier body between top and bottom surfaces further reduces thermal stress and mechanical shock. Metallized castellations on opposite carrier sides provide additional surface area for reflow solder joints with the PCB, and a means for visually inspecting the solder joint quality. A gap in the metallization on the top layer of the carrier prevents solder spreading during multiple soldering cycles, which may result in poor solder joints.

Abstract: A method of manufacturing a component-built-in wiring substrate which exhibits excellent reliability, through improvement of adhesion between a resin filler and a core substrate, is provided. In some embodiments the method comprises a core substrate preparation step for preparing a core substrate, an accommodation-hole forming step for forming an accommodation hole in the core substrate, and a through-hole forming step for forming through-holes. In a plating-layer forming step, a plating layer is formed on an inner wall surface of the accommodation hole and plating layers are formed on the inner wall surfaces of the through-holes, which become through-hole conductors each having a hollow. In an accommodation step, a component is accommodated in the accommodation hole. In a resin charging step, a resin filler is filled into a gap between component side-surfaces and the inner wall surface of the accommodation hole and into the hollows.

Abstract: A shielding arrangement for preventing AM radio interference when a wireless charger is used in a vehicle has a plurality of parallel conductors arranged at a distance from one another responsive to a frequency desired to be attenuated. An interconnection arrangement includes a solid conductive junction and connects the conductors to one another without forming loops, and to ground. The conductors are traces disposed on a PCB. Additional parallel conducts are disposed on the other side of the PCB at an orthogonal orientation with respect to the first conductors. The spacing between the conductors is determined in response to the frequency desired to be attenuated, as well as frequencies thereabove that are desired to be propagated therethrough, such as mobile telephone signals. The solid conductive junction that is disposed on the printed circuit board is electrically and thermally conductive, such as copper.

Abstract: A portable battery charging apparatus having two or more battery charging interfaces on separate panels. Wires electrically couple the battery charging apparatuses to a charger unit. The wires are routed for flexibility to fold and unfold the panels. The battery charging apparatuses and the charging unit may be connected to a flexible material. Each battery charging apparatus may include two or more charging jacks for the same or different batteries. The charger unit has an input to receive a power source, and an output to power a further device, for example a further battery charging apparatus.

Abstract: A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Abstract: Some novel features pertain to a substrate that includes a first core layer, a second core layer laterally located to the first core layer in the substrate, a first inorganic core layer (e.g., glass, silicon, ceramic) laterally positioned between the first core layer and the second core layer, the first inorganic core layer configured to be vertically aligned with a die configured to be coupled to the substrate, and a dielectric layer covering the first core layer, the second core layer and the first inorganic core layer. In some implementations, the first inorganic core layer has a first coefficient of thermal expansion (CTE), the die has a second coefficient of thermal expansion, and the first core layer has a third coefficient of thermal expansion (CTE). The first CTE of the first inorganic core layer closely matches the second CTE of the die in order to reduce the likelihood of warpage.

Abstract: A light emitting device in which a plurality of LED chips are arranged. Each of the plurality of LED chips include a light emitting region that is formed on a substrate, a first pad electrode that is formed on the substrate, and a through-hole that penetrates the substrate. First wiring that passes through the through-hole of one LED chip and the through-hole of an adjacent LED chip, and electrically connects the first pad electrode of the one LED chip and the first pad electrode of the adjacent LED chip is provided. The tip-end parts of the first wiring that have passed through the through-holes have, at a cross section cut at a plane that is parallel with a principal surface of the substrate, a larger cross-sectional area than the cross-sectional area of the first wiring inside the through-holes.

Abstract: A manufacturing method includes the follow steps. Firstly, a carrier is provided. Then, a plurality of traces are formed on the carrier. Then, a trace molding compound layer is formed on the carrier by a first molding process. Then, the carrier is removed from the trace molding compound layer to expose an etched surface of the trace molding compound layer and trace upper surfaces of the traces. Then, at least a chip is disposed on the etched surface of the trace molding compound layer and the chip is connected to the trace upper surfaces. Then, a chip molding compound layer is formed on the etched surface by a second molding process substantially similar to the first molding process, wherein the chip molding compound layer and the trace molding compound layer are formed of substantially the same molding compound material.

Abstract: A package includes a main unit having formed therein a through hole that penetrates the package from a first surface to a second surface; and a connection terminal that is provided inside the through hole. The second surface is a bottom surface of the main unit, and has an electric circuit incorporated therein. The connection terminal is electrically connected to the electric circuit incorporated in the main unit, and configured to be contactable by an insertion target that is inserted in the through hole from a side of an inserting direction.

Abstract: A planar light source apparatus includes a light source; a flexible printed circuit (FPC) having a wiring part that extends from a light source mounting part having the light source; a rear frame that accommodates the light source and the FPC; and a driver substrate, which is arranged on a backside that is an opposite side of an inner surface of the rear frame, and which has a connector configured to connect the FPC, wherein an end portion of the wiring part is extracted to the backside through an opening hole formed in the rear frame and is connected to the connector, and wherein the backside of the rear frame has a protrusion portion, which is arranged in the vicinity of an insertion slot of the connector, and is which formed to be substantially level with an arrangement position of the insertion slot.

Abstract: A multi-chip module (MCM) that includes alignment features is described. This MCM includes at least two substrates having facing surfaces with positive features disposed on them. Note that a given positive feature on either of the surfaces protrudes above the surface. Furthermore, the two substrates are mechanically coupled by these positive features. In particular, a given one of the positive features on one of the surfaces mates with a given subset of the positive features on the other of the surfaces. Additionally, the given subset of the positive features includes two or more of the positive features.

Abstract: An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

Abstract: A circuit substrate includes: a laminate substrate in which a conductive layer and an insulating layer are laminated; a filter chip that has an acoustic wave filter and is provided inside of the laminate substrate; and an active component that is provided on a surface of the laminate substrate and is connected with the filter chip, at least a part of the active component overlapping with a projected region that is a region of the filter chip projected in a thickness direction of the laminate substrate.

Abstract: A printed board is provided, which includes at least a first connecting electrode and a second connecting electrode. A solder is provided over the first connecting electrode and the second connecting electrode, and a chip component is provided over the solder. The chip component includes a first terminal electrode and a second terminal electrode. The first connecting electrode is overlapped with the first terminal electrode and is electrically connected to the first terminal electrode through the solder. The second connecting electrode is overlapped with the second terminal electrode and is electrically connected to the second terminal electrode through the solder. Two corner portions of each of the first connecting electrode and the second connecting electrode are overlapped with two corner portions of each of the first terminal electrode and the second terminal electrode.

Abstract: An electronic device is presented for electrical connection between a first pad contact of an integrated circuit component and a target contact positioned substantially in a first plane of a target platform. The electronic device includes a first surface substantially parallel to the first plane and a second surface below the first surface substantially parallel to the first plane. The first surface includes a first contact region configured to connect to the first pad contact when the electronic device is connected between the first pad contact and the target contact. The second surface includes a second contact region configured to connect to the target contact when the electronic device is connected between the first pad contact and the target contact. The electronic device further includes a multitude of electrically passive elements connected between the first and second contact regions.

Abstract: A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; connecting a base component directly to the base substrate; mounting a stack component over the base component; attaching a flattened exposed interconnect directly on the stack component; and applying an encapsulant over the stack component with a portion of the flattened exposed interconnect exposed.

Abstract: A multilayer ceramic capacitor includes flat inner electrodes that are laminated on each other. An interposer includes a substrate that is larger than the multilayer ceramic capacitor. A first mounting electrode to mount the multilayer ceramic capacitor is located on a first principal surface of the substrate, and a first external connection electrode for connection to an external circuit board is located on a second principal surface. A recess is located in a side surface of the interposer. A connecting conductor is located in the wall surface of the recess. The connecting conductor is located at a position spaced apart by a predetermined distance from the side surface of the interposer.

Abstract: A multilayer ceramic capacitor includes flat-shaped inner electrodes that are laminated. An interposer includes an insulating substrate that is larger than contours of the multilayer ceramic capacitor. A first mounting electrode that mounts the multilayer ceramic capacitor is located on a first principal surface of the insulating substrate, and a first external connection electrode for connection to an external circuit board located on a second principal surface. The multilayer ceramic capacitor is mounted onto the interposer in such a way that the principal surfaces of the inner electrodes are parallel or substantially parallel to the principal surface of the interposer, that is, the first and second principal surfaces of the insulating substrate.

Abstract: A card-type information recording medium including a PCB that has a loop antenna pattern and a routing pattern formed on the top surface and the bottom surface thereof through the use of an etching process, an NFC communication unit and a USIM card unit that are horizontally mounted on the top of the PCB, and a molding material that is formed on the top of the PCB so as to cover the NFC communication unit and the USIM card unit.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a substrate having (i) a first side configured to receive a semiconductor die and (ii) a second side disposed opposite to the first side. The substrate comprises a printed circuit board material. The apparatus further comprises an interposer that is (i) disposed in the substrate and (ii) configured to electrically couple the first side of the substrate and the second side of the substrate. The interposer comprises a semiconductor material.

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Abstract: A moisture-resistant electronic device includes at least one electronic component at least partially covered by a moisture-resistant coating. The moisture-resistant coating may be located within an interior of the electronic device. The moisture-resistant coating may cover only portions of a boundary of an internal space within the electronic device. A moisture-resistant coating may include one or more discernible boundaries, or seams, which may be located at or adjacent to locations where two or more components of the electronic device interface with each other. Assembly methods are also disclosed.

Abstract: A solder ball which suppresses generation of voids in a joint, excels in a thermal fatigue property, and can also obtain a good drop impact resistance property, and an electronic member using the same are provided. The solder ball is formed of a Sn—Bi type alloy containing Sn as a main element, 0.3 to 2.0 mass % of Cu, 0.01 to 0.2 mass % of Ni, and 0.1 to 3.0 mass % of Bi, and an intermetallic compound of (Cu, Ni)6Sn5 is formed in the Sn—Bi alloy so that the generation of voids in the joint when being jointed to an electrode is suppressed, a thermal fatigue property is excellent, and a good drop impact resistance property can also be obtained.

Abstract: An electrically conductive material includes a liquid gallium alloy mixed with multiple solid particles, so as to form an electrically conductive material in which solid and liquid coexist. The electrically conductive material is disposed between and electrically connecting a first conductor and a second conductor. The first conductor is disposed on a first electronic element, and the second conductor is disposed on a second electronic element.

Abstract: A power conversion device is provided. The power conversion device includes a printed wiring board assembly, a grounding member, and a plurality of insulating struts. The printed wiring board assembly includes a printed circuit board and a plurality of electronic components. The printed circuit board has a plurality of through holes. The electronic components are disposed on the printed circuit board. The insulating struts correspond to the through holes and physically connect and electrically insulate the printed circuit board and the grounding member.

Abstract: A contact structure and assembly and a method for manufacturing the same for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: An integrated silicone for protecting electronic devices includes a base resin, a thermal initiator, and a photoinitiator.

Abstract: A suspension board with circuit includes an electronic element, and a mounting portion having a terminal portion electrically connected to the electronic element. The electronic element and the mounting portion are bonded to each other via an adhesive containing a metal ion scavenger.

Abstract: Electronic devices to output signals at different frequencies are mounted to a circuit board that has a group of layers, where the group of layers include reference plane layers and signal layers between the reference plane layers. A first signal layer has conductive traces having a first dimension to communicate the signals at a first frequency, and a second signal layer has conductive traces having a second, different dimension to communicate signals at a second, different frequency. The first and second signal layers are successive layers without any reference plane layer in between the first and second signal layers.

Abstract: A component built-in module of the present invention includes: a flexible substrate that includes a first surface and a second surface on an opposite side of the first surface, the first surface including a concave part recessed in a direction from the first surface toward the second surface; a plurality of electronic components that are mounted on the first surface, mounting heights of the electronic components from the first surface to respective upper surfaces of the electronic components differing from each other; and a resin that seals the first surface. Among the plurality of electronic components, at least an electronic component having a highest mounting height is mounted in the concave part.