Abstract: The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 ?m, and a height difference between the substrate and the edge ring is less than about (+/?) 300 ?m. The resistivity of the ring is less than about 50 Ohm-cm.
Type:
Grant
Filed:
February 20, 2017
Date of Patent:
June 29, 2021
Assignee:
Applied Materials, Inc.
Inventors:
Olivier Joubert, Jason A. Kenney, Sunil Srinivasan, James Rogers, Rajinder Dhindsa, Vedapuram S. Achutharaman, Olivier Luere
Abstract: A vertical wafer boat has an upper boat segment and a lower boat segment, with the upper boat segment configured to removably mount on the lower boat segment, and to receive one or more semiconductor substrates. The lower boat segment includes a top plate, a first set of adiabatic plates, and a second set of adiabatic plates. One or more posts connect the top plate, the first set of adiabatic plates, and the second set of adiabatic plates. The first set of adiabatic plates include a first set of gaps separating a first plurality of sections; the second set of adiabatic plates include a second set of gaps separating a second plurality of sections; and the first set of adiabatic plates and the second set of adiabatic plates are interleaved.