With Field Effect Produced By Insulated Gate (epo) Patents (Class 257/E29.255)
E Subclasses
- Vertical transistor (EPO) (Class 257/E29.274)
- With multiple gates (EPO) (Class 257/E29.275)
- With supplementary region or layer in thin film or in insulated bulk substrate supporting it for controlling or increasing voltage resistance of device (EPO) (Class 257/E29.276)
- Characterized by drain or source properties (EPO) (Class 257/E29.277)
- For preventing leakage current (EPO) (Class 257/E29.28)
- For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO) (Class 257/E29.281)
- With light shield (EPO) (Class 257/E29.282)
- With supplementary region or layer for improving flatness of device (EPO) (Class 257/E29.283)
- With drain or source connected to bulk conducting substrate (EPO) (Class 257/E29.284)
- Silicon transistor (EPO) (Class 257/E29.285)
- Characterized by insulating substrate or support (EPO) (Class 257/E29.295)
- Comprising Group III-V or II-VI compound, or of Se, Te, or oxide semiconductor (EPO) (Class 257/E29.296)
- Comprising Group IV non-Si semiconductor materials or alloys (e.g., Ge, SiN alloy, SiC alloy) (EPO) (Class 257/E29.297)
- Characterized by property or structure of channel or contact thereto (EPO) (Class 257/E29.299)