Abstract: There is provided a dry etching method for forming wiring trenches in a first insulating layer and in a second insulating layer provided thereon. First, the second insulating layer is etched partway under first etching conditions using resist as a mask (first etching step). Next, the remnant of the second insulating layer and the first insulating layer are etched under second etching conditions different from the first etching conditions, without changing the etching conditions (second etching step).

Abstract: The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

Abstract: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

Abstract: A method for forming a pattern in a semiconductor device includes forming an etch target layer comprising metal over a substrate. A hard mask pattern is formed over the etch target layer. The etch target layer is etched to form a pattern such that a line width of the etch target layer is smaller than a line width of the hard mask pattern.

Abstract: An exposure mask and a method for forming a gate using the same are provided. A recess is formed by using a recess exposure mask with an isolated light transmitting pattern so that the recess may be formed only on an active region, and an edge of the active region is protected from damage during a recess forming process. Accordingly, production time and expense are reduced, yet device productivity is improved.

Abstract: The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which particles with a pointed shape are generated is formed; forming an inter-layer insulation layer with a poor step coverage on the metal plate electrode, the particles with the pointed shape and a surface of the substrate in the peripheral region; etching a portion of the inter-layer insulation layer, thereby exposing predetermined portions of lateral sides of the particles with the pointed shape; selectively removing the exposed portions of the particles with the pointed shape to separate top portions of the particles with the pointed shape from the inter-layer insulation layer; and planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process.

Abstract: An etching method is described, including a first etching step that uses a first etching gas including a first fluorinated hydrocarbon compound, and a second etching step that uses a second etching gas including a second fluorinated hydrocarbon compound. The hydrogen content in the first fluorinated hydrocarbon compound is lower than that in the second fluorinated hydrocarbon compound, such that the after-etching-inspection (AEI) critical dimension is smaller than the after-development-inspection (ADI) critical dimension.

Abstract: A method of manufacturing a semiconductor device according to the invention is an effective technique for ensuring a sufficient process margin and enabling the formation of a fine pattern in a peripheral circuit region. The method includes forming an anti-reflective layer with a varying thickness in a peripheral circuit region and a cell region, and then over-etching the anti-reflective layer in the peripheral circuit region. The method is capable of improving the data processing speed of a semiconductor device and therefore increases the device efficiency.

Abstract: The invention relates to a method of realization of a sacrificial layer, including the steps of: lithography of a resin deposited on a substrate in order to supply a lithographed resist pattern on a substrate zone, the zone having a given size and a given form, the pattern occupying a given volume, annealed according to a thermal cycle of the lithographed resist pattern, the method being characterised in that it includes, according to the resin, the determination of the size and of the form of said zone of the substrate, and the determination of the volume of the resin deposited on said zone so that the thermal cycle annealing supplies a profile chosen from among the following profiles: a planarising domed profile and a “double air gap” profile.

Abstract: A semiconductor device having sufficient sensitivity, strength, and the like and a method for fabricating such a semiconductor device. In a method for fabricating a semiconductor device which detects the shape of a skin surface by detecting capacitance formed between the skin surface and a conductive film between which a passivation film including a silicon nitride film and a polyimide film is, the polyimide film with a thickness of not less than 400 nm nor more than 700 nm is formed at a curing temperature higher than or equal to 350° C. and lower than or equal to 380° C. as a top layer of the semiconductor device. When the polyimide film is cured, nitrogen gas or the like is made to flow in at a flow rate of 110 liters/minute or more. By adopting this method, a very thin passivation film is formed on a semiconductor device and a semiconductor device having sufficient sensitivity, strength, and the like can be fabricated.

Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first trench pattern, forming spacers over sidewalls of the first trench pattern, etching a bottom portion of the first trench pattern using the spacers as a barrier to form a second trench pattern, performing an isotropic etching on the second trench pattern to round sidewalls of the second trench pattern and form a bulb pattern, and forming a gate over a recess pattern including the first trench pattern, the rounded second trench pattern and the bulb pattern.

Abstract: By providing a silicon cap layer on a compressive silicon nitride layer, the diffusion of nitrogen into sensitive resist material may be efficiently reduced, while the silicon may be converted into a highly compressive silicon dioxide in a later manufacturing stage. Consequently, yield loss due to contact failures during the formation of semiconductor devices requiring differently stressed silicon nitride layers may be reduced.

Abstract: There is disclosed a manufacturing method in which depths of individual liquid chambers can be set to be small. The manufacturing method is a manufacturing method of a liquid discharge head having a liquid chamber which communicates with a discharge port for discharging a liquid, and includes: etching a first Si layer of an SOI substrate by use of an insulating layer as an etching stop layer to form the liquid chamber at the first Si layer, the SOI substrate being constituted by the first Si layer, the insulating layer and a second Si layer in this order; and removing a part or all of the second Si layer.

Abstract: Anisotropic dry etching uses a hard mask as an etching mask and a mixture of fluorocarbon, oxygen and rare gas as an etching gas, and effects etching of a dielectric film and deposition of deposits on the hard mask for suppressing reduction of the thickness of the hard mask. A higher deposition rate of the deposits is employed during the middle stage of the etching than during the initial stage and final stage of the etching. The higher deposition rate suppresses the reduction of the remaining thickness of the hard mask especially during the middle stage.

Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Abstract: A method of forming a via hole reaching a bonding pad in a wafer, which have a plurality of devices on the front surface of a substrate and bonding pads on each of the devices, by applying a pulse laser beam from the rear surface of the substrate, comprising the steps of: affixing a protective member to the front surface of the substrate; grinding the rear surface of the substrate having the protective member affixed to the front surface to reduce the thickness of the wafer to a predetermined value; forming via holes in the substrate by applying a pulse laser beam from the rear surface of the substrate of the wafer having the predetermined thickness; and etching the wafer having the via holes in the substrate from the rear surface of the substrate.

Abstract: A non-volatile memory is described. A substrate comprising a stacked layer is provided. A sacrificial layer is deposited and patterned to form a first opening. A first spacer is formed on sidewalls of the first opening, and the stacked layer is etched using the first spacer as a first mask to form a second opening. An isolation layer is formed in a portion of the first and the second openings, and a conductive filling layer is formed thereon. The stacked layer is etched using a portion of the conductive filling layer as a second mask.

Abstract: A bias correction level can be defined with an improved efficiency when a transfer pattern of a hole is formed, so that the hole can be stably formed as originally designed. When a hole pattern is formed over a substrate, correction reference holes 103 existing in a region 113, which is capable of affecting a formation of a correction target hole 101, is extracted, and a bias correction level employed in the formation of the correction target hole 101 is defined, in accordance with a two-dimensional arrangement of the extracted correction reference holes 103.

Abstract: A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.

Abstract: A method of forming a semiconductor device is provided. An interlayer dielectric is formed on a substrate. A di-block polymer layer that includes a plurality of first polymer blocks and a plurality of second polymer blocks is formed on the interlayer dielectric. The di-block polymer layer is divided into a first phase to which the first polymer blocks are bound and a second phase to which the second polymer blocks are bound. The second phase is removed so that at least part of the first phase remains in place, where the remaining first phase defines at least part of a pore. The interlayer dielectric that is exposed beneath the pore is etched to form an opening. The opening may have a smaller width than the minimum feature size that a photolithography process is capable of resolving. As a result, a linewidth of an electrode that may be formed to fill the opening may be reduced.

Abstract: A method of manufacturing a semiconductor device, has applying perhydro polysilazane to a substrate; and immersing at least the surface of said substrate to which perhydro polysilazane is applied in a mixture containing water heated to 120 degrees C. or higher to which ultrasound is applied, thereby modifying the perhydro polysilazane into silicon oxide.

Abstract: The method for forming a multi-stage recess in a layer structure comprises forming a photo-resist film atop a layer structure; a first step (49, 70) of etching the layer structure through an opening of the photo-resist film used as a mask, for forming a first stage of the recess; a step of widening the opening of the photo-resist film after the first etching step, for producing a widened opening of the photo-resist film, and a second step (58, 72) of etching the layer structure through the widened opening of the photo-resist film for forming a second stage of the multi-stage recess.

Abstract: Embodiments relate to an image sensor, and in particular to a manufacturing method of an image sensor for preventing an undercut phenomenon in an etching process so that the salicidation of a pixel area can be prevented. Embodiments relate to a manufacturing method of an image sensor for preventing an undercut according to embodiments including forming plasma-enhanced tetra ethyl ortho silicate (PE-TEOS) films in a non-salicide area and a salicide area defined over a semiconductor substrate using a CVD process. A photoresist pattern may be formed covering the salicide area over the PE-TEOS films. A nitridation process may be performed over the PE-TEOS films formed over the non-salicide area using plasma. The photoresist pattern is removed. The non-nitrided PE-TEOS films of the PE-TEOS films may be removed using an etching process.

Abstract: A method is used for processing a structure of a semiconductor component. The structure has at least one partial structure to be etched, in particular a sublithographic partial structure. The at least one partial structure has at least one structure to be etched with at least one lateral etch stop to which at least one mask is applied in such a way that at least one lateral etch stop is covered by the mask and afterward at least one of the structures to be etched is etched away isotropically as far as at least one etch stop using the mask. The at least one mask and the at least one etch stop are then removed.

Abstract: In one aspect, a method of manufacturing a semiconductor package includes providing a semiconductor substrate which includes a plurality of semiconductor chips and a scribe lane defined between the semiconductor chips, forming a trench within the scribe lane, filling the trench with a photolytic polymer, grinding a back side of the semiconductor substrate including the photolytic polymer within the trench, and radiating light onto a front surface of the semiconductor substrate to dissolve the photolytic polymer.

Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Abstract: By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.

Abstract: A semiconductor device manufacturing method that includes depositing a first insulating film on a semiconductor substrate, etching a part of the first insulating film, and performing UV irradiation to the first insulating film.

Abstract: A fuse region and a wiring region are defined on a base to form a fuse in the fuse region of the base. A first insulation film is formed on the base and the fuse. After a first contact opening is formed in the first insulation film in the wiring region, a first plug is formed by filling a conductive material in the first contact opening. A second insulation film is formed on the first insulation film. A second contact opening, in which the first plug is exposed, and a stopper opening, in which the first insulation film of the fuse region is exposed, are formed in the second insulation film. A second plug is formed by filling the second contact opening with a conductive material and a stopper film is formed by filling the stopper opening with conductive material.

Abstract: A method for manufacturing an image sensor according to embodiments includes forming a transistor over a substrate. A protective layer including boron (B) may be formed, covering the transistor formed over the substrate. The protective layer including the boron may be annealed to move foreign substances including the boron to the surface of the protective layer. The surface of the protective layer including the foreign material may be removed. An oxide protective layer may be formed over the protective layer including the boron where the foreign substance is removed.

Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.

Abstract: The disclosure relates to a method for producing a microelectronic device comprising one or more Si1-zGez-based semiconductor wire(s) (with 0<z?1), including the steps of: a) thermal oxidation of at least a portion of a Si1-xGex-based semiconductor layer (with 0<x<1) resting on a support, so as to form at least one Si1-yGey-based semiconductor zone (with 0<y<1 and x<y), b) lateral thermal oxidation of the sides of the second Si1-yGey-based semiconductor zone so as to reduce the second zone in at least one direction parallel to the main plane of the support and to form one or more Si1-zGez-based semiconductor wire(s) (with 0<y<1 and y<z).

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: A method for manufacturing a semiconductor device includes: a) forming a first single-crystalline semiconductor layer having a higher etching selection ratio than a semiconductor substrate, in a manner covering an exposed part of a single-crystalline region on an active surface of the semiconductor substrate; b) forming a second single-crystalline semiconductor layer having smaller etching selection ratio than the first single-crystalline semiconductor layer, in a manner covering the first single-crystalline layer; c) removing and opening the second single-crystalline semiconductor layer and the first single-crystalline semiconductor layer within a region, the region being adjacent to an element region formed of a part of the second single-crystalline semiconductor layer and sandwiching the element region, so as to form a recess for a support, the recess exposing the semiconductor substrate; d) forming a support precursor layer over the active surface of the semiconductor substrate in a manner filling the rec

Abstract: A method of forming a via hole reaching a bonding pad in a wafer having an insulating film constituting a plurality of devices on the front surface of a substrate and bonding pads on each of the devices by applying a pulse laser beam to the rear surface of the substrate, the method comprising the steps of: forming a non-through hole reaching the insulating film formed on the substrate by applying a pulse laser beam to the rear surface of the substrate; forming an insulating film on the inner wall of the hole which is formed in the substrate by the first step; and forming a via hole reaching a bonding pad by applying a pulse laser beam to the hole having the insulating film which is formed on the inner wall by the insulating film forming step.

Abstract: A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.

Abstract: A method and superalloy component for depositing a layer of material onto gas turbine engine components by atomic layer deposition. A superalloy component may have a ceramic thermal barrier coating on at least a portion of its surface, comprising a superalloy substrate and a bonding coat; and aluminum oxide (Al2O3) layer may be deposited on top of an yttria-stabilized zirconia layer and form a bonding coat by atomic layer deposition. The yttria-stabilized zirconia layer may have a plurality of micron sized gaps extending from the top surface of the ceramic coating towards the substrate and defining a plurality of columns of the yttria-stabilized zirconia layer. Also, atomic layer deposition may be used to lay an aluminum oxide (Al2O3) layer over a tantalum oxide (Ta2O5) layer on a silicon-based substrate.

Abstract: A semiconductor device has multi-layered interlayer insulating layers 3 formed on a semiconductor substrate 1, and wirings 4 formed in the interlayer insulating layers 3. The interlayer insulating layers 3 are composed of porous bodies having fine columnar pores and parent-material regions consisting mainly of silicon oxides surrounding the fine pores. The wirings 4 are composed of structures wherein columnar substances containing aluminum are dispersed in a base material containing silicon, or regions wherein an electrically conductive material is introduced in a portion of the porous bodies. The average diameter of the fine pores in the porous bodies is 1 nm or larger and 10 nm or smaller, and the average distance between the fine pores is 3 nm or larger and 15 nm or smaller. The fine pores in the porous bodies is formed perpendicularly, or substantially perpendicularly to the film surface on a semiconductor substrate 1.

Abstract: To provide a wafer support and a semiconductor substrate processing method by which dopants released from a rear surface of a semiconductor substrate can be adequately restrained from reaching a top surface of a semiconductor substrate and a reaction gas can be restrained from reaching a rear surface of the semiconductor substrate.

Abstract: A method of forming a semiconductor device includes loading a semiconductor substrate into a reaction chamber, and providing metal organic precursors including hafnium and zirconium into the reaction chamber to form hafnium-zirconium oxide (HfxZr1-xO; 0<X<1) with a tetragonal crystalline structure on the semiconductor substrate. Related structures are also discussed.

Abstract: Disclosed herein is a method of forming an inductor in a semiconductor device, the method including forming an etching-prevention film, a first interlayer insulating film, and a first hard mask film over a silicon semiconductor substrate in this sequence; selectively etching the first hard mask film to form a hole; forming a second interlayer insulating film over the first hard mask film; forming a second hard mask film over the second interlayer insulating film; forming a photoresist pattern having a trench forming opening over the second hard mask film; removing a part of the second hard mask film and a part of the second interlayer insulating film by using the photoresist pattern as an etching mask, to form a first trench in the second interlayer insulating film; removing the photoresist pattern and polymers produced in the first trench by ashing and cleaning process; etching the second interlayer insulating film by using the second hard mask film as an etching mask until the first hard mask film is expose

Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.

Abstract: An object is to provide a technique for manufacturing an insulating layer with favorable withstand voltage. Another object is to provide a technique for manufacturing a semiconductor device having an insulating layer with favorable withstand voltage. By subjecting a semiconductor layer or semiconductor substrate mainly containing silicon to a high density plasma treatment, an insulating layer is formed on a surface of the semiconductor layer or a top surface of the semiconductor substrate. At this time, the high density plasma treatment is performed by switching a supply gas in the middle of the treatment from a gas containing a rare gas, oxygen, and hydrogen, to a gas containing a rare gas and oxygen.

Abstract: A method of forming a nonsalicide region in a semiconductor device includes depositing silicon oxide and photoresist on a semiconductor substrate to form a salicide prevention layer and a photoresist layer, respectively, patterning the photoresist layer using a photolithography process to partition the salicide prevention layer into a nonsalicide region and a silicide region, reacting a nitrogen gas of a plasma state to the nonsalicide region, depositing metal on the substrate having the nonsalicide region to form a metal layer, removing the metal layer on the nonsalicide region using etchant. The nonsalicide region is formed with a nitric oxide layer when reacting a nitrogen gas of a plasma state, thereby preventing the formation of undercuts during wet etch process.

Abstract: A first hard mask is formed on a polysilicon film or a target member to be etched, on which a second hard mask composed of amorphous silicon is formed. Ions of boron or the like are implanted into a desired portion of the second hard mask, and then the first hard mask is etched with a mask of the second hard mask. Only the portion not ion-implanted of the second hard mask is etched off by wet etching. A sidewall film is formed on sidewalls of the first hard mask, and then the first hard mask having an upper portion exposed, not covered with the second hard mask is selectively etched off.

Abstract: In a method of manufacturing a semiconductor device, a polysilicon layer doped with impurities is formed on a front side and a backside of a substrate. An insulation layer is formed on the substrate having the polysilicon layer to cover the polysilicon layer on the backside of the substrate. The insulation layer on the front side of the substrate is partially etched to partially expose the front side of the substrate. An oxidation process using oxygen radicals is then carried out to form an oxide layer on the exposed front side of the substrate Thus, when the oxidation process is carried out, the insulation layer prevents impurities in the polysilicon layer on the backside of the substrate from being outgassed. As a result electrical characteristics of the transistor formed on the front side of the substrate may not be deteriorated.