Abstract: A method for forming a poly-silicon film, using sequential lateral solidification (SLS) by laser irradiation through an optical device to pattern the laser beam and provide a periodic energy profile on the edges of transparent regions so as to widen the poly-silicon grains and achieve grain size uniformity. The optical device comprises a plurality of first transparent regions with a length of L, wherein at least one side of the edge of each of the first transparent regions has a first periodic shape.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique of a semiconductor device by which a lithography step that uses a photoresist is simplified is provided. A manufacturing cost is reduced and throughput is improved. An irradiation object is formed over a substrate by sequentially stacking a first material layer and a second material layer. The irradiation object is irradiated with a first laser beam that is absorbed by the first material layer and a second laser beam that is absorbed by the second material layer so that the laser beams overlap. A part or all of the region irradiated with an overlap part of the laser beams is ablated to form an opening.

Abstract: A substrate processing apparatus may include a processing chamber including a plasma generating unit arranged in an upper region thereof. A grid system, which may extract ions from plasma formed by the plasma generating unit and may accelerate the ions to have substantially uniform directivity. The grid system may be positioned below the plasma generating unit. A reflector may be arranged below the grid system and may include parallel reflecting plates for converting the ions accelerated from the grid system into neutral beams.

Abstract: A photovoltaic device optical system for enhanced light harvesting with a transparent layer of dielectric material having on one side an array of micro-lenses and on the opposite side a metal reflective film with an array of openings. The micro-lenses focus direct sunlight impinging thereon through the openings, to separate direct sunlight and diffuse sunlight. The photovoltaic device has a first photovoltaic cell system for the exploitation of the direct sunlight located in the opposite hemi-space of the micro-lenses array with respect to the plane of the openings array and a second photovoltaic cell system for the exploitation of diffuse sunlight, located in the same hemi-space containing the micro-lenses array with respect to the plane of the openings array.

Abstract: In a SiC pn diode, the lifetime is controlled by electron beam irradiation of about 3×1013 cm?2 or more. As a result of the life time control, as shown by a current-voltage characteristic (K10) in FIG. 1, the current started to flow at about 32 V and the on-voltage at an applied current of 100 A was 50 V in the SiC pn diode. In this case, the SiC pn diode has a resistance of 0.5? when the SiC pn diode is turned on. The conducting region of the SiC pn diode is 0.4 cm2, and is reduced to 0.2 ?cm2 by increasing the on-resistance by the lifetime control. Therefore, for instance, in an electric circuit device using a diode and a resistor connected in series in prior arts, the resistor can be eliminated.

Abstract: Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate.

Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.

Abstract: An image sensor includes first to fourth image sensing sections symmetrically aligned in a form of a 2×2 matrix, first to fourth pixel arrays aligned in the first to fourth image sensing sections, respectively, in adjacent to each other, and first to fourth peripheral circuit parts aligned at peripheral portions of the first to fourth image sensing sections. A middle-size CMOS image sensor is provided that is suitable for the available field size of conventional photo equipment, so the manufacturing cost may be minimized and price competitiveness may be maximized while providing high-quality images with high pixel resolution.

Abstract: A mover (344) moving a stage (238) along a first axis and about a second axis includes a magnetic component (454), and a conductor component (456). The magnetic component (454) includes one or more magnets (454D) that are surrounded by a magnetic field. The conductor component (456) is positioned near the magnetic component (454) in the magnetic field. Further, the conductor component (456) interacts with the magnetic component (454) when current is directed to the conductor component (456) to generate a controlled force along the first axis, and a controlled moment about the second axis. Additionally, the conductor component (456) interacts with the magnetic component (454) to generate a controlled force along a third axis that is perpendicular to the first axis and the second axis when current is directed to the conductor component (456).

Abstract: An annealed wafer having enhanced gettering effects for Cu is produced by heating a silicon substrate containing a nitrogen concentration of 5×1014 to 1×1016/cm3, a carbon concentration of 1×1015 to 5×1016/cm3, and an oxygen concentration of 6×1017 to 11×1017/cm3 at a temperature of 650 to 800° C. for a time ?4 hours, and subjecting the heated substrate to argon annealing at a temperature of 1100 to 1250° C., wherein internal stacking fault density after annealing is ?5×108/cm3.

Abstract: Disclosed are methods of making fine patterns by exploiting difference in threshold laser fluence of materials and a thin film transistor (TFT) fabrication methods using the same, and more particularly, to a method of forming a fine pattern and a method of fabricating a TFT through the same method, in which a plurality of layers different in threshold laser fluence are stacked and then exposed to a laser so that a layer having a low threshold laser fluence can be selectively removed, thereby making fine patterns precisely and forming a cavity of a gate electrode precisely and easily.

Abstract: Methods for forming a denuded zone in an oxygen-containing semiconductor wafer using rapid laser annealing (RLA) are disclosed. The method includes scanning an intense beam of laser radiation over the surface of the wafer to raise the temperature of each point on the wafer surface to be at or near the wafer's melting temperature for a time period on the order of a millisecond or so. This rapid heating and cooling causes oxygen in the wafer near the wafer surface to diffuse out from the wafer surface. Oxygen in the body of the wafer remains unheated and thus does not diffuse toward the wafer surface. The result is an oxygen-depleted zone—called a “denuded zone”—formed immediately adjacent the wafer surface. The methods further include forming a semiconductor device feature in the denuded zone such as by implanting the wafer with dopants.

Abstract: Disclosed are methods of manufacturing a semiconductor device. The method of manufacturing one semiconductor device includes forming a transistor structure on a semiconductor substrate, forming a metal interconnection layer on the transistor structure, forming a protective layer on the metal interconnection layer, and implanting hydrogen ions into the semiconductor substrate having the protective layer by using a hydrogen ion implanter. Hydrogen ions are stably and effectively implanted into a selected region by using a hydrogen ion implanter in the manufacturing process of the semiconductor device, thereby facilitating the manufacturing process and improving the performance of the semiconductor device.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.

Abstract: A method of manufacturing a semiconductor device includes a first absorption step, a releasing step, a second absorption step, and an exposure step. In the first absorption step, a wafer chuck of a wafer stage absorbs the semiconductor wafer to adjust the temperature of the semiconductor wafer. In the releasing step, the semiconductor wafer is released from the wafer chuck. In the second absorption step, a wafer chuck of a wafer stage for exposure absorbs the semiconductor wafer. In the exposure step, the semiconductor wafer is exposed.

Abstract: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.

Abstract: A process for forming an oxide-containing film from silicon is provided that includes heating the silicon substrates to a process temperature of between 250° C. and 1100° C. with admission into the process chamber of diatomic reductant source gas Z-Z? where Z and Z? are each H, D and T and a stable source of oxide ion. Multiple exhaust ports exist along the vertical extent of the process chamber to create reactant across flow. A batch of silicon substrates is provided having multiple silicon base layers, each of the silicon base layers having exposed <110> and <100> planes and a film residual stress associated with the film being formed at a temperature of less than 600° C. and having a <110> film thickness that exceeds a <100> film thickness on the <100> crystallographic plane by less than 20%, or a film characterized by thickness anisotropy less than 18% and an electrical breakdown field of greater than 10.5 MV/cm.

Abstract: A measuring device configured to measure a wave aberration of an optical system to be measured includes a reflection optical element for reflecting light, having passed through a mask and the optical system to be measured, into the optical system to be measured, and a detector for detecting an interference fringe of light having passed through pinholes and openings. The mask has at least three pinhole-opening pairs, each including one pinhole and one opening having a larger diameter than the pinhole that are arranged point-symmetrically, the three pinhole-opening pairs having the common center of symmetry. The light to be measured formed in two of the three pairs is made to interfere with the reference light formed in the remaining pair, or, the light to be measured formed in one of the three pairs is made to interfere with the reference light formed in the other two pairs.

Abstract: A method for producing a semiconductor device includes bonding a transfer layer disposed on a first substrate to a second substrate and detaching the transfer layer from the first substrate. In bonding the transfer layer disposed on the first substrate to the second substrate, the method further includes placing a seal having a frame shape on a surface of the first substrate on which the transfer layer is disposed or a surface of the second substrate facing the first substrate, placing an adhesive in a region inside the seal, and superposing the surface of the first substrate on which the transfer layer is disposed on the second substrate with the seal and the adhesive. The seal and the adhesive are incompatible with each other. The seal and the adhesive are not cured in the period from placing the seal to superposing the surface of the first substrate on which the transfer layer is disposed on the second substrate.

Abstract: A system, method and masking arrangement are provided of enhancing the width of polycrystalline grains produced using sequential lateral solidification using a modified mask pattern is disclosed. One exemplary mask pattern employs rows of diamond or circular shaped areas in order to control the width of the grain perpendicular to the direction of primary crystallization.

Abstract: There is provided a method of forming a pattern on a group III nitride semiconductor substrate. A method of forming a pattern on a group III nitride semiconductor substrate according to an aspect of the invention may include: irradiating a laser beam onto at least one first region for preventing etching in a group III nitride semiconductor substrate; and etching at least one second region exclusive of the first region using the first region irradiated with the laser beam as a mask.

Abstract: A method of manufacturing a semiconductor device wherein semiconductor elements (e.g., transistors) respectively formed in multiple independent wells have the same characteristics with the number of production process steps being reduced. A P-type well as an area of a first conductivity type is formed on a semiconductor substrate. Then, second and fourth wells as two regions of a second conductivity type are formed apart from each other in the P-type well, and a first buried well of N-type as a first buried region of the second conductivity type to connect the second and fourth wells is formed at the bottom of a third well (part of the area of the first conductivity type) sandwiched between the second and fourth wells. In this way, a triple well is formed on the semiconductor substrate.

Abstract: The invention pertains to a photovoltaic (PV) module comprising a plurality of cells, each cell containing a substrate, a transparent conductor layer, a photovoltaic layer, and a back-electrode layer, wherein the photovoltaic layer comprises at least one p-i-n or n-i-p silicon layer, characterized in that said silicon layer comprises 10 to 1000 conducting spots of recrystallized silicon per cm2, each having independently a surface or 10 to 2500 ?m. The PV module can be obtained by a method wherein the p-i-n or n-i-p silicon layer is locally heated whereby said silicon is transformed at these spots, after which the silicon at these spots is allowed to solidify in a transformed state.

Abstract: A FLOTOX-TYPE EEPROM of the invention has a configuration wherein an N region 25 as an impurity region formed under a tunnel window 12 and a channel stopper region 19 formed under a LOCOS oxide film 18 are spaced apart by a predetermined distance Y. Therefore, the tunnel window 12 does not sustain damage if an excessive voltage is applied to the tunnel window 12. As a result, the FLOTOX-TYPE EEPROM is adapted to limit the voltage applied to the tunnel window 12 and to reduce stress on the tunnel window 12 and can achieve an increased number of rewrites.

Abstract: A method for fabricating a semiconductor body is presented. The semiconductor body includes a p-conducting zone, an n-conducting zone and a pn junction in a depth T1 in the semiconductor body between the p-conducting zone and the n-conducting zone. The method includes providing the semiconductor body, producing the p-doped zone by the diffusion of an impurity that forms an acceptor in a first direction into the semiconductor body, and producing the n-conducting zone by the implantation of protons in the first direction into the semiconductor body into a depth T2>T1 and the subsequent heat treatment of the semiconductor body in order to form hydrogen-induced donors.

Abstract: Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.

Abstract: A plasma of a gas containing an impurity is produced through a discharge in a vacuum chamber, and a plurality of substrates are successively doped with the impurity by using the plasma, wherein a plasma doping condition of a subject substrate is adjusted based on an accumulated discharge time until the subject substrate is placed in the vacuum chamber.

Abstract: A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then melted, resolidified, and annealed to completely dissociate and activate the boron clusters.

Abstract: The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a second wavelength. The second wavelength is larger than the first wavelength. A marker structure is provided having a first layer and a second layer. The second layer is present either directly or indirectly on top of said first layer. The first layer has a first periodic structure and the second layer has a second periodic structure. At least one of the periodic structures has a plurality of features in at least one direction with a dimension smaller than 400 nm. Additionally, a combination of the first and second periodic structure forms a diffractive structure arranged to be illuminated by radiation with the second wavelength.

Abstract: Disclosed herein are a method for fabricating an organic thin film transistor, including treating the surfaces of a gate insulating layer and source/drain electrodes with a self-assembled monolayer (SAM)-forming compound through a one-pot reaction, and an organic thin film transistor fabricated by the method. According to example embodiments, the surface-treatment of the gate insulating layer and the source/drain electrodes may be performed in a single vessel through a single process.

Abstract: A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape.

Abstract: A method for manufacture of application specific solar cells includes providing and processing custom design information to determine at least a cell size and a cell shape. The method includes providing a transparent substrate having a back surface region, a front surface region, and one or more grid-line regions overlying the front side surface region. The one or more grid regions provide one or more unit cells having the cell size and the cell shape. The method further includes forming a layered structure including photovoltaic materials overlying the front surface region.

Abstract: A process for the fabrication of semiconductor devices on a substrate, the semiconductor devices including at least one metal layer. The process includes, removing the substrate and applying a second substrate; and annealing the at least one metal layer by application of a beam of electromagnetic radiation on the at least one metal layer.

Abstract: A robot apparatus according to the invention is configured to hand over a workpiece by rotating by a prescribed angle a finger including a holding means for holding the workpiece. The robot apparatus includes: a drive shaft including a first finger and a second finger spaced from each other. The first finger includes a first arm portion and a second arm portion extending from its rotation center with a prescribed angle therebetween so as to be distanced from each other. The second finger includes a third arm portion and a fourth arm portion extending from its rotation center with a prescribed angle therebetween so as to be distanced from each other. The second arm portion and the fourth arm portion are distanced from each other when the first arm portion and the third arm portion overlap in the axial direction of the drive shaft. The robot apparatus can further improve productivity without incurring size increase and high cost.

Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.

Abstract: A diffractive optical element, a lithographic apparatus including a diffractive optical element, and a semiconductor device manufacturing method diffract a radiation beam onto an output plane. The diffractive optical element has a plurality of unit cells each having a phase structure for adjusting a cross-sectional intensity distribution of an incoming radiation beam into a desired intensity distribution. The unit cells of the diffractive optical element have corresponding phase structures that are arranged adjacently and are mirrored or inverted with respect to each other.

Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.

Abstract: An improved process of substrate cleaving and a device to perform the cleaving are disclosed. In the traditional cleaving process, a layer of microbubbles is created within a substrate through the implantation of ions of a gaseous species, such as hydrogen or helium. The size and spatial distribution of these microbubbles is enhanced through the use of ultrasound energy. The ultrasound energy causes smaller microbubbles to join together and also reduces the straggle. An ultrasonic transducer is acoustically linked with the substrate to facilitate these effects. In some embodiments, the ultrasonic transducer is in communication with the platen, such that ultrasound energy can be applied during ion implantation and/or immediately thereafter. In other embodiments, the ultrasonic energy is applied to the substrate during a subsequent process, such as an anneal.

Abstract: A method for manufacturing a semiconductor device, includes: bringing a first major surface of a first substrate into close contact with a second major surface of a second substrate being different in thermal expansion coefficient from the first substrate at a first temperature higher than room temperature; and bonding the first substrate and the second substrate by heating the first substrate and the second substrate to a second temperature higher than the first temperature with the first major surface being in close contact with the second major surface.

Abstract: Disclosed are methods for providing wafer photonic flow control to a semiconductor wafer (1700) having a substrate (1720), at least one active layer (1765) and at least one surface layer (1710). Photonic flow control can be achieved through the formation of trenches (1725) and/or insulating implants (1730) formed in said wafer (1700), whereby active regions (1760) are defined by trenches (1725) that operate as nonconductive areas (1750). Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Photonic flow control at the wafer level is important when using WLBI methods and systems.

Abstract: By using a first substrate which has a light-transmitting property and whose first face is provided with a light-absorbing layer, a mixture including an organic compound and an inorganic material is irradiated with light having a wavelength, which is absorbed by the inorganic material to heat the mixture, and thereby a film of the organic compound included in the mixture is formed on the first face of the first substrate. Then, the first face of the first substrate and a deposition surface of a second substrate are arranged to be adjacent to or in contact with each other, irradiation with light having a wavelength, which is absorbed by the light-absorbing layer is conducted from a second face side of the first substrate, to heat the organic compound, and thereby at least part of the organic compound is formed as a film on the deposition surface of the second substrate.

Abstract: The present invention is a method for producing an annealed wafer, wherein, at least, when a boat in which a semiconductor wafer is placed is inserted into a furnace tube, the boat is inserted along with introducing an inert gas into the furnace, so that entirety of the semiconductor wafer to be a product reaches a thermally uniform portion, then an insertion rate of the boat in which the semiconductor wafer is placed is decelerated and/or suspended, so that an interval between the furnace tube and the shutter is maintained for a predetermined time, and then the furnace tube is blocked in with the shutter. Thereby, there can be provided a method for producing an annealed wafer by which during the heat treatment, it can be more certainly prevented that the wafer is contaminated with conductive impurities and that thereby resistivity of the wafer is changed before and after the heat treatment.

Abstract: There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern.

Abstract: The present disclosure is directed to systems and methods for protecting a semiconductor product or material from harmful effects of pulsed laser irradiation. In some embodiments, a thin sacrificial protective mask layer that expires after one laser processing operation is applied to the surface of the product or material to be laser-treated. The thin protective mask layer reflects, absorbs, or otherwise protects the underlying product or material from the energy of the laser.

Abstract: A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with a first exposure energy using a first pattern mask with a first light transmitting part having a first width at boundaries between the individual color filters; forming a second exposed part overlapping a portion of the first exposed part by exposing the photoresist film with a second exposure energy smaller than the first exposure energy using a second pattern mask with a second light transmitting part having a second width wider than the first width; and forming microlenses by developing the photoresist film.

Abstract: The present invention relates to radiation hardening by design (RHBD), which employs layout and circuit techniques to mitigate the damaging effects of ionizing radiation. Reverse body biasing (RBB) of N-type metal-oxide-semiconductor (NMOS) transistors may be used to counteract the effects of trapped positive charges in isolation oxides due to ionizing radiation. In a traditional MOS integrated circuit, input/output (I/O) circuitry may be powered using an I/O power supply voltage, and core circuitry may be powered using a core power supply voltage, which is between the I/O power supply voltage and ground. However, in one embodiment of the present invention, the core circuitry is powered using a voltage difference between the core power supply voltage and the I/O power supply voltage. The bodies of NMOS transistors in the core circuitry are coupled to ground; therefore, a voltage difference between the core power supply voltage and ground provides RBB.

Abstract: Provided is a heat treatment method wherein generation of slip dislocation in silicon wafer RTP is suppressed, in order to solve a problem of not sufficiently suppressing generation of slip dislocation of silicon wafers in conventional RTP. A step is provided for suspending temperature rising for 10 seconds or longer at a temperature in a range of over 700° C. to below 950° C., so as to prevent generation of slip dislocation during rapid heating, at least at a silicon wafer portion that contacts with a supporting section of a rapid heating apparatus or at a portion on the outermost circumference section of the silicon wafer.

Abstract: A process is disclosed for producing a doped gallium arsenide single crystal by melting a gallium arsenide starting material and subsequently solidifying the gallium arsenide melt, wherein the gallium arsenide melt contains an excess of gallium relative to the stoichiometric composition, and wherein it is provided for a boron concentration of at least 5×1017 cm?3 in the melt or in the obtained crystal. The thus obtained crystal is characterized by a unique combination of low dislocation density, high conductivity and yet excellent, very low optic absorption, particularly in the range of the near infrared.

Abstract: A p-n junction is formed at the interface of a low-concentration n-type impurity layer and a p-type diffusion region in the vicinity of the upper major surface of an n-type semiconductor substrate of a semiconductor device. A mask composed of an absorber is placed on the upper major surface of the semiconductor device, and electron beams are radiated. Thereafter, heat treatment is conducted. As a result, the peak of the crystal lattice defect densities is present in the vicinity of the upper major surface of the n-type semiconductor substrate, and the crystal lattice defect densities are decreasingly distributed toward the lower major surface. Thereby, a semiconductor device that can minimize the variation of the breakdown voltage characteristics of the p-n junction of the diode, and can control the optimum carrier lifetime can be obtained.