Radiation Treatment (epo) Patents (Class 257/E21.328)
  • Publication number: 20100003809
    Abstract: A method for destruction of metallic carbon nanotubes is provided. The method includes irradiating a mixture of semiconducting carbon nanotubes and metallic carbon nanotubes with energy beams (such as laser light), thereby selectively destroying metallic carbon nanotubes or semiconducting carbon nanotubes. The energy beams have energy components for resonance absorption by the metallic carbon nanotubes or semiconducting carbon nanotubes.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 7, 2010
    Applicant: SONY CORPORATION
    Inventor: Houjin Huang
  • Publication number: 20090325392
    Abstract: An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Jack Hwang, Sridhar Govindaraju, Karson Knutson, Harold Kennel, Aravind Killampalli
  • Publication number: 20090325393
    Abstract: Disclosed is a heat treatment method including a step of placing a wafer W provided with a low-k film and a metal layer in a heat treatment furnace 41, a step of supplying gaseous acetic anhydride into the heat treatment furnace 41, while controlling the flow rate using a mass flow controller 44d, and a step of heating the wafer W in the heat treatment furnace 41 supplied with gaseous acetic anhydride by using a heater 41b provided in the heat treatment furnace 41.
    Type: Application
    Filed: July 18, 2007
    Publication date: December 31, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hidenori Miyoshi, Masaki Narushima
  • Publication number: 20090317983
    Abstract: In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.
    Type: Application
    Filed: September 1, 2006
    Publication date: December 24, 2009
    Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY
    Inventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Masahiro Nagano, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
  • Publication number: 20090311847
    Abstract: Presented is a method for producing an optoelectronic component. The method includes separating a semiconductor layer based on a III-V-compound semiconductor material from a substrate by irradiation with a laser beam having a plateau-like spatial beam profile, where individual regions of the semiconductor layer are irradiated successively.
    Type: Application
    Filed: August 21, 2009
    Publication date: December 17, 2009
    Inventors: Michael FEHRER, Berthold HAHN, Volker HARLE, Stephan KAISER, Frank OTTE, Andreas PLOSSL
  • Publication number: 20090311880
    Abstract: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 ?m is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer as a larger beam surrounding the line beam. The two beams are scanned in synchronism in the direction of the narrow dimension of the line beam to create a narrow heating pulse from the line beam when activated by the larger beam. The energy of GaAs radiation is greater than the silicon bandgap energy and creates free carriers. The energy of the CO2 radiation is less than the silicon bandgap energy so silicon is otherwise transparent to it, but the long wavelength radiation is absorbed by the free carriers.
    Type: Application
    Filed: August 24, 2009
    Publication date: December 17, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Dean JENNINGS, Haifan LIANG, Mark YAM, Vijay PARIHAR, Abhilash J. MAYUR, Aaron HUNTER, Bruce ADAMS, Joseph Michael RANISH
  • Publication number: 20090311840
    Abstract: A method of manufacturing a semiconductor device includes forming, over a substrate, a gate insulating film containing a high-k insulating film which is composed of a material having a dielectric constant larger than that of silicon dioxide film; forming a gate electrode containing a metal over the gate insulating film; forming extension regions by implanting an dopant into the substrate using the gate electrode as a mask; and annealing the substrate, having the dopant implanted therein, by flash lamp annealing or laser annealing; wherein the annealing further includes: a first step irradiating a substrate with a light pulse having a predetermined peak intensity; and a second step irradiating a substrate with light pulses having peak intensities lower than that of the light pulse used in the first step.
    Type: Application
    Filed: June 15, 2009
    Publication date: December 17, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takashi ONIZAWA
  • Publication number: 20090305445
    Abstract: In the present invention, a first substrate which is an evaporation donor substrate is prepared in which a material layer is formed over a patterned reflective layer. A surface of the material layer over the first substrate is irradiated with first light which satisfies one predetermined irradiation condition to pattern the material layer. A surface opposite to the surface of the first substrate is irradiated with second light which satisfies another predetermined irradiation condition to evaporate the patterned material layer onto a second substrate, which is a deposition target substrate. According to the present invention, deterioration of a material included in the material layer can be prevented and a film pattern can be formed on the second substrate with high accuracy.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 10, 2009
    Inventors: Hisao Ikeda, Takahiro Ibe
  • Publication number: 20090305518
    Abstract: An SOI wafer which does not generate slip dislocation even if laser annealing is performed for no more than 0.1 seconds at a maximum temperature of 1200° C. or more is provided. This wafer is an SOI wafer used for a process of manufacturing a semiconductor device, in which laser annealing is conducted for no more than 0.1 seconds at a maximum temperature of 1200° C. or more, which includes an active layer, a support layer of a monocrystalline silicon, and an insulated oxide film layer between the active layer and the support layer, wherein light-scattering defect density measured by a 90° light scattering method at the depth region of 260 ?m toward the support layer side from an interface between the insulated oxide film layer and the support layer is 2×108/cm3 or less.
    Type: Application
    Filed: August 14, 2009
    Publication date: December 10, 2009
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Masataka HOURAI
  • Patent number: 7629274
    Abstract: A storage node, a method of fabricating the same, a semiconductor memory device and a method of fabricating the same is provided. The method of fabricating a storage node may include forming a lower electrode, forming an irradiated data storage layer and forming an upper electrode.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: December 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hyun Lee, Sang-Bong Bang
  • Publication number: 20090298299
    Abstract: The present invention relates to methods of fabricating electronic devices using laser ablation and to devices fabricated thereby. Embodiments of the methods are particularly suitable for defining electrodes within thin film transistor (TFT) structures using laser ablation in a step-and-repeat mode.
    Type: Application
    Filed: August 31, 2006
    Publication date: December 3, 2009
    Applicant: PLASTIC LOGIC LIMITED
    Inventors: Paul A. Cain, Carl Hayton
  • Publication number: 20090298300
    Abstract: Methods and apparatus for hyperbaric rapid thermal processing of a substrate are described. Methods of processing a substrate in a rapid thermal processing chamber are described that include passing a substrate from outside the chamber through an access port onto a support in the interior region of the processing chamber, closing a port door sealing the chamber, pressurizing the chamber to a pressure greater than 1.5 atmospheres absolute and directing radiant energy toward the substrate. Hyperbaric rapid thermal processing chambers are described which are constructed to withstand pressures greater than at least about 1.5 atmospheres absolute or, optionally, 2 atmospheres of absolute pressure. Processing chambers may include pressure control valves to control the pressure within the chamber.
    Type: Application
    Filed: May 7, 2009
    Publication date: December 3, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Joseph M. Ranish, Khurshed Sorabji, Alexander N. Lerner, Aaron M. Hunter
  • Publication number: 20090291549
    Abstract: On a Si substrate 1, i.e., a semiconductor substrate, a gate insulating film 2 is formed, and then a W-based film 3a is formed on the gate insulating film 2 by CVD using a film forming gas including W(CO)6 gas. Then, the film is oxidized under existence of a reducing gas, and the W in the W-based film 3a is not oxidized but only C is selectively oxidized to reduce the concentration of C contained in the W-based film 3a. Then, after performing heat treatment as needed, resist coating, patterning, etching and the like are performed, and, an impurity diffused region 10 is formed by ion implantation and the like, and a semiconductor device having a MOS structure is formed.
    Type: Application
    Filed: November 24, 2006
    Publication date: November 26, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hideaki Yamasaki, Koji Akiyama, Kazuyoshi Yamazaki, Yumiko Kawano
  • Publication number: 20090289350
    Abstract: Disclosed is a semiconductor package wherein a semiconductor chip is mounted on one surface of a substrate. In this semiconductor package, an inflection point forming portion made of a material having a higher coefficient of thermal expansion than the substrate is formed in a part of the substrate surface on which the semiconductor chip is mounted.
    Type: Application
    Filed: July 5, 2006
    Publication date: November 26, 2009
    Applicant: NEC CORPORATION
    Inventor: Shinji Watanabe
  • Publication number: 20090286374
    Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.
    Type: Application
    Filed: July 24, 2009
    Publication date: November 19, 2009
    Applicants: NEC CORPORATION, NEC LCD TECHNOLOGIES, LTD
    Inventors: Shigeru MORI, Takahiro KORENARI, Tadahiro MATSUZAKI, Hiroshi TANABE
  • Publication number: 20090286383
    Abstract: A photo-curing or photosintering process is utilized to modify, reduce or eliminate whiskers or nanowires growing on a material surface.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 19, 2009
    Applicant: APPLIED NANOTECH HOLDINGS, INC.
    Inventors: Nan Jiang, Zvi Yaniv
  • Publication number: 20090280628
    Abstract: In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.
    Type: Application
    Filed: July 15, 2009
    Publication date: November 12, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Manoj Vellaikal, Kartik Santhanam, Yen B. Ta, Martin A. Hilkene, Matthew D. Scotney-Castle, Canfeng Lai, Peter I. Porshnev, Majeed A. Foad
  • Publication number: 20090278164
    Abstract: A GaN-based semiconductor light-emitting device 1 includes a stacked body 10A having the component layers 12 that include an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer each formed of a GaN-based semiconductor, sequentially stacked and provided as an uppermost layer with a first bonding layer 14 made of metal and a second bonding layer 33 formed on an electroconductive substrate 31, adapted to have bonded to the first bonding layer 14 the surface thereof lying opposite the side on which the electroconductive substrate 31 is formed, made of a metal of the same crystal structure as the first bonding layer 14, and allowed to exhibit an identical crystal orientation in the perpendicular direction of the bonding surface and the in-plane direction of the bonding surface.
    Type: Application
    Filed: February 16, 2007
    Publication date: November 12, 2009
    Applicant: SHOWA DENKO K.K.
    Inventors: Hiroshi Osawa, Takashi Hodota
  • Publication number: 20090273376
    Abstract: The present invention discloses AC/DC converters and methods of manufacturing the same. The method includes providing a substrate; forming an oxide layer on a top surface of the substrate; applying a photo-resist layer on the oxide layer to define a well region; performing an ion-implantation in the well region using a dopant; and driving in atoms of the dopant to a depth in the well region through a thermal treatment, wherein the driving in process provides a concentration profile of the dopant in the well region such that the semiconductor structure has a high breakdown voltage.
    Type: Application
    Filed: February 19, 2009
    Publication date: November 5, 2009
    Inventors: Siarhei KALODKA, Sergey Gaitukevich, Vitali Maziarkin, Alan Wang, Chen-Hui Tsay
  • Publication number: 20090267162
    Abstract: A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment.
    Type: Application
    Filed: March 13, 2009
    Publication date: October 29, 2009
    Inventor: Kazuaki Nakajima
  • Publication number: 20090245311
    Abstract: Provided are a process for producing a nitride semiconductor laser that is a process applied to materials wherein a diffusion of an impurity is not easily attained, such as nitride semiconductor material, and substituted for any process including the step of local diffusion of an impurity, which has been hitherto carried out for GaAlAs based or AlGaInP based semiconductors, and that is a process which is effective, high in precision, and suitable for mass production; and a nitride semiconductor laser produced by this process. The nitride-semiconductor-producing process of the present invention includes the steps of: preparing a substrate having an MQW active layer made of a nitride semiconductor containing In; irradiating a vicinity of a light-emitting end face of the multiquantum well active layer, or a planned region of the light-emitting end face selectively with a laser beam; and performing heating treatment after the laser-irradiating step.
    Type: Application
    Filed: March 4, 2009
    Publication date: October 1, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kyozo KANAMOTO, Katsuomi Shiozawa
  • Publication number: 20090239371
    Abstract: A semiconductor wafer (10) is structured such that fine structures (3), such as membranes, bridges or tongues, with a thickness d<<D are formed, wherein D designates the thickness of the semiconductor wafer (10). Then particles of a desired material are applied. A temporal or spatial temperature gradient is generated in the semiconductor wafer (10), e.g. by progressive heating. In such a heating process the fine structures heat up more quickly and become hotter than the remaining wafer because they have a smaller heat capacity per area and cannot carry off heat as quickly. In this manner, the fine structures can be heated to a temperature that allows a sintering of the particles. For coating the semiconductor wafer (10) is brought into a reactor (11). A precursor compound of a metal is provided and fed to the reactor (11), where a reaction takes place during which the metal is transformed to a final compound and is deposited in the form of particles on the semiconductor wafer (10).
    Type: Application
    Filed: November 23, 2005
    Publication date: September 24, 2009
    Inventors: Felix Mayer, Christoph Kleinlogel
  • Publication number: 20090230514
    Abstract: A method of manufacturing a nitride semiconductor device includes the steps of: growing a group III nitride semiconductor layer on a substrate; forming a processed region in the substrate with a laser beam; and reducing the thickness of the substrate thereby spontaneously dividing the substrate from the processed region by the internal stress of the substrate. The substrate may be a sapphire substrate or an SiC substrate.
    Type: Application
    Filed: July 25, 2008
    Publication date: September 17, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Shinichi Kohda
  • Publication number: 20090233455
    Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices to enhance channel strain. The method includes relaxing a gate structure using a low temperature thermal creep process to enhance channel strain. The gate structure undergoes a plastic deformation during the low temperature thermal creep process.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 17, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: THOMAS W. DYER
  • Publication number: 20090233413
    Abstract: A method for fabricating a semiconductor device using a SOI substrate, includes the steps of: preparing a SOI substrate, comprises a semiconductor support layer; an insulating layer formed on the semiconductor support layer; and a SOI layer formed on the insulating layer; forming an active region on the SOI layer, so that a part of the semiconductor support layer is exposed; and forming a specific mark on the exposed part of the semiconductor support layer.
    Type: Application
    Filed: March 9, 2009
    Publication date: September 17, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Takeshi Katayama
  • Publication number: 20090233456
    Abstract: An irradiation optical system includes: a first projection optical system for mixing a plurality of luminous fluxes outputted from a laser light source having a plurality of linearly arrayed light emitting points with each other and dividing the mixed luminous fluxes into a plurality of luminous fluxes and then projecting, to a slit member having a plurality of slits parallel to each other, the plural luminous fluxes as a line beam extending across the plural slits; and a second projection optical system for projecting an image of the plural slits of the slit member to an irradiation target.
    Type: Application
    Filed: February 25, 2009
    Publication date: September 17, 2009
    Applicant: Sony Corporation
    Inventor: Koichi Tsukihara
  • Patent number: 7589032
    Abstract: Continuous wave laser apparatus with enhanced processing efficiency is provided as well as a method of manufacturing a semiconductor device using the laser apparatus. The laser apparatus has: a laser oscillator; a unit for rotating a process object; a unit for moving the center of the rotation along a straight line; and an optical system for processing laser light that is outputted from the laser oscillator to irradiate with the laser light a certain region within the moving range of the process object. The laser apparatus is characterized in that the certain region is on a line extended from the straight line and that the position at which the certain region overlaps the process object is moved by rotating the process object while moving the center of the rotation along the straight line.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: September 15, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka, Hidekazu Miyairi, Aiko Shiga, Akihisa Shimomura, Mai Akiba
  • Publication number: 20090224284
    Abstract: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high.
    Type: Application
    Filed: February 8, 2009
    Publication date: September 10, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Michio NEMOTO
  • Patent number: 7585790
    Abstract: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 8, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Kun-Hsien Lee, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang, Neng-Kuo Chen
  • Publication number: 20090221136
    Abstract: By operating an implantation tool with a source gas having a halogen fraction of 66 atomic percent or less relative to the total composition of the source gas, an in situ cleaning effect may be achieved while performing an implantation process.
    Type: Application
    Filed: October 22, 2008
    Publication date: September 3, 2009
    Inventors: Christian Krueger, Rastislav Kocis, Marek Braun, Niels-Wieland Hauptmann, Heinz Seidel
  • Publication number: 20090218577
    Abstract: Under one aspect, a method of processing a film includes defining a plurality of spaced-apart regions to be crystallized within a film, the film being disposed on a substrate and capable of laser-induced melting; generating a sequence of laser pulses having a fluence that is sufficient to melt the film throughout its thickness in an irradiated region, each pulse forming a line beam having a length and a width; continuously scanning the film in a first scan with a sequence of laser pulses at a velocity selected such that each pulse irradiates and melts a first portion of a corresponding spaced-apart region, wherein the first portion upon cooling forms one or more laterally grown crystals; and continuously scanning the film in a second time with a sequence of laser pulses at a velocity selected such that each pulse irradiates and melts a second portion of a corresponding spaced-apart region, wherein the first and second portions in each spaced-apart region partially overlap, and wherein the second portion upon
    Type: Application
    Filed: August 16, 2006
    Publication date: September 3, 2009
    Inventor: James S. Im
  • Patent number: 7582492
    Abstract: The invention provides a method of doping impurities that includes a step of doping impurities in a solid base substance by using a plasma doping method, a step of forming a light antireflection layer that functions to reduce light reflection on the surface of the solid base substance, and a step of performing annealing by light radiation. According to the method, it is possible to reduce the reflectance of light radiated during annealing, to efficiently apply energy an impurity doped layer, to improve activation efficiency, to prevent diffusion, and to reduce sheet resistance of the impurity doped layer.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: September 1, 2009
    Assignee: Panasonic Corporation
    Inventors: Cheng-Guo Jin, Yuichiro Sasaki, Bunji Mizuno, Katsumi Okashita, Hiroyuki Ito, Tomohiro Okumura, Satoshi Maeshima, Ichiro Nakayama
  • Publication number: 20090215250
    Abstract: In plasma immersion ion implantation of a polysilicon gate, a hydride of the dopant is employed as a process gas to avoid etching the polysilicon gate, and sufficient argon gas is added to reduce added particle count to below 50 and to reduce plasma impedance fluctuations to 5% or less.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Kartik Santhanam, Manoj Vellaikal, Peter I. Porshnev, Majeed A. Foad
  • Publication number: 20090209111
    Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 20, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Wataru Shimizu, Ikuo Kurachi
  • Publication number: 20090203231
    Abstract: A phase modulation element according to the present invention has a first area having a first phase value based on a phase modulation unit having a predetermined size and a second area having a second phase value based on the phase modulation unit having the predetermined size, and each phase distribution is defined by a change in area shares of the first area and the second area depending on each position.
    Type: Application
    Filed: April 16, 2009
    Publication date: August 13, 2009
    Inventors: Masakiyo MATSUMURA, Yukio TANIGUCHI
  • Publication number: 20090197401
    Abstract: Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 6, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Shijian Li, Kartik Ramaswamy, Hiroji Hanawa, Seon-Mee Cho, Biagio Gallo, Dongwon Choi, Majeed A. Foad
  • Publication number: 20090197427
    Abstract: A thermal cycle includes: increasing a temperature from an initial temperature to a temperature T1 at an arbitrary rate R1 (° C./sec); holding the temperature at the temperature T1 for an arbitrary period t1 (sec); increasing the temperature from the temperature T1 to a temperature T2 at a rate R2 (° C./sec) of 1.0×107 (° C./sec) or less; and holding the temperature at the temperature T2 for a period t2 (sec) of 50 msec or less. The thermal cycle thereafter includes: decreasing the temperature from the temperature T2 to the temperature T1 at a rate R1? (° C./sec) of 1.0×107 (° C./sec) or less; holding the temperature T1 for an arbitrary period t3 (sec); and decreasing the temperature from the temperature T1 to a final temperature at an arbitrary rate R2? (° C./sec). Such a thermal cycle is successively repeated in a plurality of iterations.
    Type: Application
    Filed: January 13, 2009
    Publication date: August 6, 2009
    Inventors: Kenji YONEDA, Kazuma TAKAHASHI
  • Publication number: 20090191724
    Abstract: A substrate heating apparatus having a conductive heater which heats a substrate includes a filament arranged in the conductive heater and connected to a filament power supply to generate thermoelectrons, and an acceleration power supply which accelerates the thermoelectrons between the filament and conductive heater. The filament has inner peripheral portions formed at a predetermined interval along an inner circle concentric with the substrate, outer peripheral portions formed at a predetermined interval on an outer circle concentric with the inner circle and having a diameter larger than that of the inner circle, and a region formed by connecting the end point of each inner peripheral portions and the end point of a corresponding one of the outer peripheral portions.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 30, 2009
    Applicants: CANON ANELVA ENGINEERING CORPORATION, CANON ANELVA CORPORATION
    Inventors: Masami Shibagaki, Hiroshi Doi, Akihiro Egami, Toshiaki Sasaki, Shinya Hasegawa
  • Publication number: 20090184340
    Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 23, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Michio NEMOTO, Haruo NAKAZAWA
  • Publication number: 20090181483
    Abstract: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution of an inverse peak pattern in which a light intensity is minimum in a point corresponding to the phase shift portion of the phase shift mask, and irradiating a polycrystalline semiconductor film or an amorphous semiconductor film with the light beam having the light intensity distribution to produce a crystallized semiconductor film.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 16, 2009
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20090176381
    Abstract: There are provided a method of manufacturing a semiconductor device and a substrate processing apparatus that are designed to suppress a popping phenomenon and reduce residues remaining on a substrate in a photoresist removing process. Oxygen gas and hydrogen gas are supplied to a plasma generating chamber while maintaining the hydrogen atom/oxygen atom ratio of the oxygen and hydrogen gases equal to or higher than 3, and the oxygen gas and the hydrogen gas are excited into plasma in the plasma generating chamber so as to remove photoresist from a substrate accommodated in a treatment chamber installed contiguous to the plasma generating chamber.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 9, 2009
    Inventors: Shin HIYAMA, Toru Kakuda, Yukitomo Hirochi
  • Publication number: 20090166624
    Abstract: A phase modulation element according to the present invention has a first area having a first phase value based on a phase modulation unit having a predetermined size and a second area having a second phase value based on the phase modulation unit having the predetermined size, and each phase distribution is defined by a change in area shares of the first area and the second area depending on each position.
    Type: Application
    Filed: February 5, 2009
    Publication date: July 2, 2009
    Inventors: Masakiyo MATSUMURA, Yukio Taniguchi
  • Patent number: 7553778
    Abstract: A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a part of the amorphous semiconductor film with the laser beam, while scanning in a longitudinal direction intersecting the irradiation area, the part superposing the first polycrystalline semiconductor film and being adjacent to the first polycrystalline semiconductor film, thereby forming a second polycrystalline semiconductor film. The laser beam has a wavelength in a range from 390 nm to 640 nm, and the amorphous semiconductor film has a thickness in a range from 60 nm to 100 nm.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: June 30, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Naoki Nakagawa, Atsuhiro Sono, Shinsuke Yura, Kazushi Yamayoshi
  • Patent number: 7553772
    Abstract: Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 30, 2009
    Assignee: LSI Corporation
    Inventors: Shiqun Gu, Wai Lo, Hong Lin
  • Publication number: 20090163038
    Abstract: Disclosed is a heat treatment unit 4 serving as a heat treatment apparatus, which includes a chamber 42 for containing a wafer W on which a low dielectric constant interlayer insulating film is formed, a formic acid supply device 44 for supplying gaseous formic acid into the chamber 42, and a heater 43 for heating the wafer W in the chamber 42 which is supplied with formic acid by the formic acid supply device 44.
    Type: Application
    Filed: May 28, 2007
    Publication date: June 25, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Hidenori Miyoshi
  • Publication number: 20090159881
    Abstract: The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination block of each chip 10 within a shot, which is a segmented region of the wafer, by a fixed pattern method. In addition, an information bit uniquely given to each shot within the wafer is written by a mask shift method. Further, an information bit uniquely given to each wafer is written in a wafer discrimination block of the chip 10 which is fabricated on the wafer by the mask shift method and mask combination method.
    Type: Application
    Filed: August 7, 2008
    Publication date: June 25, 2009
    Inventors: Hidehiko KANDO, Isao Sakama
  • Publication number: 20090149034
    Abstract: In a semiconductor module, adhesion between an insulating base material and an insulator provided on the insulating base material, for example a sealing resin of the semiconductor element, is to be improved. A plurality of interconnect layers, each including an interlayer dielectric film 405 and a copper interconnect 407, is stacked and a solder resist layer 408 is formed on an uppermost layer. Elements 410a and 410b are formed on a surface of the solder resist layer 408. The elements 410a and 410b are molded in a molding resin 415. The surface of the solder resist layer 408 is modified by plasma processing under a specific condition so that minute projections are formed thereon. Such surface of the solder resist layer 408 is processed such that a value of y/x becomes not less than 0.4, where x represents a detected intensity at a binding energy of 284.5 eV and y represents a detected intensity at a binding energy of 286 eV, by an X-ray photoelectric spectroscopy spectrum.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 11, 2009
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Ryosuke USUI, Hideki Mizuhara, Takeshi Nakamura
  • Publication number: 20090146146
    Abstract: A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region, a drain region, and a charge carrier channel between the source and drain regions. The second intrinsic stress is aligned substantially parallel to the charge carrier channel.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 11, 2009
    Inventors: Roman Knoefler, Armin Tilke
  • Publication number: 20090142875
    Abstract: A method for forming a selective emitter on a silicon solar cell is provided including forming an oxide layer on a surface of the P-type silicon substrate, implanting phosphorus doping atoms into the oxide layer on the substrate using plasma immersion ion implantation, patterning the oxide layer, annealing the substrate to provide heavily doped regions in the patterned regions and a lightly doped region between the patterned regions, and providing metal contacts to the heavily doped regions.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Peter Borden, Mitchell C. Taylor
  • Publication number: 20090133731
    Abstract: Devices including nano-junctions made between aligned functionalized carbon nanotubes, and methods of aligning functionalized carbon nanotubes for the purpose of fabricating either coaligned or criss-crossed p-n junctions. Devices, such as thermoelectric devices, may be formed of a plurality of n-type carbon nanotubes forming a film and/or a plurality of p-type carbon nanotubes forming a film. Methods of making a criss-crossed p-n nanojunction device include the steps of functionalizing a carbon nanotube to create a p-type tube, functionalizing a carbon nanotube to create an n-type tube, applying an RF field to align nanotubes of a given p- or n-type, and orienting nanotubes of different types cross-wise relative to each other to achieve criss-crossed p-n nanojunctions.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 28, 2009
    Applicant: New Jersey Institute of Technology
    Inventors: Haim Grebel, Shamim Mirza