Abstract: The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film.

Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.

Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.

Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated into individual package strip for leadless packages. Three-dimensional stacking is achieved by a bonding area on an uppermost portion of the sidewall. The sidewall of the strip is high enough to enclose an encapsulant covering a later mounted integrated circuit die and associated bonding wires.

Abstract: The semiconductor device comprises a support plate; a semiconductor element; and conductor posts consisting of a conductor having a first end at one end and a second end at the other end, the second end being connected to the semiconductor element and the conductor posts being connected to the support plate at a position on the side of the second end that is closer to the first end, wherein the conductor posts have a heat conductivity of approximately 200 W/m·K or higher and a Vickers hardness of approximately 70 or lower.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the L-plated lead; and an encapsulant encapsulating the L-plated lead and the die.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; embedding a circuit end of an internal interconnect in the bonding interconnect; and connecting a lead end of the internal interconnect to the lead.

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a hole, a lead extension, and an exterior pad under the lead extension with the hole abutting the lead extension; connecting an electrical interconnect between an integrated circuit and the lead extension; forming an encapsulation over the integrated circuit and surrounding the electrical interconnect and through the hole; and removing a bottom portion of the lead frame resulting in a stand-off lead from the lead extension with the exterior pad on the stand-off lead.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.

Abstract: A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a frame platform and a frame base; forming an elevated paddle on the frame platform and a base pad on the frame base; mounting an integrated circuit over the elevated paddle; forming an encapsulation on the lead frame and over the elevated paddle, the base pad, the integrated circuit, and the internal interconnect; and removing the lead frame to expose an encapsulation recess and an encapsulation base with the base pad exposed along the encapsulation base and the elevated paddle exposed in the encapsulation recess.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a carrier top side; mounting an integrated circuit over the carrier top side; attaching a bottom attachment directly on the integrated circuit; dragging a sandwich connector from the bottom attachment, the sandwich connector having a connector diameter; and attaching a top attachment directly on the sandwich connector, the top attachment wider than the bottom attachment.

Abstract: A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer.

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.

Abstract: A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers.

Abstract: Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.

Abstract: A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps.

Abstract: A semiconductor device includes: a semiconductor substrate that includes a semiconductor; an electrode layer formed on a first surface side inside the semiconductor substrate; a frame layer laminated on the first surface of the semiconductor substrate; a conductor layer formed in an aperture portion formed by processing the semiconductor substrate and the frame layer in such a manner as to expose the electrode layer on the first surface of the semiconductor substrate; a vertical hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate.

Abstract: A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Abstract: A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.

Abstract: A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

Abstract: An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.

Abstract: In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced.

Abstract: A method of making a semiconductor device includes providing a substrate and forming a conductive layer on the substrate. The conductive layer includes a first metal. A semiconductor die is provided. A bump is formed on the semiconductor die. The bump includes a second metal. The semiconductor die is positioned proximate to the substrate to contact the bump to the conductive layer and form a bonding interface. The bump and the conductive layer are metallurgically reacted at a melting point of the first metal to dissolve a portion of the second metal from an end of the bump. The bonding interface is heated to the melting point of the first metal for a time sufficient to melt a portion of the first metal from the conductive layer. A width of the conductive layer is no greater than a width of the bump.

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.

Abstract: Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).

Abstract: A trace routing method for a multi-layer interconnection circuit includes the steps of providing stacked contacts with trace stubs at input/output pads of said interconnection circuit, and limiting contacts between conductive layers to two-level contacts in routing areas where maximum routing density is desired.

Abstract: The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.

Abstract: In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses 10a are formed beforehand at both end portions respectively of the wedge tool lest both end portions in the width direction of the Al ribbon bonded to the pad should contact the pressure bonding surface of the wedge tool.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.

Abstract: A semiconductor device includes (i) a tape base material, (ii) a wiring pattern, (iii) a semiconductor element which is electrically connected with the wiring pattern, (iv) a top-side insulating protective film which covers a top surface of the tape base material and has an top-side opening section provided in a region where the top-side insulating protective film faces the semiconductor element, and (v) a reverse-side insulating protective film which covers a reverse surface of the tape base material and has a reverse-side opening section provided on a reverse side below the top-side opening section. The top-side insulating protective film has a protruding opening section extending outwardly from the region. An opening of the reverse-side opening section is 1.00 time to 8.50 times larger in an area than the region.

Abstract: A plastic package (100) in which a semiconductor chip (101) is adhesively (102) attached to a metal stripe (110a) having an agglomerate structure, and electrically connected to bondable and solderable metal stripes (120) having particulate structures; metal stripes (120) are touching metal stripes (110b) of agglomerate structure to form vertical stacks (150); coats of solder (140) are welded to the agglomerate metal stripes (100a and 110b).

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Abstract: A method for manufacturing an LED module, including steps of: providing a heat conductive plate and an LED die, the heat conductive plate defining a concave groove therein; forming an electrode circuit layer on the heat conductive plate around the concave groove; plating one metal layer on a bottom of the concave groove of the heat conductive plate, and plating another metal layer on the LED die; eutectically bonding the metal layer of the heat conducting plate and the metal layer of the LED die together to form into an eutectic layer; forming electrodes on the LED die, and connecting the electrodes with the electrode circuit layer; and encapsulating the LED die in the concave groove.

Abstract: In a multichip thin package requiring a thickness of submillimeter region, it is difficult to thin the package if the chips are mounted over a usual die pad. According to a technique of the present application, in a manufacturing method of a semiconductor device of a thin resin sealed multichip rectangular package having wire connection between the chips, at least one chip is fixed to a die pad thinned more than a die pad support lead, the die pad is supported by die pad support leads arranged to respectively connect a pair of long sides of the rectangle, and sealing resin is introduced from one side of the pair of long sides when resin molding is performed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle.

Abstract: Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.

Abstract: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection.

Abstract: A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.

Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Abstract: To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted, and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.

Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.

Abstract: A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.