Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.

Abstract: A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

Abstract: An embedded package includes a first semiconductor chip having a first conductive line which has a first sunken area, a second semiconductor chip having a second conductive line which has a second sunken area, wherein the first semiconductor chip and the second semiconductor chip are arranged facing each other, and wherein the first sunken area and the second sunken area are arranged facing each other, a core layer surrounding the first semiconductor chip and the second semiconductor chip, wherein the core layer has a first circuit pattern coupled to an external terminal; and a bump formed in the first and second sunken areas, wherein the bump is coupled to the first circuit pattern.

Abstract: A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.

Abstract: The present invention relates to a semiconductor device and a semiconductor process for making the same. The semiconductor device of the present invention includes a semiconductor substrate, at least one conductive via and at least one insulation ring. The semiconductor substrate has a first surface. The conductive via is disposed in the semiconductor substrate. Each conductive via has a conductor and an insulation wall disposed the peripheral of the conductor, and the conductive via is exposed on the first surface of the semiconductor substrate. The insulation ring is disposed the peripheral of the conductive via, and the depth of the insulation ring is smaller than that of the insulation wall. Since the insulation ring is disposed the peripheral of the conductive via, the insulation ring can protect the end of the conductive via from being damaged.

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted to a die-attach area and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die-attach area are all covered with a molding material, with portions of the electrical contacts and die-attach area protruding from a bottom surface of the molding material.

Abstract: A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Abstract: A method for manufacturing a chip package includes exposing a ground ring out of encapsulating material in a direct or indirect way and forming a conductive film electrically connected to the ground ring so as to form an EMI shield and prevent external EMI. The present invention also massively forms conductive film for package structure for lowering the complexity and cost of manufacturing processes.

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

Abstract: A wiring circuit layer 2 having a connecting conductor part 21 that can be connected to an electrode 31 of a semiconductor element 3 is formed on a metal support substrate 1 in a way such that the wiring circuit layer can be separated from the substrate 1, and that the connecting conductor part 21 is exposed on the upper face of the wiring circuit layer. The wiring circuit layer 2 is laminated on the element 3 while in a wafer state, and the connecting conductor part 21 and the electrode 31 are connected. Subsequently, the support substrate 1 is peeled from the wiring circuit layer 2, and the wafer is diced, whereby individual semiconductor devices are obtained.

Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Abstract: A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.

Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: A device having electronic components mounted therein has a first electronic component having an external terminal on a first surface and a heat spreader on a second surface, at least one second electronic component that is placed in the direction of a second surface of the first electronic component, a flexible circuit board that is electrically connected to the first electronic component and at least one second electronic component, and at least the part to which at least one second electronic component is connected is located on the second surface side of the first electronic component, and a spacer that is located between at least part of the flexible circuit board and the second surface of the first electronic component. The spacer can prevent heat from the first electronic component from being directly transferred to the second electronic component.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Abstract: An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conductive material and connecting the signal pattern of the wiring board and the signal electrode pad of the semiconductor element, and a second connection portion being made of a conductive material and connecting the power-source pattern of the wiring board and the power-source electrode pad of the semiconductor element. The conductive material of the first connection portion and the conductive material of the second connection portion are selected such that the conductive material of the second connection portion has an electrical resistance which is lower than an electrical resistance of the conductive material of the first connection portion.

Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Abstract: A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Abstract: A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the integrated circuit and the solder mask layer. One or more crack seal rings are disposed on the solder mask surface. The crack seal rings are copper traces with terminals that allow current to be applied to the traces. A broken trace (open circuit condition) is indicative of a crack in the package. Thus, electrical testing is performed to detect physical defects.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.

Abstract: An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body on the integrated circuit die and the metal sheet, and forming a ball pad, a bond finger, or a combination thereof from the metal sheet that is not protected by the molded package body; coupling a circuit package on the ball pad; and forming a component package on the substrate, the base integrated circuit, and the leadframe interposer.

Abstract: A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit.

Abstract: A semiconductor device includes a plurality of storage node contact plugs passing through a first interlayer dielectric layer, a plurality of storage nodes in contact with the storage node contact plugs, each including a first electrode having a pillar shape and a second electrode spaced apart from the first electrode by a certain distance and surrounding the first electrode, and a second interlayer dielectric layer filling a gap between the second electrodes of neighboring storage nodes.

Abstract: A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.

Abstract: A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Abstract: A conventional semiconductor device has a problem that a frame constituting a heat sink is expensive and the heat sink is highly likely to come off a resin package. A semiconductor device of the present invention reduces the frame price because a heat sink is formed by subjecting a frame with a uniform thickness to pressing or something similar. Furthermore, the heat sink is less likely to come off a resin package because step regions of the heat sink are pressed as connection regions to be connected to the other frame in which leads are arranged, and thereby, resin constituting the resin package goes around the step regions and reaches up to back surfaces of the respective step regions. Moreover, a structure which makes the heat sink much less likely to come off is realized because recessed portions are arranged in the step regions of the heat sink.

Abstract: A semiconductor element to be mounted on a circuit carrier includes a semiconductor die and at least one lead frame. In order to reduce the size required for mounting a semiconductor die on a circuit carrier, a semiconductor element includes a semiconductor die and at least one lead frame. The at least one lead frame is directly attached to the semiconductor die at a connection region of the semiconductor die, and the connection region provides an electrical connection to and mechanical support for the semiconductor die.

Abstract: A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.

Abstract: A semiconductor structure having: an electrically and thermally conductive layer disposed on one surface of the semiconductor structure; an electrically and thermally conductive heat sink; a electrically and thermally conductive carrier layer; a plurality of electrically and thermally nano-tubes, a first portion of the plurality of nano-tubes having proximal ends disposed on a first surface of the carrier layer and a second portion of the plurality of nano-tubes having proximal ends disposed on an opposite surface of the carrier layer; and a plurality of electrically and thermally conductive heat conductive tips disposed on distal ends of the plurality of nano-tubes, the plurality of heat conductive tips on the first portion of the plurality of nano-tubes being attached to the conductive layer, the plurality of heat conductive tips on the second portion of the plurality of nano-tubes being attached to the heat sink.

Abstract: To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.

Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole.

Abstract: A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.

Abstract: A compact, high-performance thermoelectric conversion module includes a laminate having a plurality of insulating layers, p-type thermoelectric semiconductors and n-type thermoelectric semiconductors formed by a technique for manufacturing a multilayer circuit board, particularly a technique for forming a via-conductor. Pairs of the p-type thermoelectric semiconductors and the n-type thermoelectric semiconductors are electrically connected to each other in series through p-n connection conductors to define thermoelectric conversion element pairs. The thermoelectric conversion element pairs are connected in series through, for example, series wiring conductors. The thermoelectric semiconductors each have a plurality of portions in which the peak temperatures of thermoelectric figures of merit are different from each other. These portions are distributed in the stacking direction of the laminate.

Abstract: A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive polymeric compound 105 between bodies 104. Metal bodies 104 form metal inter-diffusions with carrier 102 and extend from the carrier across thickness 103a, stopping at and contacting second chip surface 101b. The high thermal conductivity of metal bodies 104 greatly increases the thermal conductivity of the attachment layer. The metal bodies may be arrayed in a regularly spaced pattern in x- and y-directions, as well as in enhanced concentrations in locations of thermal hot spots and of high thermomechnical stresses. In the latter application, the metal bodies prevent the growth of microcracks and delamination.

Abstract: A method of making a semiconductor device includes providing a substrate and forming a conductive layer on the substrate. The conductive layer includes a first metal. A semiconductor die is provided. A bump is formed on the semiconductor die. The bump includes a second metal. The semiconductor die is positioned proximate to the substrate to contact the bump to the conductive layer and form a bonding interface. The bump and the conductive layer are metallurgically reacted at a melting point of the first metal to dissolve a portion of the second metal from an end of the bump. The bonding interface is heated to the melting point of the first metal for a time sufficient to melt a portion of the first metal from the conductive layer. A width of the conductive layer is no greater than a width of the bump.

Abstract: A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.

Abstract: A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.

Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.

Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Abstract: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.