Attaching Or Detaching Leads Or Other Conductive Members, To Be Used For Carrying Current To Or From Device In Operation (epo) Patents (Class 257/E21.506)
  • Patent number: 8097491
    Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: January 17, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hung-Yuan Hsu, Sui-An Kao
  • Publication number: 20120009738
    Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 12, 2012
    Inventors: Grant A. Crawford, Islam Salama
  • Publication number: 20120009737
    Abstract: When chip-scale molding system is employed for QFP, the number of semiconductor devices available from a leadframe decreases because cavities each requires a runner portion. This problem can be overcome by employing MAP system, but use of a laminate tape increases the production cost. In through mold system, each cavity needs an ejector pin, which however makes it difficult to place a support pillar. The present application provides a manufacturing method of a semiconductor device by filling, while sandwiching a leadframe between mold dies having a matrix-state cavity group in which cavity columns obtained by linking mold cavities in series via a through gate have been placed in rows, a sealing resin in the cavities. In this method, the matrix-state cavity group has, at the cavity corner portions thereof, a support pillar having a cross-section striding over all the cavities adjacent to the cavity corner portions when viewed planarly.
    Type: Application
    Filed: June 15, 2011
    Publication date: January 12, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Bunshi KURATOMI, Fukumi SHIMIZU
  • Publication number: 20120009787
    Abstract: A method for forming a masking layer of a semiconductor device includes forming a plurality of pillar structures separated by a trench, forming a gap-fill material partially filling the trench and exposing an upper sidewall of each pillar structure, forming a masking layer that covers the pillar structures and the gap-fill material, performing an ion implantation to the masking layer to form an implanted portion covering upper portion of the gap-fill material and one side of the upper sidewalls of each pillar structure and a non-implanted portion covering the other side of the upper sidewalls of each pillar structure, forming a sacrificial layer over the masking layer, exposing the non-implanted portion of the masking layer, and selectively removing the exposed non-implanted portion.
    Type: Application
    Filed: November 17, 2010
    Publication date: January 12, 2012
    Inventor: Won-Kyu KIM
  • Publication number: 20120009734
    Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
  • Publication number: 20120001310
    Abstract: A package for a semiconductor device according to the present invention includes at least one through hole 6 provided on at least one of lead frames 1 and 2. Thus when resin is injected to form a mounting region 4 of a semiconductor element while holding the lead frames 1 and 2, the resin can be injected from the back sides of the lead frames 1 and 2 through the through hole 6 serving as a resin flow path, thereby shortening the resin flow path and suppressing the occurrence of portions unfilled with the resin and poor appearances.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Masanori Nishino, Hiroshi Horiki
  • Publication number: 20120003771
    Abstract: A method for producing a thermoelectric module comprises steps of positioning electrodes (4) on a pair of current-supplying/pressing members (2) arranged to face each other, at their surfaces facing each other; arranging a plurality of thermoelectric elements (3) to be interposed between the electrodes (4); and bonding the electrodes (4) and the thermoelectric elements (3) by supplying an electric current to pass through the electrodes (4) and the thermoelectric elements (3) while pressing the electrodes (4) and the thermoelectric elements (3) by means of the current-supplying/pressing members (2), wherein the method further comprises a step of forming an intermediate layer (5) containing an electroconductive metal powder and having elasticity, between each of the electrodes (4) and the thermoelectric element (3) to be bonded thereto.
    Type: Application
    Filed: March 1, 2010
    Publication date: January 5, 2012
    Inventors: Naoki Uchiyama, Kazuya Kubo, Masashi Mikami, Keizo Kobayashi, Toshiyuki Nishio
  • Publication number: 20120001308
    Abstract: In a semiconductor module, a first heat sink is disposed on a rear surface of a first semiconductor chip constituting an upper arm, and a second heat sink is disposed on a front surface of the first semiconductor chip through a first terminal. A third heat sink is disposed on a rear surface of a second semiconductor chip constituting a lower arm, and a fourth heat sink is disposed on a front surface of the second semiconductor chip through a second terminal. A connecting part for connecting between the upper arm and the lower arm is integral with the first terminal, and is connected to the third heat sink while being inclined relative to the first terminal.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 5, 2012
    Applicant: DENSO CORPORATION
    Inventors: Keita Fukutani, Kuniaki Mamitsu, Yasushi Ookura, Masayoshi Nishihata, Hiroyuki Wado, Syun Sugiura
  • Publication number: 20120001339
    Abstract: The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein an interposer, such as a through-silicon via interposer, may be used in a bumpless build-up layer package to facilitate stacked microelectronic components.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Inventor: Pramod Malatkar
  • Publication number: 20120001311
    Abstract: In a package for a semiconductor device according to the present invention, steps 10 are provided at least on the sides of lead frames 1 and 2 at exposed portions in the opening of a resin part 3, thereby increasing adhesion between the lead frames 1 and 2 and resin and suppressing leakage of molding resin and intrusion of outside air or moisture from a gap between the lead frames 1 and 2 and the resin.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Masanori Nishino, Hiroshi Horiki
  • Publication number: 20110316167
    Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Inventors: Paul Alan McConnelee, Kevin Matthew Durocher, Scott Smith, Donald Paul Cunningham
  • Publication number: 20110316140
    Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Inventors: Ravi K. Nalla, Mathew J. Manusharow, Drew Delaney
  • Publication number: 20110316134
    Abstract: According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 29, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi ISHII, Naohisa Okumura, Taku Nishiyama
  • Publication number: 20110318883
    Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
    Type: Application
    Filed: September 6, 2011
    Publication date: December 29, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Josef Maynollo, Thomas Detzel
  • Publication number: 20110312133
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 22, 2011
    Inventors: Soo-San Park, Sang-Ho Lee, DaeSik Choi
  • Publication number: 20110312134
    Abstract: The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 22, 2011
    Inventor: YUICHI MACHIDA
  • Publication number: 20110312131
    Abstract: In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 22, 2011
    Inventors: Mukul Renavikar, Daewoong Suh, Carl Deppisch, Abhishek Gupta
  • Publication number: 20110309516
    Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
  • Publication number: 20110309490
    Abstract: A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 22, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Fa Lu, Chung-Shi Liu, Chen-Hua Yu, Wei-Yu Chen, Cheng-Ting Chen
  • Patent number: 8080885
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: December 20, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Rui Huang
  • Publication number: 20110304053
    Abstract: An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material.
    Type: Application
    Filed: June 11, 2010
    Publication date: December 15, 2011
    Applicant: International Business Machines Corp.
    Inventors: Qinghuang Lin, Dirk Pfeiffer, Ratnam Sooriyakumaran
  • Patent number: 8076181
    Abstract: A packaging technique is described for QFNs, DFN, and other surface mount packages that allows the sides of leads to be plated with a wettable metal prior to the lead frames being singulated from the lead frame sheet. The leads of the lead frames in the sheet are shorted together and to the body of the lead frame sheet by a sacrificial interconnect structure. Chips are mounted to the lead frames and encapsulated, leaving the bottoms of the leads exposed. The lead frame sheet is then sawed along boundaries of the lead frames but not sawed through the interconnect structure. The sawing exposes at least a portion of the sides of the leads. The leads are then electroplated while the leads are biased with a bias voltage via the interconnect structure. After the plating, the lead frame sheet is sawed completely thorough the interconnect structure to singulate the lead frames and prevent the interconnect structure from shorting the leads together.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: December 13, 2011
    Assignee: Linear Technology Corporation
    Inventors: David A. Pruitt, Lothar Maier
  • Publication number: 20110298110
    Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 8, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20110300670
    Abstract: The occurrence of a resin seal failure is suppressed. A molding step is carried out using a lead frame in which there are formed multiple air vent portions for discharging gas in each cavity formed in the upper die of a molding die to outside the cavity. The air vent portions are formed at positions overlapping with the other corner portions, arranged inside a gate portion of the cavity. Each of the air vent portions is led out from the other corner portions of the cavity to outside a clamp area and is extended along sides of the cavity, respectively, in the clamp area.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 8, 2011
    Inventors: Shigeki TANAKA, Atsushi Fujisawa, Masahiro Tani, Satoru Suzuki
  • Publication number: 20110298125
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a pillar ball; mounting an interposer having a first functional side and a second functional side over the pillar ball and a semiconductor chip; encapsulating the interposer, the pillar ball, and the semiconductor chip with an encapsulation; forming a via through the first functional side and the second functional side of the interposer, and through the encapsulation to expose a portion of the pillar ball; and filling the via with a pillar post.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Inventor: ChanHoon Ko
  • Publication number: 20110300668
    Abstract: An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventor: Pirooz Parvarandeh
  • Publication number: 20110299255
    Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.
    Type: Application
    Filed: August 18, 2011
    Publication date: December 8, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Teru NAKANISHI, Nobuyuki HAYASHI, Masaru MORITA, Yasuhiro YONEDA
  • Publication number: 20110298113
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, including having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.
    Type: Application
    Filed: August 15, 2011
    Publication date: December 8, 2011
    Inventors: Frederick Rodriguez Dahilig, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Publication number: 20110298114
    Abstract: A stacked leadframe assembly is disclosed. The stacked leadframe assembly includes a first die having a surface that defines a mounting plane, a first leadframe stacked over and attached to the first die, a second die stacked over and attached to the first leadframe; and a second leadframe stacked over and attached to the second die. The leadframes have die paddles with extended side panels that have attachment surfaces in the mounting plane.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Inventor: David Alan PRUITT
  • Patent number: 8071470
    Abstract: A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: December 6, 2011
    Assignee: Carsem (M) SDN. BHD.
    Inventors: Lily Khor, Yong Lam Wai, Lau Choong Keong
  • Patent number: 8072053
    Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 6, 2011
    Assignee: Kaixin Inc.
    Inventor: Tung Lok Li
  • Patent number: 8071438
    Abstract: A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 6, 2011
    Assignee: BeSang Inc.
    Inventor: Sang-Yun Lee
  • Patent number: 8071426
    Abstract: A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: December 6, 2011
    Assignee: Utac Thai Limited
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Publication number: 20110291254
    Abstract: Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with at least one die through electrically conducting bumps or balls and electrically conducting ribbons. Embodiments of the present invention may permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.
    Type: Application
    Filed: August 9, 2011
    Publication date: December 1, 2011
    Applicant: GEM Services, Inc.
    Inventors: James Harnden, Richard K. Williams, Anthony Chia, Teng Hui, Hongbo Yang, Zhou Ming, Anthony C. Tsui
  • Publication number: 20110291265
    Abstract: A semiconductor integrated circuit having a multi-chip structure includes a number of stacked semiconductor chips. Each of the semiconductor chips includes a first through electrode formed through the semiconductor chip, a first bump pad formed over the semiconductor chip at a region where the first bump pad is separated from the first through electrode, a first internal circuit formed inside the semiconductor chip, coupled to the first through electrode through a first metal path, and coupled to the first bump pad through a second metal path; and a redistribution layer (RDL) formed over a backside of the semiconductor chip.
    Type: Application
    Filed: July 7, 2010
    Publication date: December 1, 2011
    Inventors: Sin-Hyun Jin, Sang-jin Byeon
  • Publication number: 20110291257
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; pressing an encapsulation onto the package carrier and with the integrated circuit therein; mounting a conductive frame, having a vertical pillar integral with a horizontal cover, through the encapsulation, over the integrated circuit, and the vertical pillar on the package carrier and the horizontal cover on the encapsulation; and forming a contact from the horizontal cover.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Inventor: Reza Argenty Pagaila
  • Publication number: 20110291261
    Abstract: An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Fleischman, Eric D. Perfecto, Sudipta K. Ray
  • Publication number: 20110291286
    Abstract: An electronic device including a die-pad area, a die fixed to the die-pad area, a connection terminal, and a ribbon of conductive material. The ribbon is electrically connected to the die and to the connection terminal, and has a prevalent dimension along a first axis, a width, measured along a second axis, which is transverse to the first axis, and a thickness, which is negligible with respect to the width; the ribbon moreover has a cross section that defines a concave geometrical shape.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 1, 2011
    Applicant: STMicroelectronics S.r.I.
    Inventors: Agatino Minotti, Giuseppe Cristaldi
  • Publication number: 20110291266
    Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.
    Type: Application
    Filed: July 9, 2010
    Publication date: December 1, 2011
    Inventors: Sin-Hyun Jin, Jong-Chern Lee
  • Patent number: 8067273
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 29, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Publication number: 20110284997
    Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chi on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.
    Type: Application
    Filed: September 29, 2010
    Publication date: November 24, 2011
    Inventors: Yuping Gong, Yan Xun Xue
  • Publication number: 20110284999
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.
    Type: Application
    Filed: August 3, 2011
    Publication date: November 24, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Publication number: 20110285001
    Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.
    Type: Application
    Filed: August 1, 2011
    Publication date: November 24, 2011
    Inventor: Zigmund Ramirez Camacho
  • Publication number: 20110278718
    Abstract: A multi-chip module (MCM) that includes at least two substrates, having facing surfaces, which are mechanically coupled by a set of coupling elements having a reflow characteristic, is described. One of the two substrates includes another set of coupling elements having another reflow characteristic, which is different than the reflow characteristic. These different reflow characteristics of the sets of coupling elements allow different temperature profiles to be used when bonding the two substrates to each other than when bonding the one of the two substrates to a carrier. For example, the temperature profiles may have different peak temperatures and/or different durations from one another. These reflow characteristics may facilitate low-cost, high-yield assembly and alignment of the substrates in the MCM, and may allow temperature-sensitive components to be included in the MCM.
    Type: Application
    Filed: May 17, 2010
    Publication date: November 17, 2011
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Hiren D. Thacker, Jing Shi, John E. Cunningham, Ashok V. Krishnamoorthy
  • Publication number: 20110278714
    Abstract: A chip package device includes a substrate having a chip bonding area and at least one contact pad, a chip having an active surface and an inactive surface, at least one wire, an adhesive layer, a heat dissipation element, and an encapsulation. The chip is disposed on the chip bonding area with its inactive surface facing the substrate. The chip includes at least one bonding pad disposed on the active surface. The wire correspondingly connects the at least one bonding pad and the at least one contact pad. The adhesive layer covers the active surface of the chip and encloses a portion of the wire extending over the bonding pad. The heat dissipation element is attached to the adhesive layer and covers the chip. The encapsulation partially encloses the periphery of the assembly including the chip, the adhesive and the heat dissipation element, and has an indented opening to expose the surface of the heat dissipation element.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 17, 2011
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: HAN CHENG HSU, TING CHANG YEH
  • Publication number: 20110281398
    Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.
    Type: Application
    Filed: July 21, 2011
    Publication date: November 17, 2011
    Inventors: Xiaochun Tan, Zhining Li, Xiaolan Jiang
  • Patent number: 8058104
    Abstract: A method for manufacturing a semiconductor device package including an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface at the first package face and a second contact surface at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pad on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled using a lead frame having pre-formed leads, with or without taping, or using partially etched lead frames. A stack of the semiconductor device packages may be formed.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: November 15, 2011
    Assignee: Unisem (Mauritius) Holdings Limited
    Inventors: Shafidul Islam, Romarico S. San Antonio
  • Patent number: 8058099
    Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 15, 2011
    Assignee: SanDisk Technologies Inc.
    Inventors: Cheemen Yu, Vani Verma, Hem Takiar
  • Patent number: 8058105
    Abstract: A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: November 15, 2011
    Assignee: Unimicron Technology Corporation
    Inventor: Shih-Ping Hsu
  • Publication number: 20110272768
    Abstract: Provided is a lead frame, an electronic device provided with a lead frame, a method of producing a lead frame, and a method of producing an electronic device provided with a lead frame that has been produced by the method of producing a lead frame, in which a lead frame is not corroded, a mechanical strength of the lead frame is not lowered, it is not necessary to carry out the conventional plating processing steps composed of two stages, the processes are simple, a cost is lower, and a large amount of waste liquid such as plating processing liquid is not generated, thereby preventing an environment from being affected. The lead frame includes an outer lead part and an inner lead part, and plating is carried out on at least a part of one or both of the outer lead part or the inner lead part.
    Type: Application
    Filed: September 12, 2008
    Publication date: November 10, 2011
    Applicants: SUN-A CORPORATION, MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Toshiaki Kawanishi, Toshihiro Hosoi, Kenjiro Izutani, Hiroyuki Nakamura, Yutaka Osawa, Hiroaki Sunada, Tetsuyasu Takahashi