Abstract: A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench.

Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.

Abstract: A semiconductor device that includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.

Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.

Abstract: A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.

Abstract: X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.

Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.

Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.

Abstract: A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.

Abstract: For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.

Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).

Abstract: A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.

Abstract: An approach for a coplanar waveguide structure in stacked multi-chip systems is provided. A method of manufacturing a semiconductor structure includes forming a first coplanar waveguide in a first chip. The method also includes forming a second coplanar waveguide in a second chip. The method further includes directly connecting the first coplanar waveguide to the second coplanar waveguide using a plurality of chip-to-chip connections.

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract: An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region.

Abstract: A structure comprises a first die, a second die, an interposer, a third die, and a fourth die. The first die and the second die each have a first surface and a second surface. First conductive connectors are coupled to the first surfaces of the first and second dies, and second conductive connectors are coupled to the second surfaces of the first and second dies. The interposer is over the first and second dies. A first surface of the interposer is coupled to the first conductive connectors, and a second surface of the interposer is coupled to third conductive connectors. The third and fourth dies are over the interposer and are coupled to the third conductive connectors. The first die is communicatively coupled to the second die through the interposer, and/or the third die is communicatively coupled to the fourth die through the interposer.

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.

Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Abstract: Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

Abstract: One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.

Abstract: A method (80) entails providing (82) a structure (117), providing (100) a controller element (102, 24), and bonding (116) the controller element to an outer surface (52, 64) of the structure (117). The structure includes a sensor wafer (92) and a cap wafer (94). Inner surfaces (34, 36) of the wafers (92, 94) are coupled together, with sensors (30) interposed between the wafers (92, 94). One wafer (94, 92) includes a substrate portion (40, 76) with bond pads (42) formed on its inner surface (34, 36). The other wafer (94, 92) conceals the substrate portion (40, 76). After bonding, methodology (80) entails forming (120) conductive elements (60) on the element (102, 24), removing (126) material sections (96, 98, 107) from the wafers (92, 94, 102) to expose the bond pads (42), forming (130) electrical interconnects (56), applying (134) packaging material (64), and singulating (138) to produce sensor packages (20, 70).

Abstract: A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration.

Abstract: One embodiment is a packaged device having multiple layers. Another embodiment is a method of forming a packaged device having multiple layers. Conductive layers and insulating layers can be formed with openings exposing semiconductor devices. The semiconductor devices can be wire-bonded to the conductive layers. In some embodiments, parasitic effects and a relative footprint of the packaged device can be reduced.

Abstract: A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed above the first chip. The vertical conductive line is electrically connected to the first chip and the second chip. The vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip.

Abstract: To protect victim bondwires in a packaged electronic component from crosstalk induced by noisy aggressor bondwires, shielding bondwires are configured between the victim bondwires and the aggressor bondwires. The shielding bondwires, on either side of the victim bondwires, are connected to the same reference voltage on the package side of the component and to each other on the die side of the component, e.g., via a metal connection mounted on the die. As configured in one embodiment, the shielding bondwires and metal connection form a two-dimensional Faraday cage that shields the victim bondwires from crosstalk induced by the aggressor bondwires.

Abstract: One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.

Abstract: A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit.

Abstract: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.

Abstract: Devices and systems for insulating integrated circuits from ultraviolet (“UV”) light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating layer overlays the second UV blocking layer. An interconnect trench is defined in the second insulating layer and second UV blocking layer. The conductive structure is electrically connected to the conductive feature and extends into the via opening and along the interconnect trench.

Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Abstract: A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate.

Abstract: A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.

Abstract: There is offered a semiconductor integrated circuit provided with a function to electrically identify a location where a defect such as chipping of an LSI die or separation of resin is caused. Corresponding to each of the four corners of a semiconductor substrate, each of L-shaped first through fourth peripheral wirings having a first end and a second end is disposed on a periphery of the semiconductor substrate. The first end of each of the first through fourth peripheral wirings is connected with a power supply wiring. Each of first through fourth detection circuits detects breaking of corresponding each of the first through fourth peripheral wirings in response to a voltage at the second end of corresponding each of the first through fourth peripheral wirings, and outputs corresponding each of first through fourth detection signals to corresponding each of output pads.

Abstract: This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component, a second package component, and a first set of conductive elements coupling the first package component to the second package component. A first polymer-comprising material is molded on the first package component and surrounds the first set of conductive elements. The first polymer-comprising material has an opening therein exposing a top surface of the second package component. A third package component and a second set of conductive elements couples the second package component to the third package component.

Abstract: A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.

Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.