Abstract: The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A plurality of memory cells, arranged in row and column fashion, is formed on each second well region. Corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.

Abstract: A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.

Abstract: Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the third conductive region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region.

Abstract: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

Abstract: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).

Abstract: Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.

Abstract: Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on insulator substrate or a large bandgap semiconductor substrate having multiple ferroelectric or magnetic memory cells disposed on it. In yet other embodiments, a high temperature nonvolatile integrated device comprises a sapphire, silicon on insulator, or a large bandgap substrate having programmable read only memory (PROM) cells or electrically erasable PROM (EEPROM) cells disposed on it.

Abstract: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.

Abstract: A semiconductor memory device includes a semiconductor substrate including an insulating layer, a charge storage region of a first conductivity type on the insulating layer, and an insulating film on the insulating layer and surrounding the charge storage region. A body region of the first conductivity type is on an upper surface of the charge storage region, and a gate stack including a gate electrode and a gate insulating film is on the body region. A source region and a drain region of a second conductivity type are on opposite sides of the body region. The charge storage region extends further towards the semiconductor substrate than the source region and/or the drain region. Methods of forming semiconductor memory devices are also disclosed.

Abstract: The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film thickness of a first silicon nitride film in the first ONO film is larger than the film thickness of a second silicon nitride film in the second ONO film.

Abstract: A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.

Abstract: The storage system of the present invention preserves data long-term by using memory devices such as flash memory devices. A flash memory mounting unit of a storage apparatus has a plurality of flash memory devices. Logical devices are set up in the storage region of the flash memory devices. A start-up scheduler controls start-up of internal refresh processing and external refresh processing. A refresh function management table respectively manages the method of refreshing the data stored in the flash memory devices and the refresh time, for each logical device. The start-up scheduler, on discovering that a logical device has reached its refresh period, sends a start-up command to the storage apparatus or external apparatus, to start-up internal refresh processing or external refresh processing.

Abstract: A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in sectors of memory cells. The memory device is between the cells of the opposite word lines belonging to at least one of the sectors of the matrix. A lateral coating along the direction of the bit lines has at least one conductive layer with a contact terminal being selectively biased or left floating during each program, read or erase operation. Each cell belongs to a sector.

Abstract: A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged in an interconnect layer above the first cell well lines and connecting the first cell well lines to one another electrically; and a cell source line connecting source terminals of the select transistors in each memory cell column.

Abstract: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator.

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide -nitride-oxide or ONO) is enhanced in the dilute steam oxidation.

Abstract: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 chemistry. The inner edges of the sloped ARC areas reduce the original photo-defined space since the underlying layers are now defined by the sloped edges.

Abstract: A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selecting the page mode causes the device to output selected memory pages.

Abstract: The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less than all of a block in response to a read command from a host or memory controller. The small portion is selected for the scrub read because of its greater vulnerability than other portions of the block to being disturbed as a result of the commanded partial block data read. This then determines, as the result of reading a small amount of data, whether at least some of the data in the block was disturbed by the command data read to a degree that makes it desirable to refresh the data of the block.

Abstract: A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells.

Abstract: A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention.

Abstract: A method and system for providing a content addressable memory cell (CAM) as well as the CAM are disclosed. In one aspect, the method and system include providing a plurality of memory cells, at least one search line and at least one match line. Each of the CAM cells includes a FLOating gate Tunnel OXide (FLOTOX) element. The FLOTOX element includes a single floating gate transistor and a high voltage select transistor and can store at least a portion of a data word. Each CAM cell also preferably includes at least one low voltage transistor capable of comparing the portion of data word stored in the FLOTOX element with the portion of searched word. The search line(s) provide search word(s). The comparator(s) are connected with the search line(s) and the memory cells. The comparator(s) compare the data word stored by the portion of the plurality of memory cells and the search word. The match line(s) indicate whether the search word matches the data word stored by the portion of the plurality of memory cells.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.

Abstract: Systems, apparatuses and methods for controlling access operations in a memory device that may include a memory controller(s) and memory. Commands, registers and/or other mechanisms may be defined to be supported by the memory device, where such commands, registers, and/or other mechanisms facilitate the control of read and write/erase operations to allow these operations to be performed simultaneously. Thus, a write and/or erase operation may be initiated on a first memory, a read operation initiated by a set of commands on a second memory, wherein the read and write/erase operations are performed substantially at the same time.

Abstract: In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to the flash memory chip) using power supplied from the host equipment to the contact IC card interface, and executes initialization of the flash memory chip between activation of the host equipment and completion of user authentication instructed by the host equipment.

Abstract: A chip select controller for a non-volatile memory device includes a first chip enable signal transfer unit, a second chip enable signal transfer unit, a first chip select pad, a second chip select pad, a third chip select pad and a chip select unit. The first chip enable signal transfer unit buffers first and second chip enable signals according to a control signal. The second chip enable signal transfer unit buffers third and fourth chip enable signals according to the control signal. The first chip select pad is configured to transfer a first chip select signal. The second chip select pad is configured to transfer a second chip select signal. The third chip select pad is configured to transfer the second chip select signal. The chip select unit addresses a specific chip according to the first chip select signal and the second chip select signal.

Abstract: A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the storing portion and the transistors in the write portion. In an alternate embodiment, circuit has a plurality of read ports. In an alternate embodiment, selecting the optimal gate oxide thickness for the transistors in circuit allows the trade-off between transistor switching speed and gate leakage current to be optimized to produce a circuit having a fast enough read access time and a low enough standby power.

Abstract: A memory device is disclosed. A floating gate is disposed overlying a substrate. A tunneling dielectric layer is interposed between the floating gate and the substrate. An inter poly dielectric layer is disposed overlying the floating gate and the substrate. A word line is disposed overlying the floating gate, extending in a row direction. A bit line is disposed in the substrate, extending in a column direction, wherein the bit line is partially overlapped by the floating gate and the word line.

Abstract: A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.

Abstract: A semiconductor memory device and methods thereof. The example semiconductor memory device may include a semiconductor substrate, a first source line and a second source line oriented in a first direction, the first and second source lines not in contact with each other, at least one bit line oriented in the first direction and at least one drain positioned between the first and second source lines and the at least one bit line. A first example method may include applying a first voltage to a source line, connected to the memory cell, during a write operation of the memory cell and applying a second voltage to the source line during a read operation of the memory cell, the first and second voltages not being the same and the second voltage not being a ground voltage.

Abstract: A balanced program rate on NVM cells is achieved by (i) scrambling data bits and user bits; and (ii) shifting ED bits (of data and user bits) according to an incremental shift number, which may be the PBE-counter (which provides an incremental number). ED bits for the LSS may also be shifted, according to an incremental shift number (which may be the PBE-counter). The ED bits of the shift-niumber inherently have an evenly balanced distribution The ED bits of the PBE-counter inherently have an evenly balanced distribution.

Abstract: The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is coupled to an associated bit line. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, responsively connect the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.

Abstract: A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.

Abstract: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of plural memory cells arranged in matrix. Each memory cell includes a first gate insulator layer formed on a semiconductor substrate, a floating gate formed on the semiconductor substrate with the first gate insulator layer interposed therebetween, a second gate insulator layer formed on the floating gate, and a control gate formed on the floating gate with the second gate insulator layer interposed therebetween. The first gate insulator layer is a first cavity layer.

Abstract: Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.

Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

Abstract: Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage node is less than a length of the channel. The embodiment further includes a memory cell with a gate separated from the storage node by a second dielectric, wherein a length of the gate is greater than a length of the storage node.

Abstract: A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data.

Abstract: The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively disposed on both sides of the first gate. The semiconductor layer is disposed on the first unit. The second unit is disposed on the semiconductor layer and is in mirror symmetry to the first unit. The second unit includes a second gate and a third and a fourth charge trapping layer respectively disposed on both sides of the second gate. The doped region is disposed at both sides of the semiconductor layer and serves as a common source/drain region of both the first and the second unit.

Abstract: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device.

Abstract: A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation on the device in which the monitoring is performed by the device. A grade of the device is derived from the value. Preferred longevity parameters include a ratio of successfully-processed data to unsuccessfully-processed data and a deviation in a power consumption of the device. The grade serves as a forecast of a life expectancy of the memory. Preferred grades include: a comparison grade, a maximum grade, and an average grade.

Abstract: A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention.

Abstract: An OTP memory device and method for testing the same is disclosed. The memory device includes a number of memory cells and each memory cell has an initial threshold voltage. Each memory cell is programmed to have a first threshold voltage larger than a maximum value of the initial threshold voltages in the test program operation. When the memory device is test pass, the memory device is directly provided for a user program operation without need of an erase operation.

Abstract: A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

Abstract: A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit line control circuit comprises a first transistor and a second transistor with a breakdown voltage higher than that of the first transistor, the second transistor being disposed between the first transistor and a bit line in the memory cell array to be serially connected to the first transistor, and wherein a connection node between the first and second transistors is fixed in potential at a data erase time.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.