Abstract: A gas sensor package is configured such that an output change part is provided in the gas sensor package including a gas sensor so that a resistance output mode can be changed to a voltage output mode, thereby enabling the gas sensor to have a regular initial voltage value by compensating a resistance change value to an initial gas sensing material. According to embodiments of the present application, a gas sensor package is configured such that a gas moving separation part is formed between a gas sensing element and a substrate with regard to a structure in which a gas sensing element is mounted to the substrate in a flip chip bonding method so that gas can be smoothly moved and thus gas sensing efficiency can be maximized.

Abstract: One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.

Abstract: A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.

Abstract: Disclosed is an apparatus for forming an encapsulation material for a light emitting device. The apparatus for forming an encapsulation material comprises: an upper mold on which is mounted a substrate having a plurality of optical semiconductors; a lower mold arranged opposite the upper mold; a resin-capture space for capturing a resin between the upper mold and the lower mold; and an ejector pin for dividing the resin-capture space into a plurality of spaces at the position where the encapsulating material is formed, thereby dividing the encapsulation material into a plurality of parts formed on the substrate.

Abstract: A method of determining a physical characteristic of an adhesive material on a semiconductor device element using structured light is provided. The method includes the steps of: (1) applying a structured light pattern to an adhesive material on a semiconductor device element; (2) creating an image of the structured light pattern using a camera; and (3) analyzing the image of the structured light pattern to determine a physical characteristic of the adhesive material. Additional methods and systems for determining physical characteristics of semiconductor devices and elements using structured light are also provided.

Abstract: A back contact solar cell is described which includes a semiconductor light absorbing layer; a first-level metal layer (M1), the M1 metal layer on a back side of the light absorbing layer, the back side being opposite from a front side of the light absorbing layer designed to receive incident light; an electrically insulating backplane sheet backside of said solar cell with the M1 layer, the backplane sheet comprising a plurality of via holes that expose portions of the M1 layer beneath the backplane sheet; and an M2 layer in contact with the backplane sheet, the M2 layer made of a sheet of pre-fabricated metal foil material comprising a thickness of between 5-250 ?m, the M2 layer electrically connected to the M1 layer through the via holes in the backplane sheet.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

Abstract: A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.

Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

Abstract: The present invention relates to an LED metal substrate package, and particularly, to an LED metal substrate package having a heat dissipating structure, and a method of manufacturing same.

Abstract: One aspect of the present disclosure provides an interposer for a semiconductor package. The interposer includes a substrate portion and a wall portion disposed on the substrate portion. The substrate portion has a first side, a second side, and an electrical interconnect structure between the first side and the second side. The substrate portion is substantially free from conductive through vias, and the cost for fabricating through silicon vias (TSV) is very expensive; therefore, the fabrication cost of the interposer can be dramatically reduced. In addition, the wall portion is disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure. At least one semiconductor die can be bonded to the interposer and inside the aperture. Consequently, the height of the semiconductor package is lower than the design of disposing the semiconductor die on top of the interposer.

Abstract: A piezoelectric device includes a first substrate having a piezoelectric element on one surface thereof and a second substrate having penetration wiring that includes a through hole formed in a thickness direction thereof and a conductor section formed in the through hole. A resin section is formed on a surface of one substrate of one of the first substrate and the second substrate, which opposes the other substrate, and is formed of an elastic body in a shape protruding toward the other substrate, and a first electrode layer is formed on the surface of the other substrate side of the resin section. A second electrode layer is formed on a surface of the other substrate that opposes the one substrate, and the first substrate and the second substrate are joined in a state in which the first electrode layer and the second electrode layer are abutting against each other.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: An LED module according to the present invention includes an LED unit 2 and a case 1, where the LED unit includes an LED chip 21, and the case 1 includes a main body 11 made of a ceramic material and a pad 12a on which the LED unit 2 is mounted. The outer edge 121a of the pad 12a is positioned inward of the outer edge 2a of the LED unit 2 as viewed in plan. These arrangements prevent the light emission amount of the LED module A1 from reducing with time.

Abstract: A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.

Abstract: A multiple axis sensor assembly includes an enclosure and encapsulated microelectromechanical system (MEMS) sensors. The encapsulated sensors are disposed inside the enclosure and are mounted in different orientations, which correspond to different axes of the sensor assembly. A controller of the sensor assembly is disposed in the enclosure and electrically coupled to the MEMS sensors.

Abstract: A printed circuit board, an electronic module and a method of manufacturing the printed circuit board are provided. The printed circuit board includes a plurality of insulation layers, metal layers formed on the plurality of insulation layers, a via formed for interlayer electrical connection of the metal layers, a trench penetrating the insulation layers, and a heat-transfer structure formed in the trench.

Abstract: A semiconductor package comprise a downset has a first end coupled to a connection portion and a second opposite end electrically coupled to a lead of a lead frame; and an adhesion layer disposed between the lead and the second end of the downset to allow adhesion therebeween; wherein the downset is bent in a non-right angle at the first end thereof such that a bottom face of the second end of the downset is tilted toward a top face of the lead and thus a first side of both sides of the bottom face is closer to the top face of the lead than a second side opposite the first side, wherein a first trap region is defined between a side face of the second end at the first side and the top face of the lead to trap therein an adhesion material of the adhesion layer, wherein a second trap region is defined between the bottom face of the second end and the top face of the lead to trap therein an adhesion material of the adhesion layer.

Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.

Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor die having at least a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die. The device can include a leadframe portion electrically coupled to the first terminal of the semiconductor die and a clip portion electrically coupled to the second terminal of the semiconductor die. The device can include a molding compound. A surface of the leadframe portion and a first surface of the molding compound can define at least a portion of a first surface of the device. A surface of the clip portion and a second surface of the molding compound can define at least a portion of a second surface of the device that is parallel to the first surface of the device.

Abstract: The present invention relates to a manufacturing method of a molded article, including: a molded article forming step of forming a molded article by curing a resin composition on a main surface, on the side of a bendable first supporting medium, of a laminated supporting medium obtained by laminating the first supporting medium and a second supporting medium that is harder than the first supporting medium; a second-supporting medium peeling step of peeling the second supporting medium from the first supporting medium after the molded article forming step; and a first-supporting medium peeling step of peeling the first supporting medium from the molded article while bending the first supporting medium after the second-supporting medium peeling step. The shape of the first supporting medium can be maintained at a curing temperature at which the resin composition is cured in the molded article forming step.

Abstract: A magnetic field sensor includes a lead frame having a plurality of leads, at least two of which have a connection portion and a die attach portion. A semiconductor die is attached to the die attach portion of the at least two leads. The sensor further includes at least one wire bond coupled between the die and a first surface of the lead frame. The die is attached to a second, opposing surface of the lead frame in a lead on chip configuration. In some embodiments, at least one passive component is attached to the die attach portion of at least two leads.

Abstract: A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material.

Abstract: A semiconductor device includes a microphone module implemented on a first semiconductor die and a signal processing module implemented on a second semiconductor die. The microphone module includes a movable microphone element arranged at a main side of the first semiconductor die and the second semiconductor die is mounted to the main side of the first semiconductor die.

Abstract: As a wireless module which is capable of improving heat dissipation while suppressing degradation of antenna characteristics, there is provided a wireless module including: a first substrate having a first surface on which a plurality of antennas and a ground portion are disposed; and a heat dissipating member disposed opposite the first surface of the first substrate. The heat dissipating member includes a plurality of openings corresponding to the plurality of antennas respectively and an intervening portion which intervenes between the plurality of openings. The ground portion is disposed between the first substrate and the heat dissipating member.

Abstract: A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structural characteristics desired in the MEMS device.

Abstract: A bonding structure comprising a contact pad, an anisotropic conductive film (ACF) and a contact structure is provided. The contact pad includes at least one recess, wherein a thickness of the contact pad is T, and a width of the at least one recess is B, The ACF is disposed on the contact pad and includes a plurality of conductive particles; each of the conductive particles is disposed in the at least one recess. A diameter of the conductive particles is A, and A is larger than B and T and satisfies B?2(AT?T2)1/2. The contact structure is disposed on the ACF and electrically connected to the contact pad via the conductive particles. The disclosure also provides a flexible device including a substrate, a patterned insulating layer, at least one contact pad, ACF, and a contact structure.

Abstract: The invention concerns a method for producing a printed circuit for a chip card module. This method involves producing two layers of electrically conductive material insulated from each other by a layer of insulating material, connection holes extending through the layer of insulating material and blocked by one of the layers of electrically conductive material, an area free of conductive material being provided in the other layer of electrically conductive material around the connection holes. The invention also concerns a printed circuit for a chip card produced using this method and a chip card module including such a printed circuit.

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM.

Abstract: The invention relates to a method for the production of current sensors which comprise a plastic housing made in an IC technology. The key steps are to mount on a leadframe and wire bond semiconductor chips having Hall sensors, to place the leadframe in an injection mold, to close the injection mold with a first mold insert and to inject plastic material, wherein each semiconductor chip is packed into an intermediate casing including a flat surface having alignment structures. Then the injection mold is opened and a current conductor section is placed on the flat surface of each intermediate casing, the current conductor section having counter structures matching the alignment structures so that it is automatically aligned and held. Then the injection mold is closed with a second mold insert and plastic material injected to form the final housing of the current sensors. It is also possible to use two different injection molds.

Abstract: The present invention relates to an LED metal substrate package, and particularly, to an LED metal substrate package having a heat dissipating structure, and a method of manufacturing same.

Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent electric short-circuiting between redistribution lines. A barrier film is formed over each side surface of a copper redistribution line. The barrier film includes, for example, a manganese oxide film. The barrier film is also in contact with each end surface of a barrier metal film that is located in the position receding inward from the side surface of the copper redistribution line. A redistribution portion is formed by the copper redistribution line, the barrier film, and the barrier metal film.

Abstract: A method of structuring an active organic layer deposited on a substrate, including depositing a sacrificial layer on the substrate by photolithography, the sacrificial layer being made of at least one resist, creating at least one pattern inside of the sacrificial layer, depositing an active organic layer on the sacrificial layer and in the pattern, depositing a protective layer made of organic polymer on the active layer and in the pattern of the resist sacrificial layer, removing the sacrificial layer by projection of a solvent on the resin forming the layer, and removing the protective layer by dissolving the polymer forming it in a solvent.

Abstract: A semiconductor device includes a semiconductor element, a connection electrode formed on the semiconductor element, and alignment marks formed on the semiconductor element. At least one of the alignment marks is made of a magnetic material.

Abstract: An electrostatic chuck device including: a plurality of adsorption areas having an electrode generating electrostatic attractive force; and a control portion controlling the electrostatic attractive force against each of the plurality of the adsorption areas independently of other adsorption areas.

Abstract: An embodiment method includes analyzing warpage characteristics of a first package component and a second package component and forming a plurality of solder paste elements on the first package component. A volume of each of the plurality of solder paste elements is based on the warpage characteristics of the first package component and the second package component. The method further includes aligning a plurality of connectors disposed on the second package component to the plurality of solder paste elements on the first package component and bonding the second package component to the first package component by reflowing the plurality of connectors and the plurality of solder paste elements.

Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.

Abstract: An electronic apparatus includes: a casing; a conductive film disposed on an inner surface of the casing, the conductive film having a recess in a surface thereof; a circuit board accommodated in the casing; a semiconductor device disposed on the circuit board; and a conductive frame fixed around the semiconductor device on the circuit board, the conductive frame being fitted in the recess.

Abstract: A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.

Abstract: A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Abstract: Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package layout design based using at least the estimated number of layers and the power layer and/or the ground layer. These mechanisms use input including connectivity information, thermal effects, and/or IC placement information to determine estimates for the total number of layers, layer stack-up, power and ground plane assignment, and via libraries to guide IC package layout design.

Abstract: One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.

Abstract: A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed.

Abstract: Embedded die packages are described that employ one or more substrate redistribution layers (RDL) to route electrode nodes and/or for current redistribution. In one or more implementations, an integrated circuit die is embedded in a copper core substrate. A substrate RDL contacts a surface of the embedded die, with at least one via (e.g., thermal via) in contact with the surface RDL to furnish electrical interconnection between the embedded die and an external contact. Additional substrate RDL or WLP RDL can be incorporated into the package to provide varying current distribution between the embedded die and external contacts.

Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.

Abstract: A cavity is formed within a first substrate together with trenches that separate first and second portions of the first substrate from each other and from the remainder of the first substrate. The first portion of the first substrate is disposed within the cavity and constitutes a microelectromechanical structure, while the second portion of the substrate is disposed at least partly within the cavity and constitutes a first portion of an electrical contact. A second substrate is secured to the first substrate over the cavity to define a chamber containing the microelectromechanical structure. The second substrate has a first portion that constitutes a second portion of the electrical contact and is disposed in electrical contact with the second portion of the first substrate such that the electrical contact extends from within the chamber to an exterior of the chamber.

Abstract: Methods and structures that may be implemented in one example to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) such as sensors and actuators. For example, structures having varying characteristics may be fabricated using the same basic process flow by selecting among different process options or modules for use with the basic process flow in order to create the desired structure/s. Various process flow sequences as well as a variety of device design structures may be advantageously enabled by the various disclosed process flow sequences.

Abstract: An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.