Abstract: An electronic device is provided wherein the characteristics thereof are prevented from deteriorating. The electronic device (1) is provided with: a chip component (2) having an electronic element (22); a wiring board (3) on which the chip component (2) is mounted with a space therebetween, the space for containing the electronic element (22); a resin layer (4) provided from the surface of the chip component (2) to the surface of the wiring board (3) so as to surround the space; and an inorganic insulating layer (5), which is provided at the resin layer (4) and is positioned at the side of the space. Since entry of water vapor into the space can be reduced not only by means of the resin layer (4) but also by means of the inorganic insulating layer (5), the electronic device (1) having high airtight sealing performance can be provided.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

Abstract: A multi-chip package has a substrate with electrical contacts for connection to an external device. A CPU die is disposed on the substrate and is in communication with the substrate. The CPU die has a plurality of processor cores occupying a first area of the CPU die, and an SRAM cache occupying a second area of the CPU die. A DRAM cache is disposed on the CPU die and is in communication with the CPU die. The DRAM cache has a plurality of stacked DRAM die. The plurality of stacked DRAM dies are substantially aligned with the second area of the CPU die, and substantially do not overlap the first area of the CPU die. A multi-chip package having a DRAM cache disposed on the substrate and a CPU die disposed on the DRAM cache is also disclosed.

Abstract: A DSC type device manufacturing process includes placing a circuit assembly in a mold. The circuit assembly includes a first heat sink, a semiconductor chip mounted on the first heat sink, a second heat sink mounted on the semiconductor chip and a pin block electrically connected to the semiconductor chip. An outer surface of the first heat sink and an outer surface of the pin block are placed in contact with a first inner surface of the mold. A spacer insert is placed in contact with, and positioned between, a second inner surface of the mold and an outer surface of the second heat sink. The mold is filled with an insulating material that is subsequently hardened. After hardening, a resulting device is extracted from the mold with the outer surfaces of the first heat sink, the pin block and the second heat sink exposed.

Abstract: A semiconductor device, having an insulating substrate; a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer which is provided on the first insulating material layer (A) and a portion of which is exposed to an external surface; a first insulating material layer (B) which is provided on the first metal thin film wire layer; a second insulating material layer which is provided on a main surface of the insulating substrate where the semiconductor element is not mounted; and a second metal thin film wire layer which is provided inside the second insulating material layer.

Abstract: Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

Abstract: An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal layers may disrupt the functionality of the IC device if the vacancies migrate to the vias interconnecting the metal layers. To mitigate vacancy migration, stressor elements are formed at the metal traces to form stress effects in the metal traces that, depending on type, either serve to repel migrating vacancies from the via contact area or to trap migrating vacancies at a portion of the metal trace displaced from the contact area. The stressor elements may be formed as stress-inducing dielectric or conductive material overlying the metal traces, or formed by inducing a stress memory effect in a portion of the metal trace itself.

Abstract: A method for bonding a first semiconductor body having a plurality of electromagnetic radiation detectors to a second semiconductor body having read out integrated circuits for the detectors. The method includes: aligning electrical contacts for the plurality of electromagnetic radiation detectors with electrical contacts of the read out integrated circuits; tacking the aligned electrical contacts for the plurality of electromagnetic radiation detectors with electrical contacts of the read out integrated circuits to form an intermediate stage structure; packaging the intermediate stage structure into a vacuum sealed electrostatic shielding container having flexible walls; inserting the package with the intermediate stage structure therein into an isostatic pressure chamber; and applying the isostatic pressure to the intermediate stage structure through walls of the container. The container includes a stand-off to space walls of the container from edges of the first semiconductor body.

Abstract: A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.

Abstract: The present disclosure relates to a multi-chip stacked package and a method for forming the same. The package comprises a chip carrier and multiple levels of chips, with one or more chips being arranged in each level, wherein one or more levels of chips, except for the topmost chips, have conductive vias, a patterned conductor layer is arranged on a back surface of a lower one of two chips in two adjacent levels, conductive bumps are provided between two adjacent levels of chips, and the conductive vias of a lower chip are electrically coupled to an upper chip by means of the patterned conductor layer and the conductive bumps. In the present disclosure, electrical connections are redistributed by means of the patterned conductor layer, and are further used for coupling multiple levels of chips by means of the conductive bumps. The resultant chip has a reduced chip size and can be used for electrically coupling various levels of chips, which achieves flexible electrical connections.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The MEMS wafer comprises a thermal insulator air gap formed between a sensing layer and a membrane. An ambient pressure chamber is formed between the CMOS wafer and the membrane of the MEMS wafer. The ambient pressure chamber is configured as a second thermal insulator air gap. The thermal insulator air gap and the second thermal insulator air gap protect portions of the semiconductor arrangement, such as the MEMS wafer, from heat originating from the CMOS wafer, which can otherwise damage such portions of the semiconductor arrangement. In some embodiments, one or more buffer layers are formed over the cap wafer as stress buffers.

Abstract: A power semiconductor module includes: a plurality of first metal plates arranged in the same planar state; a power semiconductor chip mounted on the first metal plate; and an overbridge-shaped second metal plate which is composed of bridge frame sections and leg sections that support the bridge frame sections, the leg sections being for appropriately performing solder bonding between electrodes of the power semiconductor chips and between the electrode of the power semiconductor chip and the first metal plate, the power semiconductor module being configured by a resin package in which these members are sealed with electrically insulating resin. In the power semiconductor module, the solder bonding section of the leg section is formed in a planar shape by bending process and is provided at a position lower than the bridge frame section.

Abstract: A leadframe system and method of manufacture includes: providing a leadframe having a side rail and a stabilizer, the side rail along a leadframe perimeter and the stabilizer within a rail inner perimeter of the side rail; forming a stabilizer plating layer directly on a bottom side of the stabilizer; and forming an encapsulation surrounded by a mold step, the mold step directly over the stabilizer and the stabilizer plating layer for forming a stiffening structure positioned within the rail inner perimeter of the side rail.

Abstract: The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Abstract: A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.

Abstract: A circuit module includes a circuit substrate, a mount component, a sealing body, and a shield. The circuit substrate includes a mount surface. The mount component is mounted on the mount surface. The sealing body is formed on the mount surface, covers the mount component and has a trench formed from a main surface of the sealing body to the mount surface. The trench includes side walls configured of a first side wall at a mount surface side and a second side wall at a main surface side. A straight line connecting the first point and the second point has a second slope gentler than the first slope against the mount surface. The shield covers the sealing body and has an inner shield section formed within the trench and an outer shield section disposed on the main surface and the inner shield.

Abstract: An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.

Abstract: Various embodiments provide a power transistor arrangement. The power transistor arrangement may include a carrier; a first power transistor having a control electrode and a first power electrode and a second power electrode; and a second power transistor having a control electrode and a first power electrode and a second power electrode. The first power transistor and the second power transistor may be arranged next to each other on the carrier such that the control electrode of the first power transistor and the control electrode of the second power transistor are facing the carrier.

Abstract: An assembly of a MEMS integrated device envisages: a package having a base substrate with a main surface in a horizontal plane, and a coating set on the base substrate; a first body including semiconductor material and integrating a micromechanical structure, housed within the package on the base substrate; at least one second body including semiconductor material and integrating at least one electronic component, designed to be functionally coupled to the micromechanical structure, the first body and the second body being arranged within the package stacked in a vertical direction transverse to the horizontal plane. In particular, at least one between the first body and the base substrate defines a first recess, in which the second body is housed, at least in part.

Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface which faces away from the first surface, and through holes which pass through the first surface and the second surface; a dielectric layer formed on one or more of the first surface and the second surface and formed with grooves around the through holes on a fourth surface of the dielectric layer facing away from a third surface of the dielectric layer which is attached to the semiconductor chip; through-silicon vias filling the through holes; and bumps formed on the through-silicon vias and on portions of the dielectric layer around the through-silicon vias and filling the grooves.

Abstract: A Through Mold Via (TMV) Integrated Circuit (IC) package is provided as a bottom IC package for a TMV Package on Package (POP) configuration. The TMV IC package has an overmold top portion having a substantially flat surface and spacer or standoff features extending upward from the flat surface. The spacer or standoff features are configured to abut the bottom surface of the top POP package during softer reflow in order to maintain a gap of predetermined height between the top and bottom IC packages.

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Abstract: Disclosed are methods for forming semiconductor devices and the semiconductor devices thus obtained. In one embodiment, the method may include providing a semiconductor wafer comprising a surface, forming on the surface at least one device, forming a release layer at least in an area of the surface that encircles the at least one device, forming on the release layer at least one wall structure around the at least one device, and forming at least one cap on the at least one wall structure. In one embodiment, the device may include a substrate comprising a surface, at least one device formed on the surface, a release layer formed at least in an area of the surface that encircles the at least one device, at least one wall structure formed around the at least one device, and at least one removable cap formed on the at least one wall structure.

Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, a p-side electrode, a plurality of n-side electrodes, a first insulating film, a p-side interconnect unit, and an n-side interconnect unit. The p-side interconnect unit is provided on the first insulating film to connect to the p-side electrode through a first via piercing the first insulating film. The n-side interconnect unit is provided on the first insulating film to commonly connect to the plurality of n-side electrodes through a second via piercing the first insulating film. The plurality of n-side regions is separated from each other without being linked at the second surface. The p-side region is provided around each of the n-side regions at the second surface.

Abstract: A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

Abstract: An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.

Abstract: A BioMEMS microelectromechanical apparatus and for fabricating the same is disclosed. A substrate is provided with at least one signal conduit formed on the substrate. A sacrificial layer of sacrificial material may be deposited on the signal conduit and optionally patterned to remove sacrificial material from outside the packaging covered area. A bonding layer may be deposited on at least a portion of the signal conduit and on the sacrificial layer when included. The bonding layer may be planarized and patterned to form one or more cap bonding pads and define a packaging covered area. A cap may be bonded on the cap bonding pad to define a capped area and so that the signal conduit extends from outside the capped area to inside the capped area. Additionally, a test material such as a fluid may be provided within the capped area.

Abstract: The invention relates to a sealed thin-film device (10, 12, 14), to a method of repairing a sealing layer (20) applied to a thin-film device (30) to produce the sealed thin-film device, to a system (200) for repairing the sealing layer applied to the thin-film device to generate the sealed thin-film device and to a computer program product. The sealed thin-film device comprises a thin-film device and a sealing layer applied on the thin-film device for protecting the thin-film device from environmental influence. The sealed thin-film device further comprises locally applied mending material (40; 42, 44) for sealing a local breach (50) in the sealing layer. An effect of this sealed thin-film device is that the operational life-time of the sealed thin-film device is improved. Furthermore, the production yield of the production of sealed thin-film devices is improved.

Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.

Abstract: A transistor may include a channel layer formed of an oxide semiconductor. The oxide semiconductor may include GaZnON, and a proportion of Ga content to a total content of Ga and Zn of the channel layer is about 0.5 to about 4.5 at %.

Abstract: Provided are a thin circuit device with show-through of thin metal wires prevented and a method of manufacturing the circuit device. A circuit device mainly includes: a substrate including a first substrate and second substrates; pads formed respectively on upper surfaces of the second substrates; a semiconductor element fixed on an upper surface of the first substrate; thin metal wires each connecting the semiconductor elements and a corresponding one of the pads; and a sealing resin with which the semiconductor element and the thin metal wires are covered, and which thereby seals the circuit device with the semiconductor element and the thin metal wires disposed therein. Furthermore, filler particles located in the uppermost portion of the sealing resin are covered with a resin material constituting the sealing resin.

Abstract: A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.

Abstract: Apparatus and methods for heating of one or more substrates with a plurality of independently controllable heating zones. Pressurized air is provided to each of a plurality of independently controlled heater blocks each including a heating element. The pressurized air is heated in the heater blocks and discharged towards one or more regions of the one or more substrates. The amount of power provided to the heating element in one of the heating blocks may be adjusted relative to the amount of power provided to the heating element in another of the heating blocks. The temperature of one heating zone may thereby be adjusted relative to other heating zones so that the temperature of different heating zones for the one or more substrates may be independently controlled. Heated air may be recovered from the heating zones and recycled. The pressurized air may be preheated by passing through a lift plate.

Abstract: A method for implementing a prompt dose mitigating capacitor is disclosed. Initially, a flip chip is provided with multiple capacitors. The flip chip is then placed on top of a substrate having multiple electronic devices connected to a set of power rails. The terminals of the capacitors within the flip chip are subsequently connected to the power rails within the substrate in order to regulate voltages appeared on the power rails during a radiation pulse.

Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.

Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.

Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.

Abstract: A method of making a package substrate having a copper bond pad and a location for receiving a semiconductor die having a remnant of one of a group consisting of HEDP and an HEDP derivative on a top surface of the copper bond pad. The semiconductor die is attached to the substrate. A wirebond connection is attached between the remnant and the semiconductor die.

Abstract: A circuit module includes a circuit substrate, at least one mount component, sealing bodies, and a shield. The circuit substrate includes a mount surface. The mount component is mounted on the mount surface. The sealing body is formed on the mount surface, covers the mount component and has a first sealing body section having a first thickness and a second sealing body section having a second thickness larger than the first thickness. The shield covers the sealing body and has a first shield section formed on the first sealing body section and having a third thickness and a second shield section formed on the second sealing body section and having a fourth thickness smaller than the third thickness. The sum of the fourth thickness and the second thickness equals to the sum of the first thickness and the third thickness.

Abstract: A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.