Abstract: Semiconductor devices are provided including a gate across an active region of a substrate; a source region and a drain region in the active region on either side of the gate and spaced apart from each other; a main channel impurity region in the active region between the source and drain regions and having a first channel impurity concentration; and a lightly doped channel impurity region in the active region adjacent to the drain region. The lightly doped channel impurity region has the same conductivity type as the main channel impurity region and a second channel impurity concentration, lower than the first channel impurity concentration. The lightly doped channel impurity region and the main channel impurity region contain a first element. The lightly doped channel impurity region also contains a second element, which is a different Group element from the first element.

Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.

Abstract: Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant may include arsenic (As). In an embodiment, a dopant solution is provided that includes a solvent and a dopant. In a particular embodiment, the dopant solution may have a flashpoint that is at least approximately equal to a minimum temperature capable of causing atoms at a surface of the substrate to attach to an arsenic-containing compound of the dopant solution. In one embodiment, a number of silicon atoms at a surface of the substrate are covalently bonded to the arsenic-containing compound.

Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a glass powder and a dispersion medium, in which the glass powder includes an donor element and a total amount of the life time killer element in the glass powder is 1000 ppm or less. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.

Abstract: A composition for doping semiconductor materials, such as silicon, may contain a) a solvent and a) an inorganic salt of a phosphor containing acid dispersed in the solvent. Also disclosed are doping methods using such composition as well as methods of making the doping composition.

Abstract: A hydrophobic organic layer may be formed on a surface of a graphene doped with a dopant to improve stability of the doped graphene with respect to moisture and temperature. Thus, the transparent electrode having the doped graphene containing the hydrophobic organic layer may be usefully applied in solar cells or display devices.

Abstract: Metal contact formation for molecular device junctions by surface-diffusion-mediated deposition (SDMD) is described. In an example, a method of fabricating a molecular device junction by surface-diffusion-mediated deposition (SDMD) includes forming a molecular layer above a first region of a substrate. A region of metal atoms is formed above a second region of the substrate proximate to, but separate from, the first region of the substrate. A metal contact is then formed by migrating metal atoms from the region of metal atoms onto the molecular layer.

Abstract: A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.

Abstract: A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n? type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n? type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n? type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n? type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n? type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.

Abstract: Methods for selectively diffusing dopants into a substrate wafer are provided. A liquid precursor is doped with dopants. The liquid precursor is selected from a group comprising monomers, polymers, and oligomers of silicon and hydrogen. The doped liquid precursor is deposited on a surface of the substrate wafer to create a doped film. The doped film is heated on the substrate wafer for diffusing the dopants from the doped film into the substrate wafer at different diffusion rates to create a heavily diffused region and a lightly diffused region in the substrate wafer. The method disclosed herein further comprises selective curing of the doped film on the surface of the substrate wafer. The selectively cured doped film acts as a diffusion source for selectively diffusing the dopants into the substrate wafer.

Abstract: Methods of fabricating solar cells are described. A porous layer may be formed on a surface of a substrate, the porous layer including a plurality of particles and a plurality of voids. A solution may be dispensed into one or more regions of the porous layer to provide a patterned composite layer. The substrate may then be heated.

Abstract: A method of diffusing an impurity-diffusing component including forming a first diffusing agent layer containing a first conductivity type impurity-diffusing component on the surface of a semiconductor substrate; calcining the first diffusing agent layer; forming a second diffusing agent layer containing a second conductivity type impurity-diffusing component on the surface of the semiconductor substrate excluding the region where the first diffusing agent layer is formed; and heating the semiconductor substrate at a temperature higher than the calcination temperature to diffuse the first and second conductivity type impurity-diffusing components to the semiconductor substrate.

Abstract: A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film.

Abstract: In one embodiment, a method includes forming a base region for a transistor using a base mask and forming a contact region to the base region. The contact region is formed in an area that is at least partially outside of the base mask. The method then forms an emitter region in a diffused base region. The base region diffuses outwardly to be formed under the contact region.

Abstract: According to one embodiment, in a method of manufacturing a semiconductor device, a gate electrode material film is anisotropically etched using a mask having a predetermined pattern so as to form a first gate electrode on a first region, first dummy gates on the space area of the first region, a second gate electrode on a second region and second dummy gates on the space area of the second region. The first dummy gates have a first coverage and are disposed so as to surround the first gate electrode. The second dummy gates have a second coverage and are disposed so as to surround the second gate electrode. A first insulating film is anisotropically etched so as to form a first sidewall having a first thickness on the first gate electrode and a second sidewall having a second thickness larger than the first thickness on the second gate electrode.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet- vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.

Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract: Herein, provided are heavily doped colloidal semiconductor nanocrystals and a process for introducing an impurity to semiconductor nanoparticles, providing control of band gap, Fermi energy and presence of charge carriers. The method is demonstrated using InAs colloidal nanocrystals, which are initially undoped, and are metal-doped (Cu, Ag, Au) by adding a metal salt solution.

Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared. At a portion of the semiconductor substrate where a first electrode is to be formed, a metal thin film made of electrode material including an impurity is formed. After the metal thin film is formed, the first electrode including a metal reaction layer in which the impurity is introduced is formed by irradiating the metal thin film with a laser light.

Abstract: Provided is a method of fabricating a gallium nitride semiconductor which enables activation of a p-type dopant with a heat treatment performed for a relatively short period of time. The fabricating method comprises the step of performing, in a vacuum, a heat treatment of a group III nitride semiconductor region, the group III nitride semiconductor region comprising a gallium nitride semiconductor, the gallium nitride semiconductor including a p-type dopant, the a group III nitride semiconductor region having a group III nitride semiconductor surface inclined with respect to a reference plane perpendicular to a reference axis, and the reference axis extending in a direction of a c-axis of the gallium nitride semiconductor.

Abstract: A method is provided for fabricating a structured semiconductor substrate including: i) depositing, on the surface of a semiconductor material, a sacrificial layer of material different from the semiconductor material. At step ii), the sacrificial layer, formed in step i) is etched at least in part so as to form sacrificial layer islets on the surface of the semiconductor material. The semiconductor material of step ii) is etched at least in part, in zones that are not protected by said islets, so as to form a structured semiconductor material, this step iii) being performed in the presence of oxygen so as to deposit an oxide layer on the surface of the semiconductor material. The sacrificial layer islets and the oxide layer are eliminated from the surface of the semiconductor material obtained in step iii), so as to form the structured substrate.

Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench.

Abstract: Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred.

Abstract: An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 ?m and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 ?m.

Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method of manufacturing a semiconductor device, a first layer containing Si is formed on a semiconductor substrate. An impurity region and a non-impurity region are formed in the first layer by selectively diffusing an impurity into the first layer. A second layer containing a metal material is formed on the first layer. The metal material is diffused into the non-impurity region by annealing the second layer.

Abstract: A semiconductor laser element includes a first electrode, a second electrode, a first reflecting mirror, a second reflecting mirror, and a resonator. The resonator includes an active layer, a current confinement layer, a first semiconductor layer having a first doping concentration formed at a side opposite to the active layer across the current confinement layer, and a second semiconductor layer having a second doping concentration higher than the first doping concentration formed between the first semiconductor layer and the current confinement layer. The first electrode is provided to contact a part of a surface of the first semiconductor layer. The first semiconductor layer has a diffusion portion into which a component of the first electrode diffuses. The second semiconductor layer contacts the diffusion portion. The second semiconductor layer is positioned at a node of a standing wave at a time of laser oscillation of the semiconductor laser element.

Abstract: Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a discontinuous mask.

Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.

Abstract: An embodiment of the present invention relates to a diffusing agent composition used in printing an impurity-diffusing component onto a semiconductor substrate, wherein the diffusing agent composition contains: a hydrolysis product of alkoxysilane (A); a component (B) containing at least one selected from the group consisting of a hydrolysis product of alkoxy titanium, a hydrolysis product of alkoxy zirconium, titania fine particle, and zirconia fine particle; an impurity-diffusing component (C); and an organic solvent (D).

Abstract: A low voltage protection device that includes a silicon substrate comprises an inner layer of a first dopant type. The device also includes a first outer layer of a second dopant type disposed adjacent a first surface of the inner layer and a second outer layer of the second dopant type disposed adjacent a second surface of the inner layer opposite the first surface. The device further includes a first mesa region disposed in a peripheral region of a first side of the low voltage protection device. The first mesa region includes a first area that includes a peripheral portion of a cathode of the low voltage protection device, the cathode formed by diffusing a high concentration of dopant species of the first type on a first surface of the silicon substrate, and a second area comprising a high concentration of diffused dopant species of the second type.

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated includes an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.

Abstract: A method for fabricating a semiconductor device, including etching a substrate to form a trench, forming a junction region in the substrate under the trench, etching the bottom of the trench to a certain depth to form a side junction, and forming a bit line coupled to the side junction.

Abstract: A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.

Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region.

Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.

Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface. The method further includes depositing an ink on the front substrate surface in a ink pattern, the ink comprising a set of silicon-containing particles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified film ink pattern.

Abstract: Photovoltaic modules comprise solar cells having doped domains of opposite polarities along the rear side of the cells. The doped domains can be located within openings through a dielectric passivation layer. In some embodiments, the solar cells are formed from thin silicon foils. Doped domains can be formed by printing inks along the rear surface of the semiconducting sheets. The dopant inks can comprise nanoparticles having the desired dopant.

Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a glass powder and a dispersion medium, in which the glass powder includes an donor element and a total amount of the life time killer element in the glass powder is 1000 ppm or less. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.