Abstract: A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate.

Abstract: An electrode formed using a transparent conductive oxide is likely to be crystallized by heat treatment performed in the manufacturing process of a semiconductor device. In the case of a thin film element using an electrode having a significantly uneven surface due to crystallization, a short circuit is likely to occur and thus reliability of the element is degraded. An object is to provide a light-transmitting conductive oxynitride which is not crystallized even if subjected to heat treatment and a manufacturing method thereof. It is found that an oxynitride containing indium, gallium, and zinc, to which hydrogen atoms are added as impurities, is a light-transmitting conductive film which is not crystallized even if heated at 350° C. and the object is achieved.

Abstract: A method for manufacturing a MOSFET includes the steps of: introducing an impurity into a silicon carbide layer; forming a carbon layer in a surface layer portion of the silicon carbide layer having the impurity introduced therein, by selectively removing silicon from the surface layer portion; and activating the impurity by heating the silicon carbide layer having the carbon layer formed therein.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film.

Abstract: An integrated semiconductor device and method of manufacturing the same includes leaving one part of a semiconductor layer so that an inclined surface is formed on a trench when forming the trench on a SOI wafer. A thick silicon oxide film (second insulation film) is formed along this incline surface. This thick silicon oxide film prevents oxygen entering a boundary surface between an insulation layer and the semiconductor layer of the SOI wafer within the trench.

Abstract: A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.

Abstract: A method of forming a metal contact on a silicon substrate is disclosed. The method includes depositing a nanoparticle ink on a substrate surface in a pattern, the nanoparticle ink comprising set of nanoparticles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified nanoparticle layer with a nanoparticle layer thickness of greater than about 50 nm. The method further includes depositing an SiNx layer on the substrate surface, SiNx layer having a SiNx layer thickness of between about 50 nm and about 110 nm; exposing the substrate to an etchant that is selective to the densified nanoparticle layer for a second time period and at a second temperature in order to create a via; and forming a metal contact in the via, wherein an ohmic contact is formed with the silicon substrate.

Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.

Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.

Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ? ? kV ? ? cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.

Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material.

Abstract: A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.

Abstract: A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate.

Abstract: Photovoltaic modules comprise solar cells having doped domains of opposite polarities along the rear side of the cells. The doped domains can be located within openings through a dielectric passivation layer. In some embodiments, the solar cells are formed from thin silicon foils. Doped domains can be formed by printing inks along the rear surface of the semiconducting sheets. The dopant inks can comprise nanoparticles having the desired dopant.

Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.

Abstract: At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.

Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The bands or chains are driven synchronously at ultra-low tension by a pin drive roller or sprocket at either the inlet or outlet end of the furnace, with appropriate tensioning systems disposed in the return path. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces.

Abstract: An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced into the semiconductor body.

Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device.

Abstract: A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the second n-type doping region is formed with a dopant concentration greater than that in the first n-type doping region. A plurality of isolation structures is disposed in the second n-type doping region of the n drift region, defining an anode region and a cathode region. A third n-type doping region is disposed in the second n-type doping region exposed by the cathode region. An anode electrode is disposed over the first n-type doping region in the anode region. A cathode electrode is disposed over the third n-type doping region in the cathode region.

Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.

Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.

Abstract: A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.

Abstract: Method of producing a partly or completely semi-insulating or p-type doped ZnO substrate from an n-type doped ZnO substrate, in which the n-type doped ZnO substrate is brought into contact with an anhydrous molten salt chosen from anhydrous molten sodium nitrate, lithium nitrate, potassium nitrate and rubidium nitrate. Partly or completely semi-insulating or p-type doped ZnO substrate, said substrate being in particular in the form of a thin layer, film or in the form of nanowires; and said substrate being doped at the same time by an element chosen from Na, Li, K and Rb; by N; and by O; it being furthermore possible for ZnO or GaN to be epitaxially grown on this substrate. Electronic, optoelectronic or electro-optic device such as a light-emitting diode (LED) comprising this substrate.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes.

Abstract: The invention relates to methods of making unsupported articles of semiconducting material using thermally active molds having an external surface temperature, Tsurface, and a core temperature, Tcore, whererin Tsurface>Tcore.

Abstract: A method of structuring multicrystalline silicon surfaces comprises the provision of a texturing solution, the application of the texturing solution to a surface of a semiconductor substrate to be structured and the heating of the texturing solution to a texturing temperature, wherein the texturing solution comprises at least a portion of phosphoric acid.

Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

Abstract: A diffusing agent composition contains a condensation product (A) and an impurity diffusion component (B). The condensation product (A) is a reaction product yielded by hydrolyzing an alkoxysilane. The impurity diffusion component (B) is a monoester or diester of phosphoric acid, or a mixture thereof.

Abstract: A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region.

Abstract: A method for forming a power device includes the following steps. An epitaxial layer is formed on a substrate. A pad layer and hard mask are formed on the epitaxial layer. A trench is etched into the hard mask, the pad layer, and the epitaxial layer. The hard mask is removed. A buffer layer is formed on the sidewall of the trench. The trench is then filled with a dopant source layer comprising plural dopants. A drive-in process is performed to diffuse the dopants into the epitaxial layer through the buffer layer, thereby forming a diffusion region around the trench.

Abstract: The invention relates to a process for producing a p-n junction in a nanostructure, in which the nanostructure has one or more nanoconstituents made of a semiconductor material with a single type of doping having one conductivity type, characterized in that it includes a step consisting in forming a dielectric element (3, 32, . . . , 3n) embedding the nanostructure over a height h, the dielectric element generating a surface potential capable of inverting the conductivity type over a defined width W of the nanoconstituents(s) thus embedded over the height h.

Abstract: A laser medium comprises a solid-state host material and dopant species provided within the solid-state host material. A first portion of the dopant species has a first valence state, and a second portion of the dopant species has a second valence state. In an embodiment, a concentration of the first portion of the dopant species decreases radially with increasing distance from a center of the medium, and a concentration of the second portion of the dopant species increases radially with increasing distance from the center of the medium. The laser medium further comprises impurities within the solid-state host material, the impurities converting the first portion of the dopant species having the first valence state into the second portion of dopant species having the second valence state.

Abstract: A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns.

Abstract: A manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the method manufacturing costs can be reduced. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch<Lg<Lwell is satisfied; and the channel regions are further formed by diffusing by activation annealing boron as a third impurity, having been implanted by activation annealing into the source regions, into a silicon carbide layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.

Abstract: A method of forming a metal contact on a silicon substrate is disclosed. The method includes depositing a nanoparticle ink on a substrate surface in a pattern, the nanoparticle ink comprising set of nanoparticles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified nanoparticle layer with a nanoparticle layer thickness of greater than about 50 nm. The method further includes depositing an SiNx layer on the substrate surface, SiNx layer having a SiNx layer thickness of between about 50 nm and about 110 nm; exposing the substrate to an etchant that is selective to the densified nanoparticle layer for a second time period and at a second temperature in order to create a via; and forming a metal contact in the via, wherein an ohmic contact is formed with the silicon substrate.

Abstract: The invention relates to a device and a method for simultaneous microstructuring and doping of semiconductor substrates with boron, in which the semiconductor substrate is treated with a laser beam coupled into a liquid jet, the liquid jet comprising at least one boron compound. The method according to the invention is used in the field of solar cell technology and also in other fields of semiconductor technology in which a locally delimited boron doping is important.

Abstract: A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer.

Abstract: Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.

Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.

Abstract: Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.

Abstract: Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred.

Abstract: A method for the manufacture of carbon based electrical components is herein presented. In the method a wafer substrate is provided upon which a first layer of carbon based semiconductor is deposited. The first layer of carbon based semiconductor is introduced to a first doping agent precursor and the first doping agent precursor and first layer of carbon based semiconductor are irradiated with light having a wavelength in the ultraviolet spectrum thereby selectively doping areas of the first layer of carbon based semiconductor.

Abstract: Systems and methods for lithography include actuating an electroactive polymer member to position mask and/or substrate.

Abstract: Disclosed are a semiconductor device producing method and a semiconductor device. The semiconductor device producing method is comprised of a step of forming a diffusion suppressing mask composed of at least two of a thick film portion, an opening portion, and a thin film portion, on a surface of a semiconductor substrate; a step of applying dopant diffusing agents containing dopants to the entirety of a surface of the diffusion suppression mask; and a step of diffusing the dopants obtained from the dopant diffusing agents onto the surface of the semiconductor substrate. In the semiconductor device, a high concentration first conductive dopant diffusion layer, a high concentration second conductive dopant diffusion layer, a low concentration first conductive dopant diffusion layer, and a low concentration second conducive dopant diffusion layer are provided on one of the surfaces of the semiconductor substrate.

Abstract: An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.

Abstract: A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.