Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

Abstract: Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired.

Abstract: A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are aligned to a straight line. A dummy metal line interconnects the two dummy metal patterns. A width of the dummy metal line is smaller than lengths and widths of the two dummy metal patterns, wherein the width is measure in a direction perpendicular to the straight line. Bottoms of the two dummy metal patterns and the dummy metal line are substantially level with a bottom surface of the metal line.

Abstract: A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration.

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract: Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and a metallic material which reacts with oxygen more easily than hydrogen does, the metallic oxide having been diffused into a region which includes a joint interface between the first wiring and the second wiring and the inside of at least one of the first wiring and the second wiring.

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration there-between are reduced.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.

Abstract: An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

Abstract: A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions.

Abstract: A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer.

Abstract: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

Abstract: A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines.

Abstract: The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: The semiconductor device 1 includes a substrate 3, a semiconductor chip 4 mounted on the substrate 3, the substrate 3, a bump 5 connecting the substrate 3 and the semiconductor chip 4, and an underfill 6 filling in around the bump 5. In the case of a bump 5 composed of a high-melting-point solder having a melting point of 230° C. or more, the underfill 6 is composed of a resin material having an elastic modulus in the range of 30 MPa to 3000 MPa. In the case of a bump 5 composed of a lead-free solder, the underfill 6 is composed of a resin material having an elastic modulus in the range of 150 MPa to 800 MPa. An insulating layer 311 of buildup layers 31 of the substrate 3 has a linear expansion coefficient of 35 ppm/° C. or less in the in-plane direction of the substrate at temperatures in the range of 25° C. to the glass transition temperature.

Abstract: A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed.

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract: A semiconductor module, comprises a package molding compound layer comprising an integrated circuit (IC) device embedded within a package molding compound, the integrated circuit device and the package molding compound having a common surface. Structures are formed to connect the semiconductor module to an external board, the structures electrically connected to the integrated circuit device. A layer is formed on the common surface, the layer comprising at least one integrated antenna structure, the integrated antenna structure being coupled to the IC device.

Abstract: An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure.

Abstract: A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

Abstract: Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.

Abstract: A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: According to one embodiment, a method can include dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.

Abstract: A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, and laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides.

Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

Abstract: Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic components of the microelectronic packages may have sintered conductive vias comprising sintered metal and magnetic particles.

Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, while avoiding electrically insulating additional protection and sealing layers that are usually to be provided.

Abstract: Provided are a semiconductor device and a method for manufacturing the same. Since an additional space for forming a shield line is unnecessary, the critical dimension of metal lines is reduced, thereby improving data transfer characteristics, signaling characteristics and noise characteristics of the metal lines. The semiconductor device includes: a plurality of metal lines disposed on the semiconductor device; a plurality of insulation layers disposed on the metal lines; and a plurality of shield lines disposed between the insulation layers.

Abstract: A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Abstract: In one embodiment, there is provided a semiconductor device that includes: a substrate; a dielectric layer on the substrate; a first ground metal layer embedded in the dielectric layer and having a first DC potential, the first ground metal layer having a first hole therethrough; a first ground patch disposed in the first hole; a second ground metal layer embedded in the dielectric layer such that the dielectric layer is interposed between the first and second ground metal layers in a thickness direction of the dielectric layer, the second ground metal layer having a second DC potential and having a second hole therethrough; a second ground patch disposed in the second hole; a first via which electrically connects the first ground metal layer and the second ground patch; and a second via which electrically connects the second ground metal layer and the first ground patch.

Abstract: A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.

Abstract: In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.

Abstract: A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.

Abstract: A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.

Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.