Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Publication number: 20110287631
    Abstract: A plasma processing apparatus and a method of manufacturing a semiconductor device which can prevent a discharge from occurring between a substrate such as a semiconductor wafer or the like, and a base material of a lower electrode or a peripheral structure of the base material, and can improve yield and productivity. The plasma processing apparatus includes a processing chamber, a lower electrode, an upper electrode, and a plurality of lifter pins for supporting a substrate to be processed. Each of the lifter pins includes a pin body part and a lid part which is disposed on a top portion of the pin body part and has an outer diameter greater than an outer diameter of the pin body part.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 24, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Takashi YAMAMOTO
  • Publication number: 20110287630
    Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William R. Brown, David Kewley, Adam Olson
  • Publication number: 20110279979
    Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Inventors: Nik Mirin, Tsai-Yu Huang, Vishwanath Bhat, Chris Carlson, Vassil Antonov
  • Publication number: 20110281439
    Abstract: A method for coating a silicon wafer comprises depositing a coating onto the exposed side of the wafer such that the coating is deposited on the entire surface area of the exposed side of the wafer, reaching to the edge of the wafer. This method either reduces significantly or eliminates die-fly during dicing of semiconductor wafers, and is effective for depositing thin layers, such as are needed for Al paste electrodes in solar cell fabrication.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 17, 2011
    Inventors: Stephen Aldo Ruatta, Paul James Gleeson, Anthony Winster, Fidelin N. Willybiro
  • Patent number: 8058183
    Abstract: A method for restoring the dielectric constant of a low dielectric constant film is described. A porous dielectric layer having a plurality of pores is formed on a substrate. The plurality of pores is then filled with an additive to provide a plugged porous dielectric layer. Finally, the additive is removed from the plurality of pores.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 15, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, May Yu, Alexandros T. Demos, Mehul Naik
  • Patent number: 8053273
    Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: November 8, 2011
    Assignee: Advanced Micro Devices Inc.
    Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay
  • Patent number: 8053328
    Abstract: A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa formed by etching through a silicon-on-insulator (SOI) film and an underlying buried oxide of an SOI substrate. The process is well suited for the growth of semiconductor nanowires that nucleates from fine particle used as a catalyst.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Guy Moshe Cohen
  • Publication number: 20110269315
    Abstract: A thin film formation method to form a silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes alternately and repeatedly performing a first gas supply process in which a silane-based gas composed of silicon and hydrogen is supplied into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object to be processed and a second gas supply process in which an impurity-containing gas is supplied into the process chamber, to form an amorphous silicon film containing an impurity. Accordingly, an amorphous silicon film containing an impurity having good filling characteristics can be formed even at a relatively low temperature.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 3, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide Hasebe, Akinobu Kakimoto
  • Patent number: 8048713
    Abstract: The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts, then providing, on said sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer with second contacts (36), and finally an etching step.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: November 1, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Véronique Sousa, Cyril Dressler
  • Publication number: 20110263132
    Abstract: In a forming method of an adhesive layer including the steps of selectively coating, on a surface to be bonded, an adhesive composition containing a thermosetting composition and an organic solvent using a noncontact coating device; and removing the organic solvent from the adhesive composition coated on the surface to be bonded and in a forming method of an adhesive layer characterized in the thermosetting composition has a hardening property so as to exhibit two kinds of reaction temperatures, the adhesive composition comprising an epoxy resin and an epoxy curing agent which are reacted through a first hardening reaction exhibiting a first DSC peak within a temperature range of 100 to 160° C. and a second hardening reaction relating to a self-polymerization of the epoxy resin and exhibiting a second DSC peak within a temperature range of 140 to 200° C.
    Type: Application
    Filed: March 15, 2011
    Publication date: October 27, 2011
    Applicants: KABUSHIKI KAISHA TOSHIBA, KYOCERA CHEMICAL CORPORATION
    Inventors: Kazuyoshi Sakurai, Yuichi Noguchi, Norio Kurokawa, Yasuo Tane
  • Publication number: 20110263134
    Abstract: In some embodiments, a reducing gas ambient containing a reducing agent is established in a batch process chamber before substrates are subjected to a deposition. The reducing atmosphere is established before and/or during loading of the substrates into the process chamber, and can include flowing reducing gas into the process chamber while the chamber is open. The reducing gas can be a mixture of a reducing agent and an inert gas, with the reducing agent being a minority component of the reducing gas. Using the reducing gas ambient, oxidation of substrate surfaces is reduced.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 27, 2011
    Applicant: ASM INTERNALTIONAL N.V.
    Inventors: Steven R.A. Van Aerde, Rene de Blank
  • Publication number: 20110263131
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.
    Type: Application
    Filed: January 18, 2011
    Publication date: October 27, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukio KATAMURA, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Publication number: 20110263133
    Abstract: A semiconductor device manufacturing apparatus includes: an accommodation section accommodating an application object; an irradiation section irradiating the application object taken out from the accommodation section with ultraviolet light; an application section including a stage allowing the application object to be placed thereon and an application head discharging a plurality of droplets of an adhesive to the application object placed on the stage, the application section applying the adhesive through the application head to the application object which is irradiated by ultraviolet light through the irradiation section and is placed on the stage; a drying section drying the adhesive applied on the application object with heat; and a transport section including a hand supporting the application object, the transport section which is capable of transporting the application object accommodated in the accommodation section to the irradiation section, the application section, and the drying section.
    Type: Application
    Filed: April 22, 2011
    Publication date: October 27, 2011
    Applicants: Kabushiki Kaisha Toshiba, SHIBAURA MECHATRONICS CORPORATION
    Inventors: Satoru Hara, Shingo Tamai, Akihiro Shigeyama, Michio Ogawa, Hitoshi Aoyagi, Hiroyuki Tanaka, Yasuo Tane, Yukio Katamura
  • Patent number: 8043981
    Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. A two frequency plasma source is used to form a plasma in a plasma reactor. In various embodiments, different quantities of power are supplied to a power source operating at the first frequency and a power source operating at the second frequency over time.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: October 25, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kai Ma, Yoshitaka Yokota, Christopher S. Olsen
  • Patent number: 8043657
    Abstract: The present invention supplies a solvent to the front surface of a substrate while rotating the substrate. Subsequently, the substrate is acceleratingly rotated to a first number of rotations, and a resist solution is supplied to a central portion of the substrate during the accelerating rotation and the rotation at the first number of rotations. Thereafter, the substrate is deceleratingly rotated to a second number of rotations, and after the number of rotations of the substrate reaches the second number of rotations, the resist solution is discharged to the substrate. The substrate is then acceleratingly rotated to a third number of rotations higher than the second number of rotations so that the substrate is rotated at the third number of rotations. According to the present invention, in application of the resist solution by spin coating, the consumption of the resist solution can be suppressed, and a high in-plane uniformity can be obtained for the film thickness of the resist film.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: October 25, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kousuke Yoshihara, Tomohiro Iseki
  • Patent number: 8043975
    Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: October 25, 2011
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Gurtej S. Sandhu
  • Patent number: 8043942
    Abstract: Disclosed is a method for producing core-shell nanowires in which an insulating film is previously patterned to block the contacts between nanowire cores and nanowire shells. According to the method, core-shell nanowires whose density and position is controllable can be produced in a simple manner. Further disclosed are nanowires produced by the method and a nanowire device comprising the nanowires. The use of the nanowires leads to an increase in the light emitting/receiving area of the device. Therefore, the device exhibits high luminance/efficiency characteristics.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Kyung Lee, Jai Yong Han, Byoung Lyong Choi, Kyung Sang Cho
  • Publication number: 20110254138
    Abstract: An improved low-temperature absorber, amorphous carbonitride (ACN) with an extinction coefficient (k) of greater than 0.15, and an emissivity of greater than 0.8 is disclosed. The ACN film can also be characterized as having a minimum of hydrocarbon content as observed by FTIR. The ACN film can be used as an effective absorbing layer that absorbs a wide range of electromagnetic radiation from different sources including lasers or flash lamps. A method of forming such an ACN film at a deposition temperature of less than, or equal to, 450° C. is also provided.
    Type: Application
    Filed: April 15, 2010
    Publication date: October 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Katherina E. Babich, Pratik P. Joshi, Kam Leung Lee, Deborah A. Neumayer, Spyridon Skordas
  • Publication number: 20110256729
    Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.
    Type: Application
    Filed: February 10, 2011
    Publication date: October 20, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian E. Goodlin, Qidu Jiang
  • Patent number: 8039847
    Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 18, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu, Heung Cho Ko, Shawn Mack
  • Patent number: 8034723
    Abstract: A film deposition apparatus for depositing a film on a substrate by performing a cycle of alternately supplying at least two kinds of reaction gases that react with each other on the substrate to produce a layer of a reaction product in a vacuum chamber is disclosed. The film deposition apparatus includes a ring-shaped locking member that may be provided in or around a wafer receiving portion of a turntable in which the substrate is placed, in order to keep the substrate in the substrate receiving portion.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: October 11, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Yukio Ohizumi, Manabu Honma
  • Patent number: 8034728
    Abstract: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor compounds that include diketonate ligands and/or ketoimine ligands.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 11, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Publication number: 20110244692
    Abstract: A method for forming a nano-textured surface on a substrate is disclosed. An illustrative embodiment of the present invention comprises dispensing of a nanoparticle ink of nanoparticles and solvent onto the surface of a substrate, distributing the ink to form substantially uniform, liquid nascent layer of the ink, and enabling the solvent to evaporate from the nanoparticle ink thereby inducing the nanoparticles to assemble into an texture layer. Methods in accordance with the present invention enable rapid formation of large-area substrates having a nano-textured surface. Embodiments of the present invention are well suited for texturing substrates using high-speed, large scale, roll-to-roll coating equipment, such as that used in office product, film coating, and flexible packaging applications. Further, embodiments of the present invention are well suited for use with rigid or flexible substrates.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 6, 2011
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Sangmoo Jeong, Liangbing Hu, Yi Cui
  • Patent number: 8030219
    Abstract: A coated substrate product is described comprising a substrate and a dielectric coating material comprising carbon, hydrogen, silicon, and oxygen. According to the method, the substrate is processed by plasma cleaning the surface and then depositing a dielectric coating by a suitable plasma process. The coating may contain one or more layers. The substrate may be a rigid material or a thin film or foil. The coated products of this invention have superior dielectric material properties and utility as substrates for the manufacture of rolled or parallel plate capacitors with high energy densities.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: October 4, 2011
    Assignees: Morgan Advanced Ceramics, Inc., K Systems Corporation
    Inventors: Fred M. Kimock, Steven J. Finke, Richard L. C. Wu
  • Publication number: 20110230054
    Abstract: In one embodiment, a semiconductor substrate cleaning method is disclosed. The method can clean a semiconductor substrate by using a chemical of 80° C. or above. The method can rinse the semiconductor substrate by using pure water of 40° C. or above after the cleaning of the semiconductor substrate. The method can then rinse the semiconductor substrate by using pure water of 30° C. or below. In addition, the method can dry the semiconductor substrate.
    Type: Application
    Filed: July 22, 2010
    Publication date: September 22, 2011
    Inventors: Hiroshi TOMITA, Hisashi Okuchi, Minato Inukai, Hidekazu Hayashi, Yasuhito Yoshimizu
  • Publication number: 20110230055
    Abstract: A film forming apparatus and a film forming method for suppressing a drop in the film forming speed caused by-product gas are provided. A film forming apparatus for forming a film on a wafer includes a chamber in which the wafer is located; a gas introducing member configured to introduce raw material gas into the chamber, in which the raw material gas turning into by-product gas and a substance which adheres to the surface of the wafer by reacting at a surface of the wafer; and a reverse reaction member configured to generate the raw material gas by causing the by-product gas to react in the chamber.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takahiro ITO, Kenji NAKASHIMA
  • Patent number: 8022012
    Abstract: A device for fabricating thin films on a substrate includes a vacuum chamber, a rotatable platen configured to hold one or more substrates within the vacuum chamber, and a housing disposed within the vacuum chamber. The housing contains a heating element and is configured to enclose an upper surface of the platen and a lower portion configured to partially enclose an underside surface of the platen which forms a reaction zone. A heated evaporation cell is operatively coupled to the lower portion of the housing and configured to deliver a pressurized metallic reactant to the reaction zone. The device includes a deposition zone disposed in the vacuum chamber and isolated from the reaction zone and is configured to deposit a deposition species to the exposed underside of the substrates when the substrates are not contained in the reaction zone.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: September 20, 2011
    Assignee: Superconductor Technologies, Inc.
    Inventors: Brian H. Moeckly, Ward S. Ruby
  • Patent number: 8022412
    Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: September 20, 2011
    Assignee: National Chung-Hsien University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Shih-Ting Chen, Tshung-Han Tsai, Hsueh-Wei Wu
  • Patent number: 8021987
    Abstract: An insulting film is modified by subjecting the insulting film to a modification treatment comprising a combination of a plasma treatment and a thermal annealing treatment. There is provided a method of enhancing the characteristic of an insulating film by improving deterioration in the characteristic of the insulating film due to carbon, a suboxide, a dangling bond or the like contained in the insulating film.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: September 20, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki, Seiji Matsuyama, Kazuhide Hasebe, Shigeru Nakajima, Tomonori Fujiwara
  • Publication number: 20110223773
    Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.
    Type: Application
    Filed: May 19, 2011
    Publication date: September 15, 2011
    Inventors: Vijay Parihar, Christopher Dennis Bencher, Rajesh Kanuri, Marlon E. Menezes
  • Publication number: 20110223750
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes: arranging a semiconductor substrate on a first electrode out of first and second electrodes arranged to be opposed to each other in a vacuum container; applying negative first pulse voltage and radio-frequency voltage to the first electrode, the negative first pulse voltage being superimposed with the radio-frequency voltage; applying negative second pulse voltage to the second electrode in an off period of the first pulse voltage; and processing the semiconductor substrate or a member on the semiconductor substrate by plasma formed between the first and second electrodes.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 15, 2011
    Inventors: Hisataka HAYASHI, Takeshi Kaminatsui, Akio Ui
  • Patent number: 8017458
    Abstract: Fluid media comprising inorganic semiconductor components for fabrication of thin film transistor devices.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: September 13, 2011
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Antonio Facchetti, Paul D. Byrne, Hyun Sung Kim
  • Publication number: 20110217849
    Abstract: A device for producing a microwave plasma, and a device and a method for treating semiconductor substrates with a microwave plasma, the microwave plasma device comprising at least one electrode (21, 22, 23), an electrode (21, 22, 23) comprising a coaxial inner conductor (21) made of electrically conductive material and a coaxial outer conductor (22) made of electrically conductive material and surrounding the inner conductor at least partially and being disposed at a distance thereto, and a plasma ignition device (23) that is connected to the coaxial inner conductor (21), characterized in that the coaxial outer conductor (22) comprises at least one first partial region (31) in which it completely surrounds the coaxial inner conductor (21) along the longitudinal axis thereof and comprises at least one further partial region (32) in which it surrounds the coaxial inner conductor (21) partially such that microwave radiation generated by the microwave generator (20) can exit in the at least one further partial re
    Type: Application
    Filed: August 4, 2009
    Publication date: September 8, 2011
    Inventors: Wilfried Lerch, Zsolt Nenyel, Thomas Theiler
  • Publication number: 20110217806
    Abstract: An electrode (3i) of a radiofrequency parallel plate plasma reactor comprises an electrode surface of a multitude of surfaces of metal members (28) which reside on dielectric spacing members (29), whereby the metal members (28) are mounted in an electrically floating manner. The dielectric members (29) are mounted, opposite to the metal members (28), upon a metal Rf supply body (14a).
    Type: Application
    Filed: September 28, 2009
    Publication date: September 8, 2011
    Applicant: OERLIKON SOLAR AG, TRUEBBACH
    Inventor: Stephan Jost
  • Patent number: 8012885
    Abstract: To provide a manufacturing method of a semiconductor device capable of performing a selective growth at a low temperature. A manufacturing method of a semiconductor device for placing in a processing chamber a substrate having at least a silicon surface and an insulating film surface on a surface; and allowing an epitaxial film to selectively grow only on the silicon surface by using a substrate processing apparatus for heating an atmosphere in the processing chamber and the substrate, using a heating unit disposed outside of the processing chamber, includes a substrate loading step of loading the substrate into the processing chamber; a pre-processing step of supplying dichlorosilane gas and hydrogen gas into the processing chamber while maintaining a temperature in the substrate processing chamber to a prescribed temperature of 700° C.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: September 6, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yasuhiro Inokuchi, Atsushi Moriya, Yasuhiro Ogawa
  • Patent number: 8012594
    Abstract: A method of manufacturing a functional film by which the functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer by using an inorganic material on a substrate containing a material having heat tolerance to a predetermined temperature; (b) forming a layer to be peeled containing a functional film, which is formed by using a functional material, on the separation layer; and (c) performing heat treatment on a structure containing the substrate, the separation layer and the layer to be peeled at the predetermined temperature so as to peel the layer to be peeled from the substrate or reducing bonding strength between the layer to be peeled and the substrate.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 6, 2011
    Assignee: Fujifilm Corporation
    Inventor: Yukio Sakashita
  • Patent number: 8012884
    Abstract: A predicted film formation rate value is computed based on a film formation rate prediction formula obtained in advance and apparatus parameters obtained during a previously-performed film formation process. A processing time required for an amount of film formed on a wafer to reach a predetermined target film thickness is computed based on the computed predicted film formation rate value and the target film thickness. Then, according to the computed processing time, a film-formation process is performed on wafers. In addition, it is determined whether the computed predicted film formation rate value is within a predetermined range, and only when it is determined to be within the predetermined range, the film formation process may be performed.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Satoshi Yasuda, Shin-ichi Imai
  • Publication number: 20110212626
    Abstract: Disclosed is a substrate processing apparatus, including: a processing chamber for processing a substrate; a substrate rotating mechanism for rotating the substrate; a gas supply unit for supplying gas to the substrate, at least two kinds of gases A and B being alternately supplied a plurality of times to form a desired film on the substrate; and a controller for controlling a rotation period of the substrate or a gas supply period defined as a time period between an instant when the gas A is made to flow and an instant when the gas A is made to flow next time such that the rotation period and the gas supply period are not brought into synchronization with each other at least while the alternate gas supply is carried out predetermined times.
    Type: Application
    Filed: May 10, 2011
    Publication date: September 1, 2011
    Inventors: Masanori SAKAI, Tomohiro YOSHIMURA
  • Publication number: 20110212625
    Abstract: A substrate processing apparatus which is capable of improving a manufacture yield while processing a substrate with high precision, and a method of manufacturing a semiconductor device. The substrate processing apparatus includes a substrate support part provided within a process chamber and configured to support a substrate; a substrate support moving mechanism configured to move the substrate support part; a gas feeding part configured to feed a gas into the process chamber; an exhaust part configured to exhaust the gas within the process chamber; and a plasma generating part disposed to face the substrate support part.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 1, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuyuki TOYODA, Osamu KASAHARA, Yoshiro HIROSE, Hiroyuki TAKADERA, Daigi KAMIMURA
  • Patent number: 8008213
    Abstract: A method of making a device includes forming at least one anodizable metal layer over at least one of an electrode or a semiconductor device, forming a plurality of pores in the anodizable metal layer by anodization of the anodizable metal layer to expose a portion of the electrode or semiconductor device, and filling at least one pore with a rewritable material such that at least some of the rewritable material is in electrical contact with the electrode or semiconductor device.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 30, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Li Xiao, Jingyan Zhang, Huicai Zhong
  • Publication number: 20110207333
    Abstract: A semiconductor wafer (10) is structured such that fine structures (3), such as membranes, bridges or tongues, with a thickness d<<D are formed, wherein D designates the thickness of the semiconductor wafer (10). Then particles of a desired material are applied. A temporal or spatial temperature gradient is generated in the semiconductor wafer (10), e.g. by progressive heating. In such a heating process the fine structures heat up more quickly and become hotter than the remaining wafer because they have a smaller heat capacity per area and cannot carry off heat as quickly. In this manner, the fine structures can be heated to a temperature that allows a sintering of the particles. For coating the semiconductor wafer (10) is brought into a reactor (11). A precursor compound of a metal is provided and fed to the reactor (11), where a reaction takes place during which the metal is transformed to a final compound and is deposited in the form of particles on the semiconductor wafer (10).
    Type: Application
    Filed: April 26, 2011
    Publication date: August 25, 2011
    Inventors: Felix Mayer, Christoph Kleinlogel
  • Publication number: 20110204484
    Abstract: Measurement targets for use on substrates, and overlay targets are presented. The targets include an array of first regions alternating with second regions, wherein the first regions include structures oriented in a first direction and the second regions include structures oriented in a direction different from the first direction. The effective refractive index of the two sets of regions are thereby different when experienced by a polarized beam, which will act as a TM-polarized beam when reflected from the first set of regions, but as a TE-polarized beam when reflected from the second set of regions.
    Type: Application
    Filed: May 27, 2009
    Publication date: August 25, 2011
    Applicant: ASMD NETHERLANDS B.V.
    Inventors: Maurits Van Der Schaar, Marcus Adrianus Van De Kerkhof, Sami Musa
  • Patent number: 8003546
    Abstract: In a method of growing silicon (Si) using a reactor, a supercritical fluid including a silicon Si source and hydrogen flows in the reactor, and the Si source reacts with hydrogen. A base substrate of a solar cell may be formed with Si made using the method of growing silicon (Si). The supercritical fluid may be a fluid in which Si is not oxidized and may be, for example, a CO2 supercritical fluid with a pressure of about 60 to about 200 atm. The Si source may be TriChloroSilane (TCS) (SiCl3H) or SiH4.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: August 23, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Chang-soo Lee, Dong-joon Ma
  • Publication number: 20110198730
    Abstract: A method of synthesizing a hyperbranched polymer by living radical polymerization of a monomer in the presence of a metal catalyst includes at least adding a compound or setting the amount of the monomer in the living radical polymerization. The compound added is at least a compound represented by R1-A or a compound represented by R2—B—R3, where R1 denotes hydrogen, an alkyl group (1-10 carbons), aryl group (1-10 carbons), or aralkyl group (7-10 carbons), A denotes a cyano group, hydroxyl group, or nitro group, R2 and R3 denote hydrogen, alkyl groups (1-10 carbons), aryl groups (6-10 carbons), aralkyl groups (7-10 carbons), or dialkylamino groups (2-10 carbons), and B denotes a carbonyl group or sulfonyl group. Setting of the monomer amount includes setting the amount of monomer to be mixed into a reaction system at one mixing to be less than the total monomer to be mixed with the reaction system.
    Type: Application
    Filed: December 20, 2007
    Publication date: August 18, 2011
    Inventors: Yuko Tanaka, Akinori Uno, Shinichiro Kabashima, Minoru Tamura, Yoshiyasu Kubo, Yusuke Sasaki, Mineko Horibe, Yukihiro Kaneko, Kaoru Suzuki
  • Publication number: 20110198736
    Abstract: Methods and structures relating to the formation of mixed SAMs for preventing undesirable growth or nucleation on exposed surfaces inside a reactor are described. A mixed SAM can be formed on surfaces for which nucleation is not desired by introducing a first SAM precursor having molecules of a first length and a second SAM precursor having molecules of a second length shorter than the first. Examples of exposed surfaces for which a mixed SAM can be provided over include reactor surfaces and select surfaces of integrated circuit structures, such as insulator and dielectric layers.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 18, 2011
    Applicant: ASM America, Inc.
    Inventors: ERIC SHERO, Mohith Verghese, Anthony Muscat, Shawn Miller
  • Patent number: 7998878
    Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is soluble in an aqueous solution comprising at least 50 weight % water and has an acid content of less than 2.5 meq/g of polymer. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: August 16, 2011
    Assignee: Eastman Kodak Company
    Inventors: David H. Levy, Lee W. Tutt
  • Publication number: 20110193103
    Abstract: A semiconductor device is provided with a porous structure layer formed by silicone resin between a substrate and a semiconductor element. Alternatively, a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing at least one type of alkoxysilane selected from a group consisting of monoalkoxysilane, dialkoxysilane, and trialkoxysilane, and tetraalkoxysilane is provided between the substrate and the semiconductor element. As a further alternative, an adhesion layer formed by a compound obtained by hydrolyzing and condensing an alkoxysilane is provided on a resin substrate, and a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing an alkoxysilane, is provided on the adhesion layer.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 11, 2011
    Applicant: FUJIFILM Corporation
    Inventors: Keigo SATO, Shigenori YUUYA
  • Patent number: 7994509
    Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: August 9, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ping Mei, Hao Luo, Carl Taussig
  • Patent number: 7994068
    Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: August 9, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Steven J. Radigan, Michael W. Konevecki
  • Patent number: 7992318
    Abstract: A disclosed heating apparatus for heating a substrate on which a film is coated includes a process chamber having a gas supply opening for supplying a first gas to the process chamber and a gas evacuation opening for evacuating the first gas from the process chamber; a heating plate that is arranged in the process chamber and includes a heating element for heating the substrate; plural protrusions arranged on the heating plate so as to support the substrate; plural suction holes formed in the heating plate so as to attract by suction the substrate toward the heating plate; and a gas inlet adapted to supply a second gas to a gap between the heating plate and the substrate supported by the plural protrusions.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: August 9, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Kawaji, Yuichi Sakai, Masatoshi Kaneda