Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Publication number: 20120064728
    Abstract: A substrate depositing system and a method of using a substrate depositing system. A substrate depositing system includes a load-lock chamber for loading and unloading a substrate, at least one transfer chamber connected to the load-lock chamber and including a substrate transfer device configured to vertically transfer the substrate, and a pair of depositing chambers connected to opposite sides of the at least one transfer chamber and including a depositing source and a pair of substrate fixing devices, the substrate transfer device including a pair of substrate installing members.
    Type: Application
    Filed: July 8, 2011
    Publication date: March 15, 2012
    Inventors: Jeong-Ho Yi, Suk-Won Jung, Seung-Ho Choi
  • Patent number: 8133549
    Abstract: The present invention relates to the use of a R—N2+ diazonium salt carrying an aromatic group R, for grafting of the aromatic group onto insulating, semiconductor, binary or ternary compound or composite material surfaces, the diazonium salt being present at a concentration close to its solubility limit, notably at a concentration higher than 0.05 M, and preferably varying between approximately 0.5 M to approximately 4 M.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: March 13, 2012
    Assignee: Alchimer
    Inventors: Christophe Bureau, Jean Pinson
  • Patent number: 8129285
    Abstract: A substrate processing method implemented in a substrate processing system that includes an etching apparatus that carries out plasma etching processing on a substrate and a vacuum-type substrate transferring apparatus to which the etching apparatus is connected is provided. A first step includes forming a protective film on a rear surface of the substrate before the plasma etching processing is carried out. The protective film prevents the rear surface of the substrate from being scratched by an electrostatic chuck that electrostatically attracts the substrate during the plasma etching processing. A second step includes electrostatically attracting the substrate to the electrostatic chuck such that the electrostatic chuck directly contacts the rear surface of the substrate and of carrying out the plasma etching processing on the substrate. A third step includes removing the protective film from the rear surface of the substrate after the plasma etching processing has been carried out.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: March 6, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Eiichi Nishimura
  • Patent number: 8129288
    Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: March 6, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Sunil Shanker, Tony Chiang
  • Patent number: 8129092
    Abstract: The present invention provides a resist pattern thickening material, which can utilize ArF excimer laser light; which, when applied over a resist pattern such as an ArF resist having a line pattern or the like, can thicken the resist pattern regardless of the size of the resist pattern; which has excellent etching resistance; and which is suited for forming a fine space pattern or the like, exceeding the exposure limits. The present invention also provides a process for forming a resist pattern and a method for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: March 6, 2012
    Assignee: Fujitsu Limited
    Inventors: Miwa Kozawa, Koji Nozaki
  • Publication number: 20120045902
    Abstract: Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication with the plenum. Showerhead electrode assemblies including a showerhead electrode flexibly suspended from a top plate are also disclosed. The showerhead electrode assemblies can be in fluid communication with temperature-control elements spatially separated from the showerhead electrode to control the showerhead electrode temperature. Methods of processing substrates in plasma processing chambers including the showerhead electrode assemblies are also disclosed.
    Type: Application
    Filed: October 28, 2011
    Publication date: February 23, 2012
    Applicant: Lam Research Corporation
    Inventors: Andreas Fischer, Rajinder Dhindsa
  • Publication number: 20120045884
    Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Inventors: Jeffrey Chinn, Boris Kobrin, Romuald Nowak
  • Patent number: 8119196
    Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
  • Patent number: 8119547
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiaki Kobayashi
  • Patent number: 8119532
    Abstract: A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the processing chamber. One or more gas sources in fluid communication with one or more gas distribution members supply process gas to a first zone adjacent to the first substrate support and a second zone adjacent to the second substrate support. A radio-frequency (RF) antenna adapted to inductively couple RF energy into the interior of the processing chamber and energize the process gas into a plasma state in the first and second zones. The antenna is located between the first substrate support and the second substrate support.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: February 21, 2012
    Assignee: Lam Research Corporation
    Inventor: Sanket P. Sant
  • Patent number: 8115189
    Abstract: Provided are a silica nanowire that includes silicon nanodots and a method of preparing the same. The silica nanowire has excellent capacitance characteristics and improved light absorption ability, and thus can be effectively used in a variety of fields, such as various semiconductor devices including CTF memory, image sensors, photodetectors, light emitting diodes, laser diodes, and the like.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: February 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyeongsu Park, Eunkyung Lee, Jaehak Lee, Byounglyong Choi, Jaegwan Chung, Sung Heo
  • Publication number: 20120034786
    Abstract: An electrode is exposed to a plasma generation volume and is defined to transmit radiofrequency power to the plasma generation volume, and includes an upper surface for holding a substrate in exposure to the plasma generation volume. A gas distribution unit is disposed above the plasma generation volume and in a substantially parallel orientation to the electrode. The gas distribution unit includes an arrangement of gas supply ports for directing an input flow of a plasma process gas into the plasma generation volume in a direction substantially perpendicular to the upper surface of the electrode. The gas distribution unit also includes an arrangement of through-holes that each extend through the gas distribution unit to fluidly connect the plasma generation volume to an exhaust region. Each of the through-holes directs an exhaust flow from the plasma generation volume in a direction substantially perpendicular to the upper surface of the electrode.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 9, 2012
    Applicant: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Alexei Marakhatnov, Andrew D. Bailey, III
  • Publication number: 20120034788
    Abstract: A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O3) are alternately fed into the reaction tubeto generate Al2O3 film on the surface of the wafer. The apparatus also includes supply tubes and for flowing the ozone and TMA and a nozzle supplying gas into the reaction tube. The two supply tubes are connected to the nozzle disposed inside the heater in a zone inside the reaction tube where a temperature is lower than a temperature near the wafer, and the ozone and TMA are supplied into the reaction tube through the nozzle.
    Type: Application
    Filed: October 11, 2011
    Publication date: February 9, 2012
    Inventors: Masanori Sakai, Toru Kagaya, Hirohisa Yamazaki
  • Publication number: 20120031332
    Abstract: A method and apparatus for oxidizing materials used in semiconductor integrated circuits, for example, for oxidizing silicon to form a dielectric gate. An ozonator is capable of producing a stream of least 70% ozone. The ozone passes into an RTP chamber through a water-cooled injector projecting into the chamber. Other gases such as hydrogen to increase oxidation rate, diluent gas such as nitrogen or O2, enter the chamber through another inlet. The chamber is maintained at a low pressure below 20 Torr and the substrate is advantageously maintained at a temperature less than 800° C. Alternatively, the oxidation may be performed in an LPCVD chamber including a pedestal heater and a showerhead gas injector in opposition to the pedestal.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Yoshitaka Yokota, Sundar Ramamurthy, Vedapuram Achutharaman, Cory Czarnik, Mehran Behdjat, Christopher Olsen
  • Publication number: 20120034789
    Abstract: A method for manufacturing a semiconductor device includes: performing modifying a surface of a semiconductor wafer including a silanol group on the surface with an alkylsilyl group; and fluorinating an alkyl group of the alkylsilyl group with which the surface was modified.
    Type: Application
    Filed: October 18, 2011
    Publication date: February 9, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Shinichi Ito
  • Patent number: 8110433
    Abstract: A method of fabricating an organic thin film transistor is disclosed, which comprises steps of (S1) forming a gate electrode on a substrate; (S2) forming a gate insulating layer on the gate electrode; (S3) providing a gas on the surface of the gate insulating layer to form hydrophobic molecules on the surface of the gate insulating layer; (S4) forming an organic semiconductor layer, a source electrode, and a drain electrode over the gate insulating layer having hydrophobic molecules thereon, wherein the gas of step (S3) is at least one selected from the group consisting of halogen-substituted hydrocarbon, un-substituted hydrocarbon, and the mixtures thereof. The method of the present invention utilizes gases comprising carbon or fluorine atom to perform surface treatment on the surface of the gate insulating layer, therefore the hydrophobic character of the surface of the gate insulating layer can be enhanced and the electrical properties of the OTFT can be improved.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: February 7, 2012
    Assignee: National Tsing Hua University
    Inventors: Cheng Wei Chou, Hsiao Wen Zan, Jenn-Chang Hwang, Chung Hwa Wang, Li Shiuan Tsai, Wen Chieh Wang
  • Patent number: 8110435
    Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 7, 2012
    Assignee: Jusung Engineering Co., Ltd.
    Inventors: Sang Ki Park, Seong Ryong Hwang, Geun Tae Cho
  • Patent number: 8105437
    Abstract: A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. That is, the method includes in-situ monitoring of the physical, electrical, and optical properties of the thin films.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: January 31, 2012
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Chester A. Farris, III
  • Patent number: 8105953
    Abstract: A semiconductor manufacturing apparatus includes a chamber, a gas supplier, a vacuum pump, an electrode, a conductive knitted wire mesh and a radio frequency power supply. The electrode is placed outside of the chamber and fixed to the chamber. The gas supplier supplies gas into the chamber. The vacuum pump exhausts the chamber. The radio frequency power supply supplies radio frequency power to the electrode through the conductive knitted wire mesh.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichirou Takehara
  • Publication number: 20120021604
    Abstract: A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.
    Type: Application
    Filed: July 22, 2010
    Publication date: January 26, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Liang Lin, Weng-Jin Wu, Jing-Cheng Lin
  • Patent number: 8101522
    Abstract: A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nanostructures.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: January 24, 2012
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Shu-Jia Syu
  • Publication number: 20120015525
    Abstract: A method of cleaning a thin film forming apparatus, for removing deposits adhering to an inside thereof after supplying a film-forming gas into a reaction chamber to form a amorphous carbon film on a workpiece, includes a heating operation of heating at least one of an inside of the reaction chamber and an inside of an exhaust pipe connected to the reaction chamber to a predetermined temperature; and a removing operation of supplying a cleaning gas containing oxygen gas and hydrogen gas into at least one of the inside of the reaction chamber and the inside of the exhaust pipe heated in the heating operation, heating the cleaning gas to the predetermined temperature to activate the oxygen gas and the hydrogen gas contained in the cleaning gas, and thereafter removing the deposits adhering to the inside of the thin film forming apparatus by the oxygen gas and the hydrogen gas activated.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 19, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Atsushi ENDO, Kazumi KUBO, Satoshi MIZUNAGA
  • Publication number: 20120015459
    Abstract: A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Han-Pin Chung, Ming-Hsi Yeh, De-Wei Yu, Kuan-Yu Chen
  • Publication number: 20120009799
    Abstract: According to one embodiment, a template manufacturing method is a method for manufacturing a template for use in an imprint processing in which a pattern having irregularities are formed on a principal surface, and the pattern is brought into contact with a resist member formed on a substrate to be processed, to transfer the pattern to the resist member, the method including implanting charged particles at least into the bottoms of concave portions of the template.
    Type: Application
    Filed: June 1, 2011
    Publication date: January 12, 2012
    Inventors: Tsukasa AZUMA, Tatsuhiko Higashiki, Kyoichi Suguro
  • Publication number: 20120009800
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Inventors: Takuya FUTASE, Tomonori Saeki, Mieko Kashi
  • Publication number: 20120009798
    Abstract: An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Helen Maynard, George D. Papasouliotis
  • Patent number: 8093158
    Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 10, 2012
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Taketoshi Sato, Masayuki Tsuneda
  • Patent number: 8094363
    Abstract: Embodiments of the present invention relate to interferometric display devices comprising an interferometric modulator and a solar cell and methods of making thereof. In some embodiments, the solar cell is configured to provide energy to the interferometric modulator. The solar cell and the interferometric modulator may be formed above the same substrate. A layer of the solar cell may be shared with a layer of the interferometric modulator.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: January 10, 2012
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Teruo Sasagawa, Lior Kogut, Ming-Hau Tung
  • Patent number: 8092606
    Abstract: A deposition apparatus configured to form a thin film on a substrate includes: a reactor wall; a substrate support positioned under the reactor wall; and a showerhead plate positioned above the substrate support. The showerhead plate defines a reaction space together with the substrate support. The apparatus also includes one or more gas conduits configured to open to a periphery of the reaction space at least while an inert gas is supplied therethrough. The one or more gas conduits are configured to supply the inert gas inwardly toward the periphery of the substrate support around the reaction space. This configuration prevents reactant gases from flowing between a substrate and the substrate support during a deposition process, thereby preventing deposition of an undesired thin film and impurity particles on the back side of the substrate.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 10, 2012
    Assignee: ASM Genitech Korea Ltd.
    Inventors: Hyung Sang Park, Seung Woo Choi, Jong Su Kim, Dong Rak Jung, Jeong Ho Lee, Chun Soo Lee
  • Publication number: 20120003438
    Abstract: A supported graphene device comprises at least one graphene feature of 1 to about 10 graphene layers having a predetermined shape and pattern, with at least a portion of each graphene feature being supported on a substrate. In some embodiments the device comprises graphene features supported on crystalline semiconductor substrate, such as silicon or germanium. The graphene features on a crystalline semiconductor substrate can be fabricated by forming an amorphous carbon doped semiconductor on the crystalline semiconductor substrate and then epitaxially crystallizing the amorphous semiconductor with carbon migration to the surface to form a graphene feature of one or more graphene layers. The epitaxy can be promoted by heating the device or by irradiation with a laser.
    Type: Application
    Filed: February 19, 2010
    Publication date: January 5, 2012
    Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Bill R. Appleton, Brent P. Gila
  • Publication number: 20120003837
    Abstract: A plasma processing method of subjecting a substance to plasma processing by using a semiconductor device manufacturing apparatus including a process chamber, a unit for supplying gas to the process chamber, an exhausting unit to reduce pressure in the process chamber, a high frequency power source for plasma generation, a coil for generating a magnetic field, and a mounted electrode for mounting the substance to be processed. The method includes steps of subjecting the substance to a predetermined plasma processing, changing the magnetic field distribution, so as to make a plasma distribution of the process chamber with respect to the surface of the substance to be processed, in a convex form, at a time of igniting the plasma and after completion of the predetermined plasma processing, as compared with a plasma distribution with respect to the surface of the substance to be processed during the predetermined plasma processing.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Inventors: Hiroyuki Kobayashi, Kenji Maeda, Kenetsu Yokogawa, Masaru Izawa
  • Patent number: 8088687
    Abstract: A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: January 3, 2012
    Assignees: Hynix Semiconductor Inc., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Seung Jin Yeom, Jae Hong Kim, Sung Goon Kang, Won Kyu Han
  • Publication number: 20110318937
    Abstract: A method of manufacturing a semiconductor device includes supplying a process gas into a process vessel accommodating a substrate to form a thin film on the substrate and supplying a cleaning gas into the process vessel to clean an inside of the process vessel, after the supplying the process gas to form the thin film is performed a predetermined number of times. When cleaning the inside of the process vessel, a fluorine-containing gas, an oxygen-containing gas and a hydrogen-containing gas are supplied as the cleaning gas into the process vessel heated and kept at a pressure less than an atmospheric pressure to remove a deposit including the thin film adhering to the inside of the process vessel through a thermochemical reaction.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 29, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naonori AKAE, Yoshiro HIROSE, Kotaro MURAKAMI
  • Patent number: 8084368
    Abstract: A barrier film made of a ZrB2 film is formed by use of a coating apparatus provided with plasma generation means including a coaxial resonant cavity and a microwave supply circuit for exciting the coaxial resonant cavity, the coaxial resonant cavity including spaced apart conductors provided around the periphery of a nonmetallic pipe for reactive gas introduction, the coaxial resonant cavity having an inner height equal to an integer multiple of one-half of the exciting wavelength, the plasma generation means being constructed such that a gas injected from one end of the nonmetallic pipe is excited into a plasma state by a microwave when the gas is in a region of the nonmetallic pipe which is not covered with the conductors and such that the gas in the plasma state is discharged from the other end of the nonmetallic pipe.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: December 27, 2011
    Assignee: Ulvac, Inc.
    Inventors: Masanobu Hatanaka, Michio Ishikawa, Kanako Tsumagari
  • Patent number: 8084278
    Abstract: A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature in the film forming furnace is heated to a range of 800° C. to 950° C. under reduced pressure while an inert gas such as Ar or helium (He) is being introduced through a gas introduction part. When the temperature reaches this temperature range, an inflow of the inert gas is stopped. Vaporized ethanol is introduced as a source gas into the film forming furnace through the gas introduction part, thus forming a graphite film on an entire surface of the wafer WF.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: December 27, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukio Uda, Koichi Sekiya, Kazuo Kobayashi, Yoichiro Tarui
  • Patent number: 8084375
    Abstract: A hot edge ring with extended lifetime comprises an annular body having a sloped upper surface. The hot edge ring includes a step underlying an outer edge of a semiconductor substrate supported in a plasma processing chamber wherein plasma is used to process the substrate. The step includes a vertical surface which surrounds the outer edge of the substrate and the sloped upper surface extends upwardly and outwardly from the upper periphery of the vertical surface.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 27, 2011
    Assignee: Lam Research Corporation
    Inventors: Akira Koshiishi, Sathya Mani, Gautam Bhattacharyya, Gregory R. Bettencourt, Sandy Chao
  • Publication number: 20110312187
    Abstract: A manufacturing apparatus for a semiconductor device, including: a reaction chamber configured to perform film formation on a wafer; a process gas supplying mechanism provided in an upper part of the reaction chamber and configured to introduce process gas to an interior of the reaction chamber; a gas discharging mechanism provided in a lower part of the reaction chamber and configured to discharge gas from the reaction chamber; a supporting member configured to hold the wafer; a cleaning gas supplying mechanism provided in an outer periphery of the supporting member and configured to emit cleaning gas in an outer periphery direction below an upper end of the supporting member; a heater configured to heat the wafer; and a rotary driving mechanism configured to rotate the wafer.
    Type: Application
    Filed: June 14, 2011
    Publication date: December 22, 2011
    Inventors: Kunihiko Suzuki, Hideki Ito
  • Publication number: 20110312188
    Abstract: A processing apparatus for processing objects, includes: a processing container structure having a bottom opening and including a processing container having a processing space for housing the objects, the container having a nozzle housing area on one side of the processing space and a slit-like exhaust port on the opposite side of the processing space from the nozzle housing area; a lid for closing the bottom opening of the processing container structure; a support structure for supporting the objects and which can be inserted into and withdrawn from the processing container structure; a gas introduction means including a gas nozzle housed in the nozzle housing area; an exhaust means including a plurality of exhaust systems for exhausting the atmosphere in the processing container structure; a heating means for heating the objects; and a control means for controlling the gas introduction means, the exhaust means and the heating means.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 22, 2011
    Applicant: Tokyo Electron Limited
    Inventors: Yu WAMURA, Yuichiro Morozumi, Izumi Sato, Shinji Asari
  • Publication number: 20110312189
    Abstract: A substrate treating apparatus is provided. The substrate treating apparatus includes a loading/unloading unit, a process unit in which a substrate treating process is performed, a loadlock unit disposed between the loading/unloading unit and the process unit, and a carrying member transferring a substrate between the process unit and the loadlock unit. Herein, the carrying member is provided in the process unit and the loadlock unit, and the loading/unloading unit, the loadlock unit, and the process unit are sequentially disposed.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 22, 2011
    Applicant: SEMES CO., LTD.
    Inventors: Sungho KIM, Choonsik KIM, Yongtaek EOM, Hyuntaek OH, Hyungkeun PARK
  • Patent number: 8080483
    Abstract: A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 20, 2011
    Assignee: Purdue Research Foundation
    Inventors: Hugh W. Hillhouse, Vikrant N. Urade, Ta-Chen Wei, Michael P. Tate
  • Patent number: 8080481
    Abstract: The present invention provides a method for manufacturing a semiconductor nanowire device in mass production at a low cost without an additional complex nanowire alignment process or SOI substrate by forming a single crystal silicon nanowire with a simple process without forming an ultra fine pattern using an electron beam and transferring the nanowire separated from the substrate to another oxidation layer or insulation substrate. And also, the present invention suggests a method for simply manufacturing a nanowire device transferring the nanowire from a semiconductor substrate formed thereon the nanowire to another substrate formed thereon an insulation layer or the like.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: December 20, 2011
    Assignee: Korea Electronics Technology Institute
    Inventors: Kook-Nyung Lee, Woo Kyeong Seong, Suk-Won Jung, Won-hyo Kim
  • Publication number: 20110306217
    Abstract: According to one embodiment, the thin film forming apparatus includes a boat capable of holding two wafers, in each of which a cutout portion is provided in an outer peripheral edge portion, in a groove portion for holding a wafer in a state where back surfaces face each other. Moreover, the thin film forming apparatus includes a reactor that accommodates the boat and form a coating on each of surfaces of the two wafers by a vapor deposition reaction. The positions in the groove portion, at which the two wafers are held, respectively, are displaced in a direction parallel to the surfaces of the wafers.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nobuyoshi SATO
  • Publication number: 20110306216
    Abstract: A holding device adapted for holding a mask and a substrate during processing of the substrate is provided. The holding device includes a mask frame adapted for supporting the mask and a substrate carrier adapted for carrying the substrate to be processed. The substrate carrier has at least one recess adapted for receiving the mask frame which holds the mask.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 15, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Uwe SCHUESSLER, Stefan BANGERT, Heike LANDGRAF
  • Publication number: 20110300716
    Abstract: Methods, apparatus, and systems for depositing materials with gaseous precursors are provided. In certain implementations, the methods involve providing a wafer substrate to a chamber of an apparatus. The apparatus includes a showerhead to deliver a gas to the chamber, a volume, and an isolation valve between the volume and the showerhead. A gas is delivered the volume when the isolation valve is closed, pressurizing the volume. The isolation valve is opened to allow the gas to flow to the showerhead when the gas is being delivered to the volume. A material is formed on the wafer substrate using the gas. In some implementations, releasing the pressurized gas from the volume reduces the duration of time to develop a spatially uniform gas flow across the showerhead.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 8, 2011
    Inventors: Kie-Jin PARK, Karl LEESER, Frank GREER, David COHEN
  • Patent number: 8071157
    Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10?5 q? (mm) given with respect to a surface tension ? (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10?5 (m·sec/N).
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Tatsuhiko Ema, Kei Hayasaki, Rempei Nakata, Nobuhide Yamada, Katsuya Okumura
  • Publication number: 20110290134
    Abstract: According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on the quartz plate, and impurities are contained in a portion between the concave sections in the quartz plate.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventors: Masamitsu ITOH, Shingo Kanamitsu
  • Publication number: 20110294303
    Abstract: An apparatus for plasma processing a substrate is provided. The apparatus comprises a processing chamber, a substrate support disposed in the processing chamber, a shield member disposed in the processing chamber below the substrate support, and a lid assembly coupled to the processing chamber. The lid assembly comprises a conductive gas distributor coupled to a power source, and an electrode separated from the conductive gas distributor and the chamber body by electrical insulators. The electrode is also coupled to a source of electric power. The substrate support is formed with a stiffness that permits very little departure from parallelism. The shield member thermally shields a substrate transfer opening in the lower portion of the chamber body. A pumping plenum is located below the substrate support processing position, and is spaced apart therefrom.
    Type: Application
    Filed: May 6, 2011
    Publication date: December 1, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Ramprakash Sankarakrishnan, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Dale R. Du Bois, Mark Fodor, Jianhua Zhou, Amit Bansal, Mohamad A. Ayoub, Shahid Shaikh, Patrick Reilly, Deenesh Padhi, Thomas Nowak
  • Publication number: 20110294286
    Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Hung, Yung-Sung Yen, Chun-Kuang Chen
  • Patent number: 8067060
    Abstract: A polymer layer is deposited on a surface of a support, said surface comprising a flat main part and at least one recessed zone with respect to the flat main part. The polymer layer is achieved by at least the following successive steps: deposition of a predetermined quantity of a liquid mixture comprising at least a polymer or at least a precursor of said polymer on the flat main part of the surface of the support, introducing at least a part of the liquid mixture into the recessed zone by moving a cylinder placed on the flat main part of the surface, deposition of an additional quantity of liquid mixture on the flat main part of the surface, and rotation of the support along an axis perpendicular to the plane of the surface.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: November 29, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Christiane Puget, David Henry
  • Publication number: 20110287635
    Abstract: A wafer carrier for a rotating disc CVD reactor includes a unitary plate of a ceramic such as silicon carbide defining wafer-holding features such as pockets on its upstream surface and also includes a hub removably mounted to the plate in a central region of the plate. The hub provides a secure connection to the spindle of the reactor without imposing concentrated stresses on the ceramic plate. The hub can be removed during cleaning of the plate.
    Type: Application
    Filed: July 22, 2011
    Publication date: November 24, 2011
    Applicant: VEECO INSTRUMENTS INC.
    Inventors: Vadim Boguslavskiy, Alexander I. Gurary