Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 8283261
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: October 9, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Publication number: 20120252222
    Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicant: TEL EPION INC.
    Inventor: John Gumpher
  • Publication number: 20120248633
    Abstract: There is provided a method of manufacturing a thin-film device, the method including forming a first substrate on a supporting base by a coating method, the first substrate being formed by using a resin material; forming a second substrate on the first substrate by using any one of a thermosetting resin and energy ray-curable resin; forming an active element on the second substrate; and removing the supporting base from the first substrate. The resin material used to form the first substrate has a glass transition temperature of at least 180° C.
    Type: Application
    Filed: March 8, 2012
    Publication date: October 4, 2012
    Applicant: SONY CORPORATION
    Inventors: Toshio Fukuda, Yui Ishii
  • Publication number: 20120248582
    Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Shiqun Gu, Ratibor Radojcic, Yiming Li
  • Patent number: 8278724
    Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: October 2, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
  • Patent number: 8276537
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Publication number: 20120241767
    Abstract: Disclosed are an SiC semiconductor element and manufacturing method for an SiC semiconductor element in which the interface state density of the interface of the insulating film and the SiC is reduced, and channel mobility is improved. Phosphorus (30) is added to an insulating film (20) formed on an SiC semiconductor (10) substrate in a semiconductor element. The addition of phosphorous to the insulating film makes it possible to significantly reduce the defects (interface state density) in the interface (21) of the insulating film and the SiC, and to dramatically improve the channel mobility when compared with conventional SiC semiconductor elements. The addition of phosphorus to the insulating film is carried out by heat treatment. The use of heat treatment to add phosphorous to the insulating film makes it possible to maintain the reliability of the insulating film, and to avoid variation in channel mobility and threshold voltage.
    Type: Application
    Filed: December 13, 2010
    Publication date: September 27, 2012
    Inventors: Hiroshi Yano, Dai Okamoto
  • Patent number: 8273668
    Abstract: Methods of forming a pattern and methods of fabricating a semiconductor device having a pattern are provided, the methods include forming a self-assembly induction layer including a first region and a second region on a semiconductor substrate. A block copolymer layer is coated on the self-assembly induction layer. A first pattern, a second pattern and a third pattern are formed by phase separating the block copolymer. At least one of the first, second and third patterns may be removed to form a preliminary pattern. An etching process may be performed using the preliminary pattern as an etching mask. The first pattern contains the same material as that of the second pattern, and the third pattern contains a material different from that of the first pattern.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: September 25, 2012
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Dong Ki Yoon, Shiyong Yi, Kyoungseon Kim, Seongwoon Choi, Seokhwan Oh, Sang Ouk Kim, Seung Hak Park
  • Publication number: 20120238106
    Abstract: A coating method for coating a treatment liquid having a viscosity of 5 cp or less on a substrate includes rotating the substrate, increasing a rotation speed of the substrate while discharging the treatment liquid on the substrate from a nozzle, and repeating at least twice increasing and decreasing the rotation speed of the substrate while discharging the treatment liquid on the substrate from the nozzle.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 20, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Chung-Bin CHUANG
  • Publication number: 20120238105
    Abstract: The present invention relates to formula, comprising at least one solvent, and at least one functional composition of the general formula (I), wherein A is a functional structural element, B is a solvent-providing structural element, and k is an integer in the range of 1 to 20. The molecular weight of the functional composition is at least 550 g/mol, and the solvent-providing structural element B corresponds to the general formula ((L-I). Ar1, Ar2 JeWeUs, independently of each other, signify an aryl or heteroaryl group, which can be substituted with one or several discretionary residues R. Each X is, independently of one another, N or CR2, preferably CH.
    Type: Application
    Filed: May 3, 2010
    Publication date: September 20, 2012
    Applicant: Merck Patent GmbH
    Inventors: Rémi Manouk Anémian, Susanne Heun, Thomas Eberle, Philipp Stoessel
  • Patent number: 8268730
    Abstract: A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: September 18, 2012
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 8268384
    Abstract: A substrate transfer system to reduce total processing time by transferring a substrate at a first delivery stage to a process block where processing can be carried out earliest. The substrate processing apparatus includes a first transfer device delivering a wafer with respect to a substrate carrier, and a second transfer device delivering a wafer between a plurality of process blocks and the first transfer device via a first delivery stage, to transfer the wafer with respect to the process blocks. The process block where there is no wafer or where processing of the last wafer within the relevant process block will be completed earliest is determined based on processing information of the wafers from the process blocks, and the wafer of the first delivery stage is transferred by the second transfer device to the relevant process block. This ensures smooth transfer of the wafer to the process block.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: September 18, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Nobuaki Matsuoka, Yoshio Kimura, Akira Miyata
  • Patent number: 8263235
    Abstract: An organic light emitting device having a high light extraction efficiency and being excellent in an light emitting efficiency and durability is provided. The organic light emitting device includes an anode and a cathode, and a layer formed of an organic compound interposed between the anode and the cathode. The layer formed of the organic compound includes a light emitting layer, and the light emitting layer is formed of at least one organic light emitting material and an aliphatic compound, and a refractive index of the light emitting layer is 1.40 or more to 1.60 or less.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: September 11, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichi Suzuki
  • Publication number: 20120225564
    Abstract: In the disclosed vapor deposition method, by using a structure wherein an inner diameter of a group-V source gas introduction piping is greater than an outer diameter a group-III source gas introduction piping, and the group-III source gas introduction piping is inserted one-to-one into the interior of the group-V source gas introduction piping, the group-III source gas piping is thereby prevented from being cooled by a cooling mechanism, and hardening of metallic materials upon the surface of the wall of the piping is alleviated. It is thus possible to provide a vapor deposition device, a vapor deposition method, and a semiconductor element manufacturing method, which are capable of efficaciously introducing easily hardening metallic materials into a reactor without the metallic materials adhering to a showerhead or a piping, and to carry out efficacious doping.
    Type: Application
    Filed: April 19, 2011
    Publication date: September 6, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yusuke Adachi, Hidekazu Sakagami
  • Publication number: 20120220136
    Abstract: According to one embodiment, a pattern data generating apparatus comprises a storage unit that stores a table defining direct self assembly information that combines a direct self assembly material, a film thickness of the direct self assembly material, and a process condition for the direct self assembly material according to a pattern dimension, a division unit that divides layout data of a device based on the pattern dimension to generate divided layouts, an extraction unit that extracts the direct self assembly information corresponding to the pattern dimension of the divided layout from the table, and a generation unit that generates pattern data by allocating the direct self assembly information extracted by the extraction unit to the divided layouts.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 30, 2012
    Inventor: Tsukasa AZUMA
  • Patent number: 8252704
    Abstract: This disclosure relates to compositions that include (a) at least one substituted or unsubstituted cyclic alkene, and (b) an antioxidant composition including at least one compound of Formula (I): R1 through R4 in Formula (I) are described in the specification.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: August 28, 2012
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Daniel J. Teff, John L. Chagolla
  • Patent number: 8252698
    Abstract: In a substrate processing method of processing a substrate in which a processing target layer, an intermediate layer, and a mask layer are stacked one on top of another, the mask layer having an opening that partially exposes the intermediate layer, a thickness of the mask layer is increased by depositing deposits on an upper surface of the mask layer with plasma generated from a mixed gas of SF6 gas and a depositive gas represented in a general equation, CxHyFz (where, x, y, and z are positive integers).
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: August 28, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Patent number: 8252697
    Abstract: Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8247332
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: August 21, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart van Schravendijk
  • Publication number: 20120208372
    Abstract: Methods for gas delivery to a process chamber are provided herein. In some embodiments, a method may include flowing a process gas through one or more gas conduits, each gas conduit having an inlet and an outlet for facilitating the flow of gas through the gas conduits and into a gas inlet funnel having a second volume, wherein each gas conduit has a first volume less than the second volume, and wherein each gas conduit has a cross-section that increases from a first cross-section proximate the inlet to a second cross-section proximate the outlet but excluding any intersection points between the gas inlet funnel and the gas conduit, and wherein the second cross-section is non-circular; and delivering the process gas to the substrate via the gas inlet funnel.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: KEDARNATH SANGAM, ANH N. NGUYEN
  • Publication number: 20120208371
    Abstract: Embodiments of the present invention provide a method and apparatus for plasma processing a substrate to form a film on the substrate and devices disposed thereon by controlling the ratio of ions to radicals in the plasma at a given pressure. A given pressure may be maintained to promote ion production using one plasma source, and a second plasma source may be used to provide additional radicals. In one embodiment, a low pressure plasma is generated in a processing region having the substrate positioned therein, and a high pressure plasma is generated in separate region. Radicals from the high pressure plasma are injected into the processing region having the low pressure plasma, thus, altering the natural distribution of radicals to ions at a given operating pressure.
    Type: Application
    Filed: July 28, 2011
    Publication date: August 16, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: MATTHEW SCOTT ROGERS, Zhong Qiang Hua, Christopher S. Olsen
  • Patent number: 8242481
    Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 14, 2012
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson, Lars-Ake Ledebo
  • Patent number: 8242006
    Abstract: A smooth electrode is provided. The smooth electrode includes at least one metal layer having thickness greater than about 1 micron; wherein an average surface roughness of the smooth electrode is less than about 10 nm.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 14, 2012
    Assignee: General Electric Company
    Inventors: Stanton Earl Weaver, Stacey Joy Kennerly, Marco Francesco Aimi
  • Patent number: 8242033
    Abstract: Methods for making and/or treating articles of semiconducting material are disclosed. In various methods, a first article of semiconducting material is provided, the first article of semiconducting material is heated sufficiently to melt the semiconducting material, and the melted semiconducting material is solidified in a direction substantially parallel to a shortest dimension of the melted article of semiconducting material. Articles of semiconducting materials made by methods described herein are also disclosed.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: August 14, 2012
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Balram Suman, Natesan Venkataraman
  • Patent number: 8242026
    Abstract: Provided is a method for performing etching process or film forming process to a substrate W whereupon a prescribed pattern is formed with an opening. The method is provided with a step of mixing a liquid and a gas, at least one of which contains a component that contributes to the etching process or the film forming process, and generating charged nano-bubbles 85 having a diameter smaller than that of the opening formed on the semiconductor substrate W; a step of forming an electric field to attract the nano-bubbles onto the surface of the substrate W; and a step of performing the process by supplying the substrate with the liquid containing the nano-bubbles 85 while forming the electric field.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 14, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Sumie Nagaseki
  • Publication number: 20120202352
    Abstract: A vertical single wall reaction tube type batch processing furnace can reduce the generation of particles. A method of removing native oxide film by fluoride gas can enhance the efficiency of utilization of gas. A method of exciting reaction gas by a catalyst at high temperature can be applied to a batch processing. A method of exciting reaction gas by a catalyst utilizes an oxidizing agent and gas other than an oxidizing agent. The flow rate of gas in the gas injection pipe and that of gas in the exhaust pipe are made to be substantially equal to each other. The gap between two adjacent wafers is made greater than the mean free path of gas. The oxidizing agent is dissociated by a catalyst of Ir, V or Kanthal while the gas other than the oxidizing agent is dissociated by a catalyst of W.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 9, 2012
    Applicant: F.T.L. CO., LTD.
    Inventor: Mikio TAKAGI
  • Publication number: 20120202307
    Abstract: A first waveguide member is formed, as viewed from above, in an image pickup region and a peripheral region of a semiconductor substrate. A part of the first waveguide member, which part is disposed in the peripheral region, is removed. A flattening step is then performed to flatten a surface of the first waveguide member on the side opposite to the semiconductor substrate.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 9, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Sho Suzuki, Takehito Okabe, Masatsugu Itahashi
  • Publication number: 20120202351
    Abstract: Methods of fabricating a photo mask are provided. The method includes collecting sample data, setting a preliminary mask layout, performing an optical proximity correction using the sample data and a preliminary mask layout to obtain an optimized preliminary mask layout, verifying the optimized preliminary mask layout to obtain a final mask layout, and fabricating the photo mask using the final mask layout. Verification of the optimized preliminary mask layout includes operating a verification simulator using the sample data and the optimized preliminary mask layout as input data to obtain verification image data. The verification image data includes a plurality of contours of a pattern at different vertical positions.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 9, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hosun Cha, Eunmi Lee, Sungwoo Lee
  • Publication number: 20120202355
    Abstract: A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 9, 2012
    Applicant: Spansion LLC
    Inventors: Rinji Sugino, Bradley Marc Davis, Lei Xue, Kenichi Ohtsuka
  • Patent number: 8236378
    Abstract: A wet processing system detects a globule of a process solution in a drippy or dripping state from the tip of any one of process solution pouring nozzles being moved to a pouring position for pouring the process solution onto a substrate by obtaining image data on the process solution pouring nozzle, and takes proper measures to prevent the process solution from dripping. A wet processing system 1 pours a process solution, such as a resist solution, through one of process solution pouring nozzles 10 onto a surface of a substrate, such as a wafer W, held substantially horizontally by a substrate holding device 41 surrounded by a cup 5 to process the surface by a wet process. A nozzle carrying mechanism 10a carries the process solution pouring nozzles 10 between a home position on a nozzle bath 14 and a pouring position above the substrate held by the substrate holding device 41. An optical image of the tips of the process solution pouring nozzles 10 is obtained by an image pickup means, such as a camera 17.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: August 7, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Tsunenaga Nakashima, Michio Kinoshita, Kousuke Nakamichi
  • Patent number: 8236705
    Abstract: Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nitin H. Parbhoo, Spyridon Skordas
  • Patent number: 8231731
    Abstract: A process for producing a semiconductor device, comprising the steps of conducting film formation on substrate (10) in reactor (1); and unloading the substrate (10) after film formation from the reactor (1) and thereafter effecting forced air cooling of the interior of the reactor (1) while the substrate (10) is absent in the reactor (1). The stress of deposited film adhering in the reactor (1) is increased over that exhibited at air cooling without blower so as to positively generate thermal stress with the result that the deposited film would undergo forced cracking over that exhibited at air cooling without blower. Microparticles scattered by the cracking are efficiently discharged from the reactor forcibly through purging in the reactor in the state of atmospheric pressure.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: July 31, 2012
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Kenichi Suzaki, Jie Wang
  • Patent number: 8232216
    Abstract: Provided are a semiconductor manufacturing apparatus and method, capable of reliably and rapidly transporting a heated semiconductor wafer. the apparatus is provided for transporting a semiconductor wafer, which has been processed by desired treatment (for example, film formation) and is held by a susceptor equipped with a heater, to the outside by a transport arm which holds the semiconductor wafer by suction, by moving the susceptor to a certain position above a top of a wafer waiting stage and introducing the semiconductor wafer held by the susceptor onto the top of the wafer waiting stage. Then, the susceptor present on the top of the wafer waiting stage is moved in a horizontal direction. After a certain cooling time, the transport arm holds the semiconductor wafer placed on the wafer waiting stage by suction and transports the semiconductor wafer to outside.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: July 31, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hiroyuki Baba, Tomoyasu Kai
  • Patent number: 8231939
    Abstract: A method and device for wet treatment of plate-like articles includes, a chuck for holding a single plate-like article having an upwardly facing surface for receiving liquid running off a plate-like article when being treated with liquid, wherein the chuck is outwardly bordered by a circumferential annular lip. The chuck has an outer diameter greater than the greatest diameter of the plate-like article to be treated, and a rotatable part with an upwardly facing ring-shaped surface for receiving liquid running off the circumferential lip of the chuck. The rotatable part is rotatable with respect to the chuck, the ring-shaped surface is coaxially arranged with respect to the circumferential annular lip, the inner diameter of the ring-shaped surface is smaller than the outer diameter of the chuck, and the distance d between the lip and the upwardly facing ring-shaped surface is in a range from 0.1 mm to 5 mm.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: July 31, 2012
    Assignee: Lam Research AG
    Inventors: Michael Brugger, Alexander Schwarzfurtner
  • Publication number: 20120190211
    Abstract: In a film forming method, firstly, a processing target substrate W as a base of a semiconductor device is held on a mounting table 34 by an electrostatic chuck. Then, a film forming gas is adsorbed onto the processing target substrate W (a gas adsorption process) ((A) of FIG. 6). Thereafter, the inside of the processing chamber 32 is evacuated in order to remove residues of the film forming gas ((B) of FIG. 6). Upon the completion of the first exhaust process, a plasma process using microwave is performed ((C) of FIG. 6). Upon the completion of the plasma process, the inside of the processing chamber 32 is evacuated in order to remove an unreacted reactant gas and the like ((D) of FIG. 6). These series of steps (A) to (D) are repeated in this sequence until a desired film thickness is obtained.
    Type: Application
    Filed: September 9, 2010
    Publication date: July 26, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hirokazu Ueda, Yusuke Ohsawa, Masahiro Horigome
  • Patent number: 8227028
    Abstract: A method of forming on a substrate an amorphous silica-based coating film having a low dielectric constant of 3.0 or below and a film strength (Young's modulus) of 3.0 GPa or more, which comprises, as a typical one, the steps of; (a) coating on the substrate a liquid composition containing hydrolysate of an organic silicon compound or compounds hydrolyzed in the presence of tetraalkylammonium hydroxide (TAAOH); (b) setting the substrate in a chamber and then drying a coating film formed on the substrate at a temperature in the range from 25 to 340° C.; (c) heating the coating film at a temperature in the range from 105 to 450° C. with introduction of a superheated steam having such a temperature into the chamber, and (d) curing the coating film at a temperature in the range from 350 to 450° C. with introduction of a nitrogen gas into the chamber.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: July 24, 2012
    Assignee: JGC Catalysts and Chemicals Ltd.
    Inventors: Miki Egami, Akira Nakashima, Michio Komatsu
  • Patent number: 8225738
    Abstract: A resist coating method supplies a resist solution to substantially the center of a target substrate to be processed while rotating the target substrate at a first rotational speed, then reduces a rotational speed of the target substrate to a second rotational speed lower than the first rotational speed, reduces the rotational speed of the target substrate to a third rotational speed lower than the second rotational speed or until rotational halt to adjust the film thickness of the resist solution, and accelerates the rotation of the target substrate to a fourth rotational speed higher than the third rotational speed to spin off a residue of the resist solution.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: July 24, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kousuke Yoshihara, Tomohiro Iseki
  • Patent number: 8222157
    Abstract: A device for inductively confining capacitively coupled RF plasma formed in a plasma processing apparatus. The apparatus includes an upper electrode and a lower electrode that is adapted to support a substrate and to generate the plasma between the substrate and the upper electrode. The device includes a dielectric support ring that concentrically surrounds the upper electrode and a plurality of coil units mounted on the dielectric support ring. Each coil unit includes a ferromagnetic core positioned along a radial direction of the dielectric support ring and at least one coil wound around each ferromagnetic core. The coil units generate, upon receiving RF power from an RF power source, electric and magnetic fields that reduce the number of charged particles of the plasma diffusing away from the plasma.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 17, 2012
    Assignee: Lam Research Corporation
    Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andreas Fischer
  • Patent number: 8222161
    Abstract: Substrate processing of a substrate is performed in a processing chamber and the evenness in in-plane film thickness is enhanced. An exhaust unit exhausts the atmosphere in the processing chamber and a processing gas is supplied that is excited by an exciting unit. A rotational drive unit horizontally rotates a support unit that supports a mounting substrate on which the substrate is mounted; and a coolant supply/discharge unit is connected to the lower end of the support unit through a connecting unit. The substrate mounting unit has a coolant circulation path therein. The support unit includes a first coolant flow path for passing coolant through the coolant circulation path. The coolant supply/discharge unit includes a second coolant flow path. The connecting unit connects the first coolant flow path and the second coolant flow path together and is provided outside the processing chamber.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: July 17, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshihiko Yanagisawa, Mitsuro Tanabe, Harunobu Sakuma, Tadashi Takasaki
  • Patent number: 8222162
    Abstract: A batch processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 17, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Okada, Yukio Tojo
  • Publication number: 20120175790
    Abstract: A composition for a patternable adhesive film, a patternable adhesive film having the same, and a method of manufacturing a semiconductor package using the patternable adhesive film are provided. The composition contains a binder resin, a radical-polymerizable acrylate monomer, a photo-radical initiator, and a thermal-radical initiator without an epoxy resin. The composition may have good patternability, adhesiveness, and low-temperature stability, and be rapidly cured at a low temperature.
    Type: Application
    Filed: August 5, 2011
    Publication date: July 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Seok HAN, Joon Yong PARK, Jae Jun LEE, Chul Ho JEONG
  • Patent number: 8216486
    Abstract: A temperature control module for a semiconductor processing chamber comprises a thermally conductive component body, one or more channels in the component body and one or more tubes concentric therewith, such that gas filled spaces surround the tubes. By flowing a heat transfer liquid in the tubes and adjusting the gas pressure in the spaces, localized temperature of the component body can be precisely controlled. One or more heating elements can be arranged in each zone and a heat transfer liquid can be passed through the tubes to effect heating or cooling of each zone by activating the heating elements and/or varying pressure of the gas in the spaces.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 10, 2012
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Henry Povolny, Jerry K. Antolik
  • Publication number: 20120168940
    Abstract: Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.
    Type: Application
    Filed: October 14, 2010
    Publication date: July 5, 2012
    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Florian Bieck
  • Publication number: 20120171873
    Abstract: According to an example embodiment, a thin film transistor (TFT) printing apparatus includes a stage having a TFT substrate loaded thereon, a stage moving device configured to move the stage according to a printing vector set to correspond to a print pattern, and a print head on an upper side of the stage and including a plurality of nozzles in a matrix shape.
    Type: Application
    Filed: July 11, 2011
    Publication date: July 5, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-woo Chung, Young-ki Hong
  • Publication number: 20120171870
    Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.
    Type: Application
    Filed: December 21, 2011
    Publication date: July 5, 2012
    Applicant: VEECO INSTRUMENTS INC.
    Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
  • Publication number: 20120164841
    Abstract: An apparatus and method for combinatorial non-contact wet processing of a liquid material may include a source of a liquid material, a first reaction cell, a second reaction cell, a first plurality of gas jets disposed within an interior of the first reaction cell, the first plurality of gas jets configured to atomize the liquid material transferred to the interior of the first reaction cell, a second plurality of gas jets disposed within an interior of the second reaction cell, the second plurality of gas jets configured to atomize the liquid material transferred to the interior of the second reaction cell, a first vacuum element disposed along a periphery of the first reaction cell, and a second vacuum element disposed along a periphery of the at least a second reaction cell.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventor: Rajesh Kelekar
  • Publication number: 20120156884
    Abstract: Disclosed is a film forming method of an amorphous carbon film, including: disposing a substrate in a processing chamber; supplying a processing gas containing carbon, hydrogen and oxygen into the processing chamber; and decomposing the processing gas by heating the substrate in the processing chamber and depositing the amorphous carbon film on the substrate.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Nozawa, Hiraku Ishikawa
  • Publication number: 20120156877
    Abstract: A top assembly for a processing chamber having a back plate and a hub is provided. The back plate has a first portion and a second portion. The first portion is connected to the second portion through a central region of the back plate, wherein a gap is defined between opposing surfaces of the first and second portions outside the central region. The first portion includes an embedded heating element. The hub is affixed to a top surface of the second portion of the back plate over the central region. The hub has a top surface with a plurality of channel openings defined within a central region of the hub and a bottom surface having a central extension with a plurality of channels defined therethrough. The bottom surface includes an annular extension spaced apart from the central extension.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Lipyeow Yap, Jay DeDontney, Shouqian Shao, Jason Wright
  • Publication number: 20120149210
    Abstract: A system for processing substrates is described. In one embodiment, the system comprises a process chamber and at least one Coanda effect gas injector. The at least one Coanda effect gas injector is disposed proximate a location for the peripheral edge of the substrate so as to provide a Coanda effect gas flow over the surface of the substrate. Apparatuses and methods are also described.
    Type: Application
    Filed: July 30, 2011
    Publication date: June 14, 2012
    Inventors: Ronald L. COLVIN, Dennis GOODWIN, SR., Jeff MITTENDORF, Charles J. MORETTI, John W. ROSE, Earl Blake SAMUELS
  • Publication number: 20120149211
    Abstract: According to one embodiment, a pattern formation method includes, before forming a circuit pattern on a substrate using imprinting, a wall pattern with a predetermined height is formed to surround the periphery of an area serving as imprint shots on the substrate in each imprint shot and to allow the imprint shots to be separated from one another. The circuit pattern is formed in the imprint shots surrounded by the wall pattern through imprinting.
    Type: Application
    Filed: September 15, 2011
    Publication date: June 14, 2012
    Inventor: Tomoko OJIMA