Abstract: A combinatorial processing method is provided. The combinatorial processing method includes providing a flow of fluid over segregated sectors of a substrate to process the segregated sectors of the substrate in parallel without significantly exposing any section to a reagent without first applying a film and without subjecting any section to the same process step at the same time. Differently processed, segregated sectors may be generated in parallel.

Abstract: There are disclosed an epitaxial film, comprising: heating an Si substrate provided with an SiO2 layer with a film thickness of 1.0 nm or more to 10 nm or less on a surface of the substrate; and forming on the SiO2 layer by use of a metal target represented by the following composition formula: yA(1?y)B??(1), in which A is one or more elements selected from the group consisting of rare earth elements including Y and Sc, B is Zr, and y is a numeric value of 0.03 or more to 0.20 or less, the epitaxial film represented by the following composition formula: xA2O3?(1?x)BO2??(2), in which A and B are respectively same elements as A and B of the composition formula (1), and x is a numeric value of 0.010 or more to 0.035 or less.

Abstract: A processing assembly for a semiconductor workpiece generally includes a rotor assembly capable of spinning a workpiece, a chemistry delivery assembly for delivering chemistry to the workpiece, and a chemistry collection assembly for collecting spent chemistry from the workpiece. The chemistry collection assembly includes a weir assembly surrounding the rotor assembly and having a plurality of weirs. Methods for processing a semiconductor workpiece generally include moving at least one of the rotor assembly and the weir assembly.

Abstract: A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.

Abstract: A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

Abstract: Provided are gas distribution plates (showerheads) for use in an apparatus configured to form a film during, for example, an atomic layer deposition (ALD) process. The gas distribution plate comprises a body defining a thickness and a peripheral edge and has a front surface for facing the substrate. The front surface has a central region with a plurality of openings configured to distribute process gases over the substrate and a focus ring with a sloped region. The focus ring is concentric to the central region such that the thickness at the focus ring is greater than the thickness at the central region.

Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.

Abstract: Methods for the fabrication of nanostructures, including nanostructures comprised of carbon nanotubes, and the nanostructures, devices, and assemblies prepared by these methods, are described.

Abstract: A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.

Abstract: The substrate processing apparatus includes: a processing chamber for storing and processing substrates stacked in multiple stages in horizontal posture; at least one processing gas supply nozzle which extends running along an inner wall of the processing chamber in the stacking direction of the substrates and supplies a processing gas to the inside of the processing chamber; a pair of inactive gas supply nozzles which are provided so as to extend running along the inner wall of the processing chamber in the stacking direction of the substrates and so as to sandwich the processing gas supply nozzle from both sides thereof along the circumferential direction of the substrates and which supply the inactive gas to the inside of the processing chamber; and an exhaust line for exhausting the inside of the processing chamber.

Abstract: The invention relates to a device for pulsed laser deposition, which device comprises: a substrate mount with a substrate mounted thereon; a target mount with a target material mounted thereon and opposite of the substrate mount; a laser device for directing a laser beam on the target material; and a shadow mask arranged over the substrate; wherein the shadow mask is arranged in a movable disc, which movable disc is movable in axial direction to and from the substrate mount. The invention also relates to a method for operating such a device.

Abstract: A method of fabricating a device is disclosed. The method comprises coating a solid structure by nanostructures selected from the group consisting of peptides and amino acids, under conditions that at least partially prevent assembly of the nanostructures into supramolecular structures.

Abstract: In one embodiment, a method of removing film materials on an edge area of a substrate in a plasma etching apparatus is disclosed. The apparatus includes a chamber, a substrate support, a shield disposed with a gap on the substrate such that plasma is not generated therein while allowing an edge portion of the substrate to be exposed, and an antenna disposed on an outer wall of the chamber to apply plasma-generating power to an area between the edge portion of the substrate and an inner wall of the chamber. The method includes spraying a curtain gas to a space between the shield and the substrate, using a curtain gas passageway; and spraying a reaction gas to an area between a side surface of the shield and an inner sidewall of the chamber formed within the shield, using a reaction gas supply passageway.

Abstract: A substrate processing method that can eliminate unevenness in the distribution of plasma. The method is for a substrate processing apparatus that has a processing chamber in which a substrate is housed, a mounting stage that is disposed in the processing chamber and on which the substrate is mounted, and an electrode plate that is disposed in the processing chamber such as to face the mounting stage, the electrode plate being made of silicon and connected to a radio-frequency power source, and carries out plasma processing on the substrate. In the plasma processing, the temperature of the electrode plate is measured, and based on the measured temperature, the temperature of the electrode plate is maintained lower than a critical temperature at which the specific resistance value of the silicon starts changing.

Abstract: A manufacturing method for a semiconductor device, that loads a substrate on which a film containing oxygen atoms, chlorine atoms, and metal atoms is formed into a processing chamber so as to be supported by a substrate support part. The substrate is heated by the substrate support part. The inside of the processing chamber is exhausted by a gas exhaust part while supplying nitrogen atoms-containing gas and hydorgen atoms-containing gas into the processing chamber by a gas supply part. A plasma generation part is then used to excite the nitrogen atoms-containing gas and the hydrogen atoms-containing gas supplied into the processing chamber.

Abstract: A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer.

Abstract: Stagnation of gas used for substrate processing in an exhaust trap is prevented, and localized precipitation of components in the gas used for substrate processing is reduced.

Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.

Abstract: A stabilized cyclic alkene composition comprising one or more cyclic alkenes, and at least one stabilizer compound having the Formula (I), R1,R2,R3,R4,R5(C6)OH??Formula (I) wherein R? through R5 can each independently be H, OH, C1-C8 linear, branched, or cyclic alkyl, C1-C8 linear, branched, or cyclic alkoxy or substituted or unsubstituted aryl, and wherein the stabilizer compound is present in an amount greater than 200 ppm up to 20,000 ppm and has a boiling point lower than 265° C. A method for forming a layer of carbon-doped silicon oxide on a substrate, which uses the stabilized alkene composition and a silicon containing compound.

Abstract: There are provided methods for functionalizing a planar surface of a microelectronic structure, by exposing the surface to at least one vapor including at least one functionalization species, such as NO2 or CH3ONO, that non-covalently bonds to the surface while providing a functionalization layer of chemically functional groups, to produce a functionalized surface. The functionalized surface is exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the planar microelectronic surface while providing chemically functional groups. The stabilized surface is exposed to at least one material layer precursor species that deposits a material layer on the stabilized planar microelectronic surface. The stabilized planar microelectronic surface can be annealed at a peak annealing temperature that is less than about 700° C.

Abstract: Methods for deposition of elemental metal films on surfaces using metal coordination complexes comprising bisamineazaallylic ligands are provided. Also provided are bisamineazaallylic ligands useful in the methods of the invention and metal coordination complexes comprising these ligands.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: Wafer-based solar cells are efficiently produced by extruding a dopant bearing material (dopant ink) onto one or more predetermined surface areas of a semiconductor wafer, and then thermally treating the wafer to cause diffusion of dopant from the dopant ink into the wafer to form corresponding doped regions. A multi-plenum extrusion head is used to simultaneously extrude interdigitated dopant ink structures having two different dopant types (e.g., n-type dopant ink and p-type dopant ink) in a self-registered arrangement on the wafer surface. The extrusion head is fabricated by laminating multiple sheets of micro-machined silicon that define one or more ink flow passages. A non-doping or lightly doped ink is co-extruded with heavy doped ink to serve as a spacer or barrier, and optionally forms a cap that entirely covers the heavy doped ink. A hybrid thermal treatment utilizes a gaseous dopant to simultaneously dope exposed portions of the wafer.

Abstract: There is disclosed a wafer processing apparatus having optimized electrode patterns for its resistive heating element. The optimized electrode pattern is designed to compensate for the heat loss around contact areas, electrical connections, and through-holes, etc., by generating more heat near or around those areas, providing maximum temperature uniformity. In another embodiment of the optimized design of the invention, the resistance of heating element closely matches the impedance of the power supply for higher efficiency, especially when higher operating temperature or higher electrical power is required.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is has in its backbone, side chains, or both backbone and side chains, multiple secondary or tertiary amide groups that are represented by the following acetamide structure: >N—C(?O)—. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.

Abstract: Disclosed is a substrate processing apparatus including: a processing chamber; plural buffer chambers; a first processing gas supply system that supplies a first processing gas to the processing chamber; a second processing gas supply system that supplies a second processing gas to the buffer chambers; a RF power source; plasma-generating electrodes in the buffer chambers; a heating system; and a controller that controls the first and second processing gas supply systems, the power source, and the heating system to expose the substrate having a metal film thereon to the first processing gas, and the second processing gas that is activated in the plural buffer chambers with an application of RF power to the electrodes and that is supplied from the buffer chambers to the processing chamber to form a film on the metal film while heating the substrate to a self-decomposition temperature of the first processing gas or lower.

Abstract: In one example, we describe a new high performance AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET), which was fabricated using HfO2 as the surface passivation and gate insulator. The gate and drain leakage currents are drastically reduced to tens of nA, before breakdown. Without field plates, for 10 ?m of gate-drain spacing, the off-state breakdown voltage is 1035V with a specific on-resistance of 0.9 m?-cm2. In addition, there is no current slump observed from the pulse measurements. This is the best performance reported on GaN-based, fast power-switching devices on sapphire, up to now, which efficiently combines excellent device forward, reverse, and switching characteristics. Other variations, features, and examples are also mentioned here.

Abstract: The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.

Abstract: In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.

Abstract: Some embodiments include methods of forming metal-containing structures. A first metal-containing material may be formed over a substrate. After the first metal-containing material is formed, and while the substrate is within a reaction chamber, hydrogen-containing reactant may be used to form a hydrogen-containing layer over the first metal-containing material. The hydrogen-containing reactant may be, for example, formic acid and/or formaldehyde. Any unreacted hydrogen-containing reactant may be purged from within the reaction chamber, and then metal-containing precursor may be flowed into the reaction chamber. The hydrogen-containing layer may be used during conversion of the metal-containing precursor into a second metal-containing material that forms directly against the first metal-containing material. Some embodiments include methods of forming germanium-containing structures, such as, for example, methods of forming phase change materials containing germanium, antimony and tellurium.

Abstract: A method of film deposition using localized plasma to protect bevel edge of a wafer in a plasma chamber. The method includes adjusting an electrode gap between a movable electrode and a stationary electrode, the wafer being disposed on one of the movable electrode and the stationary electrode, to a gap distance configured to prevent plasma formation over a center portion of the wafer, the gap distance also dimensioned such that a plasma-sustainable condition around the bevel edge of the wafer is formed after the adjusting. The method also includes flowing deposition gas into the plasma chamber. The method includes maintaining, using a heater, a chuck temperature that is configured to facilitate film deposition on the bevel edge. The method further includes generating the localized plasma from the deposition gas for depositing a film on the bevel edge.

Abstract: Certain example embodiments of this invention relate to methods of treating the surface of a soda lime silica glass substrate, e.g., a soda lime silica alkali ion glass substrate, and the resulting surface-treated glass articles. More particularly, certain example embodiments of this invention relate to methods of removing a top surface portion of a glass substrate using ion sources. During or after removal of this portion, the glass may then be coated with another layer, to be used as a capping layer. In certain example embodiments, the glass substrate coated with a capping layer may be used as a color filter and/or TFT substrate in an electronic device. In other example embodiments, the glass substrate with the capping layer thereon may be used in a variety of display devices.

Abstract: The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-1 and an MP wafer group-2. At least one of the MP wafers of the MP wafer group-1 is processed with a second process step-1 and at least one of the MP wafers of the MP wafer group-2 is processed with a second process step-2 to form different device components on the MP wafers of the MP wafer group-1 and group-2, respectively. At least one of the MP wafers of the MP wafer group-1 is processed with a third process step-3 and at least one of the MP wafers of the MP wafer group-2 is processed with a third process step-4 to form a substantially same device component on the MP wafers.

Abstract: The present invention provides a method of forming a self-assembly fullerene array on the surface of a substrate, comprising the following steps: (1) providing a substrate; (2) pre-annealing the substrate at a temperature ranging from 200° C. to 1200° C. in a vacuum system; and (3) providing powdered fullerene nanoparticles and depositing them on the surface of the substrate by means of physical vapor deposition technology in the vacuum system, so as to form a self-assembly fullerene array on the surface of the substrate. The present invention also provides a fullerene embedded substrate prepared therefrom, which has excellent field emission properties and can be used as a field emitter for any field emission displays. Finally, the present invention provides a fullerene embedded substrate prepared therefrom, which can be used to substitute for semiconductor carbides as optoelectronic devices and high-temperature, high-power, or high-frequency electric devices.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: A method for batch brazing jet stacks in a diffusion furnace. The method may include inserting fusible parts into slots of quartz boats and transporting the quartz boats into an interior of a reaction chamber of a diffusion furnace. An operator may seal the interior of the reaction chamber and an atmosphere of the interior of the reaction chamber may be adjusted according to a brazing recipe. A preheated furnace heating element may be moved toward the reaction chamber to increase a temperature and the fusible parts may be brazed according to the brazing recipe. The furnace heating element may then be moved away from the reaction chamber, the chamber unsealed, and the brazed parts removed.

Abstract: An oxidation method for performing direct oxidation includes respectively supplying an oxidizing gas and a deoxidizing gas to the process field, and directly oxidizing a surface target substrates by use of oxygen radicals and hydroxyl group radicals generated by a reaction between the oxidizing gas and the deoxidizing gas. The oxidizing gas is supplied through an oxidizing gas nozzle extending over a vertical length corresponding to the process field and is spouted from a plurality of gas spouting holes formed on the oxidizing gas nozzle and arrayed over the vertical length corresponding to the process field. The deoxidizing gas is supplied through a plurality of deoxidizing gas nozzles having different heights respectively corresponding to a plurality of zones of the process field arrayed vertically and is spouted from gas spouting holes respectively formed on the deoxidizing gas nozzles each at height of a corresponding zone.

Abstract: Disclosed is a method for manufacturing a semiconductor light-receiving device having high reproducibility and reliability. Specifically disclosed is a semiconductor light-receiving device 100 with a mesa structure wherein a light-absorbing layer 6, an avalanche multiplication layer 4 and an electric-field relaxation layer 5 are formed on a semiconductor substrate 2. The light-absorbing layer 6, avalanche multiplication layer 4 and electric-field relaxation layer 5 exposed in the side wall of the mesa structure are protected by an SiNx film or an SiOyNz film. The hydrogen concentration in the side wall surface of the electric-field relaxation layer 5 is set at not more than 15%, preferably not more than 10% of the carrier concentration of the electric-field relaxation layer 5.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: A process of manufacturing a semiconductor device may be simplified, and oxidation of a metal element-containing film may be suppressed. The method of manufacturing a semiconductor device includes loading a substrate including a metal element-containing film and an insulating film formed on the metal element-containing film into a process chamber and supporting the substrate using a substrate support installed in the process chamber; supplying a reactive gas including at least one of hydrogen in excited state and nitrogen in excited state, and oxygen in excited state onto the substrate in the process chamber and processing the substrate; and unloading the substrate from an inside of the process chamber.

Abstract: A vaporizing and feed apparatus for vaporizing and feeding a solid film-forming raw material comprises a supercritical fluid feeding part for producing and feeding a supercritical fluid, a supercritical fluid adjusting part for dissolving the solid film-forming raw material in the supercritical fluid by bringing the supercritical fluid fed from the supercritical fluid feeding part into contact with the solid film-forming raw material, and a vaporizing part for phase-transitioning the supercritical fluid having the dissolved solid film-forming raw material to a gas, the solid film-forming raw material thereby being deposited in the gas, and for vaporizing the deposited solid film-forming raw material.

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

Abstract: A manufacturing apparatus for a semiconductor device, comprising: a reactor chamber configured to load a wafer therein; a gas supplying mechanism configured to supply a process gas into the reactor chamber; a gas discharging mechanism configured to discharge a gas from the reactor chamber; a wafer supporting member configured to mount the wafer thereon; a ring configured to mount the wafer supporting member thereon; a rotary drive controlling mechanism configured to connect to the ring for rotating the wafer; a heater arranged in the ring for heating the wafer to a predetermined temperature; an electrode part configured to connect to the heater and including a screw concave portion; and an electrode including a screw portion which is connected to the electrode part via the screw concave portion.

Abstract: A holding device adapted for holding a mask and a substrate during processing is described. The holding device includes a substrate carrier adapted for carrying the substrate; and a mask for masking the substrate, wherein the mask is releasably connected to the substrate carrier; wherein the substrate carrier or the mask has at least one recess adapted for receiving a cover for covering the substrate carrier during deposition.

Abstract: An apparatus for electrostatic chucking and dechucking of a semiconductor wafer includes an electrostatic chuck with a number of zones. Each zone includes one or more polar regions around a lift pin that contacts a bottom surface of the semiconductor wafer. The apparatus also includes one or more controllers that control the lift pins and one or more controllers that control the polar regions. The controller for the lift pins receives data from one or more sensors and uses the data to adjust the upward force of the lift pins. Likewise, the controller for the polar regions receives data from the sensors and uses the data to adjust the voltage in the polar regions.

Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.

Abstract: Disclosed is a technology in which a nozzle part is mounted in a vacuum chamber and a silicon substrate is held to face a discharge hole of the nozzle part. For example, ClF3 gas and Ar gas are supplied from the nozzle part and the mixed gas is discharged from the nozzle part under a vacuum atmosphere. By doing this, the mixed gas is adiabatically expanded and the Ar atoms or ClF3 molecules are combined, which become a gas cluster. The gas cluster is irradiated to the surface of the silicon substrate without being ionized and, as a result, the surface of the silicon surface becomes a porous state. Then, lithium is grown on the surface of the silicon substrate in a separate vacuum chamber 41 by sputtering without breaking the vacuum.

Abstract: A manufacturing method of a structure by an imprint process includes a first imprint step of forming a first resin material layer by applying a first resin material onto a substrate and then transferring an imprint pattern of a mold onto the first resin material layer, a second imprint step of forming a second resin material layer by applying a second resin material onto the first resin material layer formed in the first imprint step and onto an area of the substrate adjacent to the first resin material layer and then transferring the imprint pattern of the mold onto the second resin material layer, and a step of forming a pattern by etching the first and second resin material layers.