Abstract: A system for sealing a processing zone in a chemical deposition apparatus is disclosed, which includes a chemical isolation chamber having a deposition chamber formed within the chemical isolation chamber; a showerhead module having a faceplate, the showerhead module including a plurality of inlets which deliver reactor chemistries to a cavity for processing semiconductor substrates and exhaust outlets which remove reactor chemistries and inert gases from the cavity, and an outer plenum configured to deliver an inert gas; a pedestal module configured to support a substrate and which moves vertically to close the cavity with a narrow gap between the pedestal module and a step around an outer portion of the faceplate; and an inert seal gas feed configured to feed the inert seal gas into the outer plenum, and wherein the inert seal gas flows radially inwardly at least partly through the narrow gap to form a gas seal.

Abstract: An electrically conductive polymer linked to conductive nanoparticle is provided. The conductive polymer can include conductive monomers and one or more monomers in the conductive polymer can be linked to a conductive nanoparticle and can include a polymerizable moiety so that it can be incorporated into a polymer chain. The electrically conductive monomer can include a 3,4-ethylenedioxythiophene as a conductive monomer. The electrically conductive polymer having the conductive nanoparticle can be prepared into an electrically conductive layer or film for use in electronic devices.

Abstract: The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another.

Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.

Abstract: Various embodiments provide ground shield structures, semiconductor devices, and methods for forming the same. An exemplary structure can include a substrate and a dielectric layer disposed on the substrate. The structure can further include multiple conductive rings disposed in the substrate, in the dielectric layer, and/or on the dielectric layer. Each conductive ring of the multiple conductive rings can have openings of about three or more, and the openings of the each conductive ring can divide the multiple conductive rings into a plurality of sub-conductive rings arranged spaced apart. The structure can further a ground ring electrically connected to each of the plurality of sub-conductive rings.

Abstract: An improved technique achieves a uniform photoresist film on a wafer by controlling the volatility of the solvent in a photoresist solution during the bake process step. Because film formation takes place in the bake rather than the spin steps of the process, the improved technique involves using less viscous and therefore less costly and easier to use resists to cast relatively thick photoresist films. Such control is achieved in an enclosed chamber into which a carrier gas is introduced; the carrier gas mixes with gaseous solvent to create a saturating atmosphere in which the rate of evaporation of solvent decreases. This enables the heating of the wafer without the reduction of solvent in the film so that the photoresist can self-level. When the film has self-leveled, the solvent is then baked off as usual.

Abstract: According to one embodiment, a semiconductor manufacturing apparatus includes a substrate stage, a transfer unit, and a control unit. A substrate is settable on the substrate stage. The transfer unit is configured to transfer a pattern having an uneven configuration onto a major surface of the substrate by attachably and removably holding a template. The pattern is provided in the transfer surface. The control unit is configured to acquire information relating to a number of foreign objects on the major surface prior to the transferring of the pattern. The control unit adds the number for a plurality of the substrates including the pattern transferred by the transfer unit. The control unit causes the transfer unit not to implement the transferring of the pattern in the case where the sum has reached the upper limit.

Abstract: Disclosed is a substrate processing apparatus, including: a processing chamber for processing a substrate; a substrate rotating mechanism for rotating the substrate; a gas supply unit for supplying gas to the substrate, at least two kinds of gases A and B being alternately supplied a plurality of times to form a desired film on the substrate; and a controller for controlling a rotation period of the substrate or a gas supply period defined as a time period between an instant when the gas A is made to flow and an instant when the gas A is made to flow next time such that the rotation period and the gas supply period are not brought into synchronization with each other at least while the alternate gas supply is carried out predetermined times.

Abstract: A plating bath for electroless deposition of gold and gold alloy layers on such silicon-based substrates, includes Na(AuCl4) and/or other gold (III) chloride salts as a gold ion source. The bath is formed as a binary bath solution formed from mixing first and second bath components. The first bath component includes gold salts in concentrations up to 40 g/L, boric acid, in amounts of up to 30 g/L, and a metal hydroxide in amounts up to 20 g/L. The second bath component includes an acid salt, in amounts up to 25 g/L, sodium thiosulfate in amounts up to 30 g/L, and suitable acid, such as boric acid in amounts up to 20 g/L.

Abstract: An oxygen-containing gas and a hydrogen-containing gas are supplied into a pre-reaction chamber heated to a second temperature and having the pressure set to less than an atmospheric pressure, and a reaction is induced between both gases in the pre-reaction chamber to generate reactive species, and the reactive species are supplied into the process chamber and exhausted therefrom, in which a substrate heated to the first temperature is housed and the pressure is set to less than the atmospheric pressure, and processing is applied to the substrate by the reactive species, with the second temperature set to be not less than the first temperature at this time.

Abstract: A deposition apparatus includes a first nozzle configured to spray a first deposition material toward a substrate and a second nozzle configured to spray a second deposition material, a first deposition source configured to supply the first deposition material to the first nozzle and a second deposition source configured to supply the second deposition material to the second nozzle. The deposition apparatus further includes a barrier member disposed between the first nozzle and the second nozzle and is configured to block the first deposition material evaporated through the first nozzle from being mixed with the second deposition material evaporated through the second nozzle and a vacuum chamber configured to surround the first and second nozzles, the first and second deposition sources and the barrier member.

Abstract: A method of manufacturing a silicon-containing film includes a first step of drying cleaning a chamber with a fluorine-containing gas, a second step of loading a substrate into the chamber, a third step of purging the chamber with a silane-based gas, with the substrate being provided in the chamber, and a fourth step of forming the silicon-containing film on the substrate after the third step.

Abstract: A deposition device includes a deposition source for discharging a deposition material to be deposited on a substrate, an angle control member at least partly in a discharging path of the deposition material for controlling a discharging angle of the deposition material, and an angle control member driver coupled to the angle control member, the angle control member driver for moving the angle control member in a discharging direction of the deposition material to control the discharging angle.

Abstract: A method of manufacturing a semiconductor device by using a substrate processing apparatus comprises a reaction chamber configured to process a plurality of substrates stacked at predetermined intervals, wherein a first gas flow from a first gas supply inlet and a second gas flow from a second gas supply inlet are crossed with each other before these gas flows reach the substrates. The method of manufacturing a semiconductor device comprises: loading the plurality of substrates into the reaction chamber; supplying a silicon-containing gas and a chlorine-containing gas from the first gas supply inlet into the reaction chamber, supplying a carbon-containing gas and a reducing gas from the second gas supply inlet into the reaction chamber and supplying a dopant-containing gas into the reaction chamber from the first gas supply inlet or the second gas supply inlet; and unloading the substrates from the reaction chamber.

Abstract: Various embodiments relate to application of a fluid to a substrate. The fluid is locally heated, for example, to obtain a desired thickness profile.

Abstract: A component of a plasma processing chamber having a protective liquid layer on a plasma exposed surface of the component. The protective liquid layer can be replenished by supplying a liquid to a liquid channel and delivering the liquid through liquid feed passages in the component. The component can be an edge ring which surrounds a semiconductor substrate supported on a substrate support in a plasma processing apparatus wherein plasma is generated and used to process the semiconductor substrate. Alternatively, the protective liquid layer can be cured or cooled sufficiently to form a solid protective layer.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, on one main surface of the substrate, a detection film having a light transmittance different from that of silicon carbide; confirming presence of the substrate by applying light to the detection film; and forming an active region in the substrate whose presence has been confirmed.

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.

Abstract: A semiconductor wafer spinning chuck includes a rotatable base, a plurality of arms, upstanding from the base, a selectively releasable clamping mechanism, associated with the arms, and a spray nozzle, extending through the base. The clamping mechanism has a first portion configured to mechanically clamp an edge of a first semiconductor wafer and hold the first wafer in a substantially horizontal orientation upon all of the arms, with a backside of the first wafer facing down. The spray nozzle is oriented to direct a spray of fluid at the backside of the first wafer.

Abstract: Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n?2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as copper. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic.

Abstract: A cold spray barrier coated component of a semiconductor plasma processing chamber comprises a substrate having at least one metal surface wherein a portion of the metal surface is configured to form an electrical contact. A cold spray barrier coating is formed from a thermally and electrically conductive material on at least the metal surface configured to form the electrical contact of the substrate. Further, the cold spray barrier coating may also be located on a plasma exposed and/or process gas exposed surface of the component.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: A coating film (90) is formed by causing vapor deposition particles (91) to pass through a mask opening (71) of a vapor deposition mask and adhere to a substrate, the vapor deposition particles (91) being discharged from a vapor deposition source opening (61) of a vapor deposition source (60) while the substrate (10) is moved relative to the vapor deposition mask (70) in a state in which the substrate (10) and the vapor deposition mask (70) are spaced apart at a fixed interval. When a direction that is orthogonal to a normal line direction of the substrate and is orthogonal to a relative movement direction of the substrate is defined as a first direction, and the normal line direction of the substrate is defined as a second direction, a plurality of control plate columns are disposed in the first direction between the vapor deposition source opening and the vapor deposition mask, each control plate column including a plurality of control plates (80a and 80b) arranged along the second direction.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: A method for protecting an exposed low-k surface is described. The method includes providing a substrate having a low-k insulation layer formed thereon and one or more mask layers overlying the low-k insulation layer with a pattern formed therein. Additionally, the method includes transferring the pattern in the one or more mask layers to the low-k insulation layer using one or more etching processes to form a trench and/or via structure in the low-k insulation layer. The method further includes forming an insulation protection layer on exposed surfaces of the trench and/or via structure during and/or following the one or more etching processes by exposing the substrate to a film forming compound containing C, H, and N. Thereafter, the method includes removing at least a portion of the one or more mask layers using a mask removal process.

Abstract: A particle reducing method includes a step of supplying a first gas to a vacuum chamber in which a susceptor, formed by an insulating object and the surface of which is provided with a substrate mounting portion, is rotatably provided; a step of generating plasma from the first gas by supplying high frequency waves to a plasma generating device provided for the vacuum chamber; and a step of exposing the substrate mounting portion, on which a substrate is not mounted, to the plasma while rotating the susceptor.

Abstract: A substrate treating apparatus includes a plurality of substrate treatment lines arranged vertically. Each substrate treatment line has a plurality of main transport mechanisms arranged horizontally, and a plurality of treating units provided for each main transport mechanism for treating substrates. A series of treatments is carried out for the substrates, with each main transport mechanism transporting the substrates to the treating units associated therewith, and transferring the substrates to the other main transport mechanism horizontally adjacent thereto. The substrate treating apparatus realizes increased processing capabilities by treating the substrates in parallel through the substrate treatment lines.

Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.

Abstract: A method of forming a dense oxide coating on an aluminum component of semiconductor processing equipment comprises cold spraying a layer of pure aluminum on a surface of the aluminum component to a predetermined thickness. A dense oxide coating is then formed on the layer of pure aluminum using a plasma electrolytic oxidation process, wherein the plasma electrolytic oxidation process causes the layer of pure aluminum to undergo microplasmic discharges, thus forming the dense oxide coating on the layer of pure aluminum on the surface of the aluminum component.

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: A manufacturing method for a semiconductor device, comprising: performing first processing on a plurality of wafers in a first processing order in a first processing apparatus; obtaining a processed amount with respect to each of the plurality of wafers in the first processing; obtaining a processed amount with respect to each of the plurality of wafers by second processing in a second processing apparatus after the first processing; deciding a second processing order, which is different from the first processing order, from the processed amount with respect to each of the plurality of wafers by the first processing and the processed amount with respect to each of the plurality of wafers by the second processing; and performing the second processing on the plurality of wafers in the second processing order in the second processing apparatus.

Abstract: Embodiments provided herein describe systems and methods for processing substrates. A substrate having a plurality of site-isolated regions defined thereon is provided. A plurality of wet processes is simultaneously performed. Each of the plurality of wet processes is performed on one of the plurality of site-isolated regions defined on the substrate. The simultaneously performing includes exposing each of the plurality of site-isolated regions to one of a plurality of wet processing formulations. Each of the plurality of wet processing formulations includes a component. The respective component is added to at least some of the plurality of wet processing formulations during the exposing. A processing condition is varied between at least two of the plurality of wet processes in a combinatorial manner.

Abstract: This disclosure relates to a plasma processing system for controlling plasma density near the edge or perimeter of a substrate that is being processed. The plasma processing system may include a plasma chamber that can receive and process the substrate using plasma for etching the substrate, doping the substrate, or depositing a film on the substrate. This disclosure relates to a plasma processing system for controlling plasma density near the edge or perimeter of a substrate that is being processed. In one embodiment, the plasma density may be controlled by reducing the rate of loss of ions to the chamber wall during processing. This may include biasing a dual electrode ring assembly in the plasma chamber to alter the potential difference between the chamber wall region and the bulk plasma region.

Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a polymer resin which has repeating units within it. At least one of the repeating units comprises a locked unit which has a cyclic structure and a lock within the unit. After the anti-reflective layer has been applied and baked, irregularities such as voids and step heights differences that have occurred may be handled by unlocking the lock within the locked unit. This unlocking breaks the cyclic structure, allowing the polymer to take up more volume and causing the anti-reflective layer to self-expand, filling the voids and reducing the step-height. The unlocking may be performed by exposure or thermal treatments.

Abstract: Components of semiconductor material processing chambers are disclosed, which may include a substrate and at least one corrosion-resistant coating formed on a surface thereof. The at least one corrosion-resistant coating is a high purity metal coating formed by a cold-spray technique. An anodized layer can be formed on the high purity metal coating. The anodized layer comprises a process-exposed surface of the component. Semiconductor material processing apparatuses including one or more of the components are also disclosed, the components being selected from the group consisting of a chamber liner, an electrostatic chuck, a focus ring, a chamber wall, an edge ring, a plasma confinement ring, a substrate support, a baffle, a gas distribution plate, a gas distribution ring, a gas nozzle, a heating element, a plasma screen, a transport mechanism, a gas supply system, a lift mechanism, a load lock, a door mechanism, a robotic arm and a fastener.

Abstract: A method for processing a substrate includes providing a set of patterned structures separated by a first gap on the substrate and directing first implanting ions to the substrate at a first ion energy, where the first implanting ions are effective to impact the substrate in regions defined by the first gap. The method also includes directing depositing ions to the substrate where the second ions are effective to deposit material on at least a portion of the set of patterned structures to form expanded patterned structures, where the expanded patterned structures are characterized by a second gap smaller than the first gap. The method further includes directing second implanting ions to the substrate at a second ion energy, where the second implanting ions effective to impact the substrate in regions defined by the second gap, the second ion energy comprising a higher ion energy than the first ion energy.

Abstract: A method of depositing an epitaxial layer on a silicon wafer is described. The silicon wafer has a diameter, and is disposed within a processing chamber within a deposition system. The method includes the steps of introducing a process gas into the system from a gas injecting port, flowing the process gas through a gas distribution plate in fluid communication with the gas injecting port and the processing chamber, the gas distribution plate including an inner array of holes and an outer array of holes, and controlling the gas flow distribution across the substrate surface. The controlling step includes selecting at least one orifice-containing plug to be secured within a hole in the gas distribution plate, and securing the selected plug within the hole.

Abstract: An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.

Abstract: A substrate processing chamber comprising a chamber wall enclosing a process zone having an exhaust port, a substrate support to support a substrate in the process zone, a gas distributor for providing a deposition gas to the process zone, a solid state light source capable of irradiating substantially the entire surface of the substrate with light, and a gas energizer for energizing the deposition gas.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film having a borazine ring skeleton and containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a precursor gas containing the predetermined element and a halogen element to the substrate; supplying a reaction gas including an organic borazine compound to the substrate; and supplying a carbon-containing gas to the substrate. In addition, the cycle is performed under a condition in which the borazine ring skeleton in the organic borazine compound is maintained.

Abstract: A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

Abstract: A substrate processing apparatus comprising: a processing chamber that can accommodate a plurality of substrates, the interior of which is divided into a plurality of zones; a gas supply system that supplies a first reactive gas, a second reactive gas, and an inert gas to each of the plurality of zones; and an exhaust system for removing the gas from the zones. A thin film is formed on the substrates in the zones by repeatedly executing a plurality of steps in relation to the zones, these steps include the following: a first reactive gas supply step; a first purge step; a second reactive gas supply step; and a second purge step. While the film is being formed, a control unit controls the gas supply system and the gas exhaust system so that the steps performed in the plurality of zones at the same time are different from one another.

Abstract: A cleaning method includes: providing a process container in which a process of forming a film on a substrate is performed; and removing a deposit including the film adhered to the process container by supplying a cleaning gas into the process container after performing the process. The act of removing the deposit includes generating a mixture gas of a fluorine-containing gas and a nitrosyl fluoride gas as the cleaning gas by mixture and reaction of the fluorine-containing gas and a nitrogen monoxide gas in a mixture part and supplying the mixture gas from the mixture part into the process container after removing exothermic energy generated by the reaction.

Abstract: An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.

Abstract: Described are methods and apparatuses for the stabilization of precursors, which can be used for the deposition of manganese-containing films. Certain methods and apparatus relate to lined ampoules and/or 2-electron donor ligands.

Abstract: A manufacturing apparatus for a semiconductor device, including: a reaction chamber configured to perform film formation on a wafer; a process gas supplying mechanism provided in an upper part of the reaction chamber and configured to introduce process gas to an interior of the reaction chamber; a gas discharging mechanism provided in a lower part of the reaction chamber and configured to discharge gas from the reaction chamber; a supporting member configured to hold the wafer; a cleaning gas supplying mechanism provided in an outer periphery of the supporting member and configured to emit cleaning gas in an outer periphery direction below an upper end of the supporting member; a heater configured to heat the wafer; and a rotary driving mechanism configured to rotate the wafer.

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.