Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Publication number: 20140235066
    Abstract: When a dry cleaning process is performed in a processing chamber by adding nitrogen monoxide (NO) gas to a cleaning gas, the handling is facilitated, and cleaning performance is improved. A substrate processing apparatus includes a processing vessel configured to process a substrate, a first cleaning gas supply system configured to pre-mix a gas containing fluorine atoms with the NO gas and supply the pre-mixed gas into the processing vessel, and a second cleaning gas supply system installed apart from the first cleaning gas supply system and configured to supply the fluorine-containing gas into the processing vessel.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Applicants: Hitachi Kokusai Electric Inc., L'Air Liquide Societe Anonyme Pour L'Etude Et L'Exploitation Des Procedes Georges Claude
    Inventors: Kenji KAMEDA, Jun SONOBE, Yudai TADAKI
  • Publication number: 20140235065
    Abstract: Disclosed is a semiconductor device manufacturing method that manufactures a semiconductor device having a resist pattern which is excellent in roughness property and line width property. The method includes forming a film which is elastic and incompatible with a resist patterned on an object to be processed to cover the surface of the resist, and heating the object to be processed formed with the film.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 21, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hidetami YAEGASHI, Kenichi OYAMA, Masatoshi YAMATO
  • Patent number: 8809201
    Abstract: The present invention provides; a method for forming a metal oxide film which has both a surface irregularity and a predetermined pattern or either and has few unevenness of surface specific resistance, light transmittance and the like, and such the metal oxide film. The method for forming a metal oxide film having both a surface irregularity and a predetermined pattern or either on a substrate, wherein, the method comprises a first process in which a liquid material containing a metal salt is applied on the substrate to form a metal salt film, a second process in which a surface irregularity or a predetermined pattern is formed to the metal salt film, and a third process in which the metal salt film is converted to a metal oxide film by thermal oxidation treatment or plasma oxidation treatment.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 19, 2014
    Assignee: Lintec Corporation
    Inventors: Satoshi Naganawa, Takeshi Kondo
  • Publication number: 20140220786
    Abstract: A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 7, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Todd Lukanc, Christopher Heinz Clifford, Tamer Coskun
  • Patent number: 8796081
    Abstract: A semiconductor structure is provided, comprising: a Si substrate; a porous structure layer formed on the Si substrate, in which the porous structure layer has a flat surface and comprises a Si1-xGex layer with low Ge content; and a Ge-containing layer formed on the porous structure layer, in which the Ge containing layer comprises a Ge layer or a Si1-yGey layer with high Ge content and x?y. Further, a method for forming the semiconductor structure is also provided.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: August 5, 2014
    Assignee: Tsinghua University
    Inventors: Jing Wang, Jun Xu, Lei Guo
  • Publication number: 20140213064
    Abstract: A semiconductor manufacturing apparatus according to the present embodiment comprises a chamber. A chemical-agent supply part is configured to supply a water-repellent agent or an organic solvent to a surface of a semiconductor substrate having been cleaned with a cleaning liquid in the chamber. A spray part is configured to spray a water-capture agent capturing water into an atmosphere in the chamber.
    Type: Application
    Filed: July 29, 2013
    Publication date: July 31, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiko KOIDE, Yoshihiro OGAWA, Masahiro KIYOTOSHI
  • Patent number: 8791030
    Abstract: In the present invention, a masking solution is supplied to an edge portion of a front surface of a substrate rotated around a vertical axis to form a masking film at the edge portion of the substrate, a hard mask solution is supplied to the front surface of the substrate to form a hard mask film on the front surface of the substrate, a hard mask film removing solution dissolving the hard mask film is supplied to the hard mask film formed at the edge portion of the substrate to remove the hard mask film formed at the edge portion of the substrate, and a masking film removing solution dissolving the masking film is supplied to the masking film to remove the masking film at the edge portion of the substrate.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: July 29, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Fumiko Iwao, Satoru Shimura, Kousuke Yoshihara
  • Patent number: 8791031
    Abstract: A method of manufacturing a semiconductor device includes: (a) supplying a first process gas from a first process gas supply unit into a process chamber via a flow rate control device to form a film on a substrate; (b) transmitting a signal representing an exhaust pressure detected by a pressure detector to a controller after the first process gas is supplied into the process chamber; (c) controlling a pressure adjustor and the flow rate control device once the signal is received by the controller such that the exhaust pressure reaches a predetermined pressure; (d) supplying a purge gas from a purge gas supply unit into the process chamber to purge an inside atmosphere after forming the first film; and (e) supplying a second process gas from a second process gas supply unit into the process chamber via the flow rate control device to form a second film.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: July 29, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Hidenari Yoshida, Tomoshi Taniyama
  • Patent number: 8791033
    Abstract: A process for coating a semiconductor wafer with a coating composition comprises curing the coating with a pulsed UV light, thereby preventing delamination during reflow operations. In a particular embodiment, the coating composition comprises both epoxy and acrylate resins. The epoxy resin can be cured thermally; the acrylate resin is cured by UV irradiation.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: July 29, 2014
    Assignee: Henkel IP & Holding GmbH
    Inventors: Jeffrey Gasa, Dung Nghi Phan, Jeffrey Leon, Sharad Hajela, Shengqian Kong
  • Patent number: 8791026
    Abstract: A method and an apparatus for treating a silicon substrate for effectively removing a silicon oxide film formed on a surface of a silicon film and improving surface uniformity of the silicon film. The method comprises providing a substrate including a silicon film; providing a first fluid, which is capable of etching a silicon oxide film, to a surface of the substrate in a first time band; providing a second fluid containing water to the surface of the substrate in a second time band, which is different from the first time band; and providing a third fluid, which is capable of etching the silicon oxide film, has different ingredients as compared to the first fluid, and has high etching ratio with respect to the silicon oxide film, to a surface of the substrate in a third time band, which is different from the first time band and the second time band.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 29, 2014
    Assignee: MMTech Co., Ltd.
    Inventors: Kil Soo An, Seung Il Chang
  • Publication number: 20140203250
    Abstract: The invention relates to a fabrication apparatus for fabricating a patterned layer (18) on a substrate (14). Protective material (17) is applied in second regions on the substrate (14) and liquid layer material (18) is then printed in first regions being different to the second regions on the substrate (14). The layer material (18) is dried by heating the layer material (18) to a drying temperature being smaller than a melting temperature of the protective material (17), before removing the protective material (17) from the substrate (14) by using a removing temperature being larger than the melting temperature of the protective material (17). A patterned layer (18) can therefore be produced, without using, for example, a costly photolithography process, and because of the use of the protective material (17) the layer material (18) is present in the desired first regions only and not in the second regions. This improves the quality of the patterned layer, which may be used for producing an OLED.
    Type: Application
    Filed: May 9, 2012
    Publication date: July 24, 2014
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Christoph Rickers, Pieter Gijsbertus Maria Kruijt
  • Publication number: 20140202632
    Abstract: Methods of treating the surface of a metal-containing hardmask used in the manufacture of semiconductors by contacting the hardmask surface with a composition capable of adjusting the water contact angle so as to substantially match that of subsequently applied organic coatings are provided.
    Type: Application
    Filed: January 19, 2013
    Publication date: July 24, 2014
    Applicant: ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Deyan WANG, Peter TREFONAS, III, Jieqian ZHANG, Peng-Wei CHUANG
  • Publication number: 20140206201
    Abstract: Compositions suitable for forming oxymetal hardmask layers are provided. Methods of forming oxymetal hardmask layers using such compositions are also provided, where the surface of the oxymetal hardmask layer formed has a water contact angle substantially matched to that of subsequently applied organic coatings.
    Type: Application
    Filed: January 19, 2013
    Publication date: July 24, 2014
    Applicant: ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Deyan WANG, Peter TREFONAS, III, Shintaro YAMADA, Kathleen M. O'Connell
  • Patent number: 8784951
    Abstract: A method of forming an insulation film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: (i) adsorbing a non-excited non-halide precursor having four or more silicon atoms in its molecule onto a substrate placed in a reaction space; (ii) supplying an oxygen-free reactant to the reaction space without applying RF power so as to expose the precursor-adsorbed substrate to the reactant; and (iii) after step (ii), applying RF power to the reaction space while the oxygen-free reactant is supplied in the reaction space; and (iv) repeating steps (i) to (iii) as a cycle, thereby depositing an insulation film on the substrate.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: July 22, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Hideaki Fukuka
  • Patent number: 8778812
    Abstract: A film deposition method includes an adsorption step of adsorbing a first reaction gas onto a substrate by supplying the first reaction gas from a first gas supplying portion for a predetermined period without supplying a reaction gas from a second gas supplying portion while separating a first process area and a second process area by supplying a separation gas from a separation gas supplying portion and rotating a turntable; and a reaction step of having the first reaction gas adsorbed onto the substrate react with a second reaction gas by supplying the second reaction gas from the second gas supplying portion for a predetermined period without supplying a reaction gas from the first gas supplying portion while separating the first process area and the second process area by supplying the separation gas from the separation gas supplying portion and rotating the turntable.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: July 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Haruhiko Furuya, Jun Ogawa, Masahiko Kaminishi, Yoshinobu Ise, Yoshitaka Enoki
  • Patent number: 8778811
    Abstract: Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine-containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25 C and about 600 C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Dipankar Pramanik, Boris Borisov
  • Patent number: 8778809
    Abstract: A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara
  • Patent number: 8771535
    Abstract: A sample contamination method according to an embodiment includes spraying a chemical solution containing contaminants into a casing, carrying a semiconductor substrate into the casing filled with the chemical solution by the spraying, leaving the semiconductor substrate in the casing filled with the chemical solution for a predetermined time, and carrying the semiconductor substrate out of the casing after the predetermined time passes.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Yamada, Makiko Katano, Ayako Mizuno, Eri Uemura, Asuka Uchinuno, Chikashi Takeuchi
  • Patent number: 8772160
    Abstract: An object of the present invention is to provide an apparatus for successive deposition used for manufacturing a semiconductor element including an oxide semiconductor in which impurities are not included. By using the deposition apparatus capable of successive deposition of the present invention that keeps its inside in high vacuum state, and thus allows films to be deposited without being exposed to the air, the entry of impurities such as hydrogen into the oxide semiconductor layer and the layer being in contact with the oxide semiconductor layer can be prevented; as a result, a semiconductor element including a high-purity oxide semiconductor layer in which hydrogen concentration is sufficiently reduced can be manufactured. In such a semiconductor element, off-state current is low, and a semiconductor device with low power consumption can be realized.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Natsuko Takase
  • Patent number: 8772176
    Abstract: In a forming method of an adhesive layer including the steps of selectively coating, on a surface to be bonded, an adhesive composition containing a thermosetting composition and an organic solvent using a noncontact coating device; and removing the organic solvent from the adhesive composition coated on the surface to be bonded and in a forming method of an adhesive layer characterized in the thermosetting composition has a hardening property so as to exhibit two kinds of reaction temperatures, the adhesive composition comprising an epoxy resin and an epoxy curing agent which are reacted through a first hardening reaction exhibiting a first DSC peak within a temperature range of 100 to 160° C. and a second hardening reaction relating to a self-polymerization of the epoxy resin and exhibiting a second DSC peak within a temperature range of 140 to 200° C.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 8, 2014
    Assignees: Kyocera Chemical Corporation, Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Sakurai, Yuichi Noguchi, Norio Kurokawa, Yasuo Tane
  • Publication number: 20140187053
    Abstract: A method of cleaning a thin film forming apparatus wherein a process for supplying a film forming gas into a reaction tube of the thin film forming apparatus to form a thin film on an object to be processed is repeated more than one time and then a cleaning gas is supplied into the reaction tube to remove extraneous particles attached to an interior of the apparatus, the method comprising: a first cleaning process including supplying a first cleaning gas into the reaction tube to remove the extraneous particles attached to the interior of the apparatus when a first cleaning start conditions is satisfied; and a second cleaning process including performing a cleaning process that is different from the first cleaning process when a second cleaning start condition that is different from the first cleaning start condition is satisfied.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 3, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Ryota GOTO, Rintaro TAKAO
  • Publication number: 20140187049
    Abstract: A showerhead electrode assembly for a plasma processing apparatus is provided. The showerhead electrode assembly includes a first member attached to a second member. The first and second members have first and second gas passages in fluid communication. When a process gas is flowed through the gas passages, a total pressure drop is generated across the first and second gas passages. A fraction of the total pressure drop across the second gas passages is greater than a fraction of the total pressure drop across the first gas passages.
    Type: Application
    Filed: March 5, 2014
    Publication date: July 3, 2014
    Applicant: Lam Research Corporation
    Inventors: Jason Augustino, Anthony de la Llera, Allan K. Ronne, Jaehyun Kim, Rajinder Dhindsa, Yen-Kun Wang, Saurabh J. Ullal, Anthony J. Norell, Keith Comendant, William M. Denty, JR.
  • Publication number: 20140174911
    Abstract: Embodiments provided herein describe methods and systems for depositing material onto a surface. A target including a material in a porous state is provided. The density of the material in the porous state is less than 89% of the absolute density of the material. The target is positioned over a surface. At least some of the material is caused to be ejected from the target and deposited onto the surface.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventor: Chi-I Lang
  • Publication number: 20140179114
    Abstract: A radical source for supplying radicals during atomic layer deposition semiconductor processing operations is provided. The radical source may include a remote volume, a baffle volume, and a baffle that partitions the remote volume from the baffle volume. The baffle volume and the remote volume may be fluidly connected through the baffle via a plurality of baffle holes. The baffle may be offset from a faceplate with a plurality of first gas distribution holes fluidly connected with the baffle volume. A baffle gas inlet may be fluidly connected with the baffle volume, and a first process gas inlet may be fluidly connected with the remote volume. Baffle gas may be flowed into the baffle volume to prevent radicalized first process gas in the remote volume from flowing through the baffle volume and the faceplate.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Inventor: Bart J. van Schravendijk
  • Publication number: 20140179113
    Abstract: Embodiments provided herein describe methods and systems for processing substrates. A plasma including radical species and charged species is generated. The charged species of the plasma are collected. A substrate is exposed to the radical species of the plasma. A layer is formed on the substrate after exposing the substrate to the radical species.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventors: Chi-I Lang, Sandip Niyogi
  • Patent number: 8759148
    Abstract: A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 24, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 8759226
    Abstract: A semiconductor processing apparatus includes a reaction chamber, a loading chamber, a movable support, a drive mechanism, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable support is configured to hold a workpiece. The drive mechanism is configured to move a workpiece held on the support towards the opening of the baseplate into a processing position. The control system is configured to create a positive pressure gradient between the reaction chamber and the loading chamber while the workpiece support is in motion. Purge gases flow from the reaction chamber into the loading chamber while the workpiece support is in motion. The control system is configured to create a negative pressure gradient between the reaction chamber and the loading chamber while the workpiece is being processed.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 24, 2014
    Assignee: ASM America, Inc.
    Inventors: Joseph C. Reed, Eric J. Shero
  • Patent number: 8759232
    Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joerg Hohage, Hartmut Ruelke, Ralf Richter
  • Patent number: 8759201
    Abstract: A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 24, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Yi-Chiau Huang, Errol Antonio C. Sanchez, Xianzhi Tao
  • Publication number: 20140170858
    Abstract: Provided is a method including forming a film including a predetermined element, oxygen and at least one element selected from a group consisting of nitrogen, carbon and boron on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate wherein the source gas contains the predetermined element, chlorine and oxygen with a chemical bond of the predetermined element and oxygen, and supplying a reactive gas to the substrate wherein the reactive gas contains the at least one element selected from the group consisting of nitrogen, carbon and boron.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 19, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Katsuyoshi HARADA, Yoshiro HIROSE, Atsushi SANO
  • Publication number: 20140167184
    Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.
    Type: Application
    Filed: August 5, 2013
    Publication date: June 19, 2014
    Applicant: Infineon Technologies AG
    Inventors: Frank Huebinger, Steffen Rothenhaeusser, Kerstin Kaemmer
  • Publication number: 20140159046
    Abstract: The present invention provides a flexible display substrate, the manufacturing method thereof and a flexible display device, relates to the field of flexible display technology, and can solve the technical problems that the existing flexible display substrate is easy to be damaged during deforming, has small amount of deformation, degraded display performance or high costs, or has difficulty in manufacturing process. The flexible display substrate according to the present invention comprising a hard material layer disposed at the fragile positions of the flexible display substrate. The manufacturing method for the flexible display substrate according to the present invention comprises forming a pattern of a hard material layer. The flexible display device of the present invention comprises the flexible display substrate mentioned above.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 12, 2014
    Inventors: Wei Deng, Jianwei Yu, Zhuo Zhang, Xiaoxiong Tian
  • Patent number: 8741782
    Abstract: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Kam L. Lee, Robert L. Wisnieff
  • Patent number: 8741783
    Abstract: A method of cleaning an inside of a processing chamber is provided according to an embodiment of the present disclosure. The method includes supplying a fluorine-based gas and a nitrogen oxide-based gas as the cleaning gas, into the processing chamber heated to a first temperature, and removing a deposit by a thermochemical reaction. The method further includes changing a temperature in the processing chamber to a second temperature higher than the first temperature, and supplying the fluorine-based gas and the nitrogen oxide-based gas as the cleaning gas, and removing extraneous materials, remaining on the surface of the member in the processing chamber, by a thermochemical reaction.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kenji Kameda, Yuji Urano
  • Patent number: 8734619
    Abstract: A method including directing a first radiation at a first copper-indium-gallium (CIG) sputtering target in a reactive copper indium gallium selenide (CIGS) sputtering process, detecting a first reflected radiation from the first CIG target and determining the amount of selenium poisoning of the first CIG target based on the first reflected radiation.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: May 27, 2014
    Assignee: Hanergy Holding Group Ltd.
    Inventor: John Corson
  • Patent number: 8733280
    Abstract: A top assembly for a processing chamber having a back plate and a hub is provided. The back plate has a first portion and a second portion. The first portion is connected to the second portion through a central region of the back plate, wherein a gap is defined between opposing surfaces of the first and second portions outside the central region. The first portion includes an embedded heating element. The hub is affixed to a top surface of the second portion of the back plate over the central region. The hub has a top surface with a plurality of channel openings defined within a central region of the hub and a bottom surface having a central extension with a plurality of channels defined therethrough. The bottom surface includes an annular extension spaced apart from the central extension.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: May 27, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Lipyeow Yap, Jay DeDontney, Shouqian Shao, Jason Wright
  • Publication number: 20140141623
    Abstract: In manufacturing a semiconductor device, a first chamber is provided. An opening couples the first chamber to a first environment through which at least one substrate can pass. A first seal environmentally isolates the first chamber from the first environment. A process chamber is coupled to the first chamber. Another seal environmental isolates the first and the process chambers. The substrate is placed within the first chamber, and the first chamber and the outside environment are isolated. The second opening is opened, and the substrate moves into the semiconductor process chamber. The first chamber is again environmentally isolated from the second volume. A semiconductor processing step is performed on the substrate within the processing chamber. While the substrate is processed, the substrate is rotated and translated through the processing chamber.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 22, 2014
    Applicant: Solyndra LLC
    Inventor: Ratson Morad
  • Patent number: 8728950
    Abstract: Disclosed are a coating method of forming a coating with a stable thickness from a coating solution with a low viscosity employing a slit-type die coater and an organic electroluminescence element prepared employing the coating method. The coating method employing a slit-type die coater comprises the steps of allowing a lip tip of the slit-type die coater to bring close to the substrate to form a coating solution bead between the lip tip and the substrate, and coating on the substrate a coating solution ejected from a slit outlet at the lip tip while relatively moving the slit-type die coater and the substrate, thereby forming at least two coating layers in the stripe shape, featured in that the lip tip has at least one groove in the coating region in the coating width direction, and a pressure at the slit outlet of the coating solution of the bead is negative or zero.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: May 20, 2014
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Shigetoshi Kawabe, Nobuaki Takahashi
  • Patent number: 8728953
    Abstract: A method of processing a semiconductor workpiece includes placing a back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, and the back surface is in fluid communication with a back region having an associated back gas pressure. The method further includes performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1?Pc1, and performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: May 20, 2014
    Assignee: SPTS Technologies Limited
    Inventors: Stephen R Burgess, Anthony P Wilby
  • Patent number: 8728952
    Abstract: Provided is a coating method of an alignment film, including: providing a board, having a substrate, the substrate forming an alignment liquid coating area thereon; forming a barrier structure around the alignment liquid coating area; coating an alignment liquid in the alignment liquid coating area, wherein the barrier structure blocks the alignment liquid to diffuse outside the alignment liquid coating area; and curing the alignment liquid to form an alignment film. The present invention may assure that the formed alignment film can not affect other areas adjacent to the alignment liquid coating area.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: MeiNa Zhu
  • Patent number: 8728951
    Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
  • Patent number: 8720049
    Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Tae Kyun Bae, Chang Gun Oh, Ho Sik Park
  • Patent number: 8722546
    Abstract: A method of forming a dielectric film having Si—C bonds and/or Si—N bonds on a semiconductor substrate by cyclic deposition, includes: (i) conducting one or more cycles of cyclic deposition in a reaction space wherein a semiconductor substrate is placed, using a Si-containing precursor and a reactant gas; and (ii) before or after step (i), applying a pulse of RF power to the reaction space while supplying a rare gas and a treatment gas without supplying a Si-containing precursor, whereby a dielectric film having Si—C bonds and/or Si—N bonds is formed on the semiconductor substrate.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: May 13, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Takahiro Oka
  • Publication number: 20140127912
    Abstract: Plasma deposition in which properties of a discharge plasma are controlled by modifying the grounding path of the plasma is potentially applicable in any plasma deposition environment, but finds particular use in ionized physical vapor deposition (iPVD) gapfill applications. Plasma flux ion energy and E/D ratio can be controlled by modifying the grounding path (grounding surface's location, shape and/or area). Control of plasma properties in this way can reduce or eliminate reliance on conventional costly and complicated RF systems for plasma control. For a high density plasma source, the ionization fraction and ion energy can be high enough that self-sputtering may occur even without any RF bias. And unlike RF induced sputtering, self-sputtering has narrow ion energy distribution, which provides better process controllability and larger process window for integration.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Inventors: Liqi Wu, Ishtak Karim, Huatan Qiu
  • Publication number: 20140127911
    Abstract: A palladium plated aluminum component of a semiconductor plasma processing chamber comprises a substrate including at least an aluminum or aluminum alloy surface, and a palladium plating on the aluminum or aluminum alloy surface of the substrate. The palladium plating comprises an exposed surface of the component and/or a mating surface of the component.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Hong Shih, Lin Xu, Rajinder Dhindsa, Travis Taylor, John Daugherty
  • Patent number: 8716150
    Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhiguo Sun, Songkram Srivathanakul, Huang Liu, Hung-Wei Liu
  • Patent number: 8715518
    Abstract: A protective chuck is disposed on a substrate with a gas bearing layer between the bottom surface of the protective chuck and the substrate surface. The gas bearing layer protects a surface region against a fluid layer covering the substrate surface. The protection of the gas bearing is a non-contact protection, reducing or eliminating potential damage to the substrate surface due to friction. The gas bearing can enable combinatorial processing of a substrate, providing multiple isolated processing regions on a single substrate with different material and processing conditions.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 6, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Rajesh Kelekar
  • Patent number: 8716147
    Abstract: Provided are a manufacturing method of a semiconductor device and a substrate processing apparatus.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 6, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takaaki Noda, Masami Miyamoto, Ryuji Yamamoto
  • Patent number: 8716148
    Abstract: A semiconductor device manufacturing method includes forming an insulation film containing silicon, oxygen and carbon over a semiconductor substrate by chemical vapor deposition; making UV cure on the insulation film being heated at a temperature of 350° C. or below after the forming the insulation film; and making helium plasma processing on the insulation film after the UV cure.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshiyuki Ohkura, Toshiki Mori
  • Publication number: 20140117529
    Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Kyle Armstrong, Michael D. Hyatt, Michael Dean Van Patten, David A. Kewley, Ming-Chuan Yang