Abstract: A substrate processing apparatus comprising: a processing chamber which is to accommodate at least one substrate; a gas supply system which is to supply processing gas into the processing chamber; an exhaust system which is to exhaust atmosphere in the processing chamber; and at least one pair of electrodes which are to bring the processing gas into an active state and which are accommodated in protection tubes such that the electrodes can be inserted into and pulled out from the protection tubes, wherein the electrodes are accommodated in the protection tube in a state where at least a portion of the electrodes is bent, and the electrodes are formed of flexible members, is disclosed.

Abstract: The present invention provides a transparent electroconductive oxide layer having a high transmittance and a high electroconductivity and further a thin-film photoelectric converter having a high photoelectric conversion efficiency by applying the transparent electroconductive oxide layer to a transparent electrode layer of a photoelectric converter. The transparent electroconductive oxide layer in the present invention is deposited on a transparent substrate with a first and a second impurities contained in the transparent electroconductive oxide layer, especially in the vicinity of a surface of the layer in a higher concentration, and carbon atoms contained in the vicinity of the surface of the layer, thereby achieving a high transmittance and a high electroconductivity simultaneously and thus solving the problem.

Abstract: A semiconductor device is provided with a porous structure layer formed by silicone resin between a substrate and a semiconductor element. Alternatively, a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing at least one type of alkoxysilane selected from a group consisting of monoalkoxysilane, dialkoxysilane, and trialkoxysilane, and tetraalkoxysilane is provided between the substrate and the semiconductor element. As a further alternative, an adhesion layer formed by a compound obtained by hydrolyzing and condensing an alkoxysilane is provided on a resin substrate, and a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing an alkoxysilane, is provided on the adhesion layer.

Abstract: A substrate processing chamber and methods for processing multiple substrates is provided and generally includes a plurality of spaced gas distribution assemblies and a substrate support apparatus to rotate substrates along a path adjacent each of the plurality of gas distribution assemblies. Each of the gas distribution assemblies comprises a plurality of elongate gas ports extending in a direction substantially perpendicularly to the path traversed by the substrate.

Abstract: A method for batch brazing in a diffusion furnace includes inserting a plurality of fusible parts into a plurality of slots of at least one quartz boat, transporting the at least one quartz boat, including the fusible parts, into an interior of a reaction chamber of the diffusion furnace, sealing the interior of the reaction chamber, adjusting an atmosphere of the interior of the reaction chamber according to a recipe, moving a preheated furnace heating element from a location spaced apart from the reaction chamber to a location in substantial proximity with the reaction chamber to increase a temperature of the atmosphere of the interior of the reaction chamber above a predefined brazing temperature for a predefined brazing time period according to the recipe.

Abstract: A gas filtration apparatus and method comprises a housing with an inlet for gas to enter and an outlet for the gas to exit. The housing contains a filter comprised of sintered metal fibers having an active filtration area through which the gas flows to remove suspended particles from the gas. The filter is substantially uniform in thickness and porosity through the active filtration area. The filter media being sealed to a metal structure in the housing with the metal structure having an opening to permit gas to flow through. A method of making a vapor/gas mixture includes the steps of producing a vapor in a gas to form the vapor/gas mixture passing the vapor/gas mixture through an opening in a housing containing a filter comprised of sintered metal fibers through which the vapor/gas mixture flows.

Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A drive mechanism attached to first and second valve plates effects rotation of the first and second valve plates to switch the valve plates between first and second angular orientations to change the degree of alignment of first and second open areas of the valve plates and thereby increase or decrease conductance to achieve desired pressure settings in the chamber.

Abstract: A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.

Abstract: A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.

Abstract: A method is provided for forming FinFETS with improved alignment features. Embodiments include forming on a Si substrate pillars of TEOS on poly-Si; conformally depositing a first TEOS liner over the entire substrate; etching the first TEOS liner and substrate through the pillars, forming first trenches; filling the first trenches and spaces between the pillars with an oxide; removing the TEOS from the pillars and the oxide therebetween; removing the poly-Si; conformally depositing a second TEOS liner over the entire Si substrate; etching the second TEOS liner and Si between the oxide, forming second trenches having a larger depth than the first trenches; filling the second trenches with oxide; removing the oxide and the first and second TEOS liners down to an upper surface of the Si substrate; and recessing the oxide below the upper surface of the Si substrate.

Abstract: A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature.

Abstract: A more uniform plasma process is implemented for treating a treatment object using an inductively coupled plasma source which produces an asymmetric plasma density pattern at the treatment surface using a slotted electrostatic shield having uniformly spaced-apart slots. The slotted electrostatic shield is modified in a way which compensates for the asymmetric plasma density pattern to provide a modified plasma density pattern at the treatment surface. A more uniform radial plasma process is described in which an electrostatic shield arrangement is configured to replace a given electrostatic shield in a way which provides for producing a modified radial variation characteristic across the treatment surface. The inductively coupled plasma source defines an axis of symmetry and the electrostatic shield arrangement is configured to include a shape that extends through a range of radii relative to the axis of symmetry.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To improve the copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: A film forming apparatus and a film forming method for suppressing a drop in the film forming speed caused by-product gas are provided. A film forming apparatus for forming a film on a wafer includes a chamber in which the wafer is located; a gas introducing member configured to introduce raw material gas into the chamber, in which the raw material gas turning into by-product gas and a substance which adheres to the surface of the wafer by reacting at a surface of the wafer; and a reverse reaction member configured to generate the raw material gas by causing the by-product gas to react in the chamber.

Abstract: A method is described for manufacturing a micromechanical component. The method includes providing a first substrate, forming a first connecting structure on the first substrate, and forming a microstructure on the first substrate after forming the first connecting structure. The microstructure has at least one movable functional element. The method further includes providing a second substrate having a second connecting structure, and joining the first and second substrates by carrying out a bonding process, the first and second connecting structures being joined to form a common connecting structure, and a sealed cavity being formed in the region of the microstructure. The method provides that the first connecting structure takes the form of a buried connecting structure extending up to an upper surface of the first substrate. Also described is a related micromechanical component.

Abstract: A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, and an interface block. An exposure device is arranged adjacent to an interface block. The interface block comprises a drying processing group including two drying processing units and an interface transport mechanism. After a substrate is subjected to exposure processing by the exposure device, the substrate is transported to the drying processing units in the drying processing group by the interface transport mechanism, where the substrate is subjected to cleaning and drying processings.

Abstract: A particle reducing method includes a step of supplying a first gas to a vacuum chamber in which a susceptor, formed by an insulating object and the surface of which is provided with a substrate mounting portion, is rotatably provided; a step of generating plasma from the first gas by supplying high frequency waves to a plasma generating device provided for the vacuum chamber; and a step of exposing the substrate mounting portion, on which a substrate is not mounted, to the plasma while rotating the susceptor.

Abstract: A shielded lid heater lid heater suitable for use with a plasma processing chamber, a plasma processing chamber having a shielded lid heater and a method for plasma processing are provided. The method and apparatus enhances positional control of plasma location within a plasma processing chamber, and may be utilized in etch, deposition, implant, and thermal processing systems, among other applications where the control of plasma location is desirable. In one embodiment, a shielded lid heater is provided that includes an aluminum base and RF shield sandwiching a heater element.

Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.

Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.

Abstract: A method of patterning a substrate includes forming spaced first features over a substrate. Individual of the spaced first features include sidewall portions of different composition than material that is laterally between the sidewall portions. A mixture of immiscible materials is provided between the spaced first features. At least two of the immiscible materials are laterally separated along at least one elevation between adjacent spaced first features. The laterally separating forms a laterally intermediate region including one of the immiscible materials between two laterally outer regions including another of the immiscible materials along the one elevation. The laterally outer regions are removed and material of the spaced first features is removed between the sidewall portions to form spaced second features over the substrate. Other embodiments are disclosed.

Abstract: A showerhead electrode for a plasma processing apparatus includes an interface gel between facing surfaces of an electrode plate and a backing plate. The interface gel maintains thermal conductivity during lateral displacements generated during temperature cycling due to mismatch in coefficients of thermal expansion. The interface gel comprises, for example, a silicone based composite filled with aluminum oxide microspheres. The interface gel can conform to irregularly shaped features and maximize surface contact area between mating surfaces. The interface gel can be pre-applied to a consumable upper electrode.

Abstract: First, a porous insulating film 120 is formed using an organic silica raw material containing a hydrocarbon group. The hydrocarbon group contains, for example, an unsaturated carbon compound, but may contain a saturated carbon compound. The skeleton of the organic silica is, for example, cyclic organic silica. Next, the surface of the porous insulating film 120 is subjected to plasma processing by using a processing gas containing an inactive gas and a reducing gas. Subsequently, in the porous insulating film 120, a wiring trench 123 is formed and is embedded with wiring 124.

Abstract: An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas.

Abstract: Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.

Abstract: An apparatus and method for delivering fluids to a semiconductor chamber for combinatorial processing is provided. In some embodiments the apparatus is comprised of a showerhead assembly having a plurality of processing sectors separated by a purge member. The processing sectors are configured to receive one or more processing fluids for combinatorial processing on a substrate. The processing sectors are isolated by a purge fluid conveyed through the purge member. The purge member is configured to selectively control the profile of the purge fluid to enhance isolation of the processing fluids within each sector. The profile of the purge fluid is manipulated by selectively controlling the shape and/or density of the purge curtain, independently between each processing sector.

Abstract: According to one embodiment, a pattern formation method includes, before forming a circuit pattern on a substrate using imprinting, a wall pattern with a predetermined height is formed to surround the periphery of an area serving as imprint shots on the substrate in each imprint shot and to allow the imprint shots to be separated from one another. The circuit pattern is formed in the imprint shots surrounded by the wall pattern through imprinting.

Abstract: A graphene-on-oxide substrate according to the present invention includes: a substrate having a metal oxide layer formed on its surface; and, formed on the metal oxide layer, a graphene layer including at least one atomic layer of the graphene. The graphene layer is grown generally parallel to the surface of the metal oxide layer, and the inter-atomic-layer distance between the graphene atomic layer adjacent to the surface of the metal oxide layer and the surface atomic layer of the metal oxide layer is 0.34 nm or less. Preferably, the arithmetic mean surface roughness Ra of the metal oxide layer is 1 nm or less.

Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.

Abstract: A film deposition method, in which a film of a reaction product of a first reaction gas, which tends to be adsorbed onto hydroxyl radicals, and a second reaction gas capable of reacting with the first reaction gas is formed on a substrate provided with a concave portion, includes a step of controlling an adsorption distribution of the hydroxyl radicals in a depth direction in the concave portion of the substrate; a step of supplying the first reaction gas on the substrate onto which the hydroxyl radicals are adsorbed; and a step of supplying the second reaction gas on the substrate onto which the first reaction gas is adsorbed.

Abstract: The substrate processing apparatus includes a reaction chamber configured to accommodate a substrate; a first gas supply unit configured to supply a first process gas containing a silicon element to the substrate; a second gas supply unit configured to supply a second process gas containing a silicon element and a chlorine element to the substrate; an exhaust unit configured to exhaust the first process gas and the second process gas; a cleaning gas bypass supply unit configured to supply a cleaning gas to the exhaust unit; a cleaning monitoring unit installed in the exhaust unit; a gas flow rate control unit configured to adjust an amount of the cleaning gas supplied; and a main control unit configured to control the gas flow rate control unit in response to a signal received from the cleaning gas monitoring unit.

Abstract: Porous nano-imprint lithography templates may include pores, channels, or porous layers arranged to allow evacuation of gas trapped between a nano-imprint lithography template and substrate. The pores or channels may be formed by etch or other processes. Gaskets may be formed on an nano-imprint lithography template to restrict flow of polymerizable material during nano-imprint lithography processes.

Abstract: A method of depositing a film with a target conformality on a patterned substrate, includes: depositing a first film on a convex pattern and a bottom surface; and depositing a second film on the first film, thereby forming an integrated film having a target conformality, wherein one of the first and second films is a conformal film which is non-flowable when being deposited and has a conformality of about 80% to about 100%, and the other of the first and second films is a flowable film which is flowable when being deposited.

Abstract: According to one embodiment, a mask manufacturing method includes acquiring positional deviation information between an actual position of a pattern formed on a mask substrate and a design position decided at the time of designing the pattern; calculating an irradiating amount and an irradiating position of radiation to be irradiated to a predetermined area of a square on the mask substrate according to the calculated positional deviation information; and irradiating the radiation based on the calculated irradiating amount and the calculated irradiating position to form in a part of the mask substrate a heterogeneous layer of which volume is expanded more greatly than that of the surrounding mask substrate region.

Abstract: An oxygen-containing gas and a hydrogen-containing gas are supplied into a pre-reaction chamber heated to a second temperature and having the pressure set to less than an atmospheric pressure, and a reaction is induced between both gases in the pre-reaction chamber to generate reactive species, and the reactive species are supplied into the process chamber and exhausted therefrom, in which a substrate heated to the first temperature is housed and the pressure is set to less than the atmospheric pressure, and processing is applied to the substrate by the reactive species, with the second temperature set to be not less than the first temperature at this time.

Abstract: A substrate carrier for performing a deposition process comprises a supporting element and a cover element. The supporting element having a through hole is used to carry a substrate. The cover element is removably engaged with the supporting element, so as to secure the substrate therebetween and expose a deposition surface of the substrate from the through hole.

Abstract: A chamber for combinatorially processing a substrate is provided. The chamber includes a first mask and a second mask that share a common central axis. The first mask and the second mask are independently rotatable around the common central axis. The first mask has a first plurality of radial apertures and the second mask has a second plurality of radial apertures. An axis of the first plurality of radial apertures is offset from an axis of the second plurality of radial apertures. A substrate support that is operable to support a substrate below the first and second masks is included. The substrate support shares the common central axis.

Abstract: An organic layer deposition apparatus including an electrostatic chuck combined with a substrate so as to fixedly support the substrate. The organic layer deposition apparatus including a receiving surface that has a set curvature for receiving the substrate; a deposition source for discharging a deposition material toward the substrate; a deposition source nozzle unit disposed at a side of the deposition source and including a plurality of deposition source nozzles arranged in a first direction; and a patterning slit sheet disposed to face the deposition source nozzle unit, and having a plurality of patterning slits arranged in a second direction perpendicular to the first direction, wherein a cross section of the patterning slit sheet on a plane formed by lines extending in the second direction and a third direction is bent by a set degree, wherein the third direction is perpendicular to the first and second directions.

Abstract: Disclosed are systems and methods for improving front-side process uniformity by back-side metallization. In some implementations, a metal layer can be formed on the back side of a semiconductor wafer prior to certain process steps such as plasma-based processes. Presence of such a back-side metal layer reduces variations in, for example, thickness of a deposited and/or etched layer resulting from the plasma-based processes. Such reduction in thickness variations can result from reduced variation in radio-frequency (RF) coupling during the plasma-based processes. Various examples of wafer types, back-side metal layer configurations, and plasma-based processes are disclosed.

Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.

Abstract: Apparatuses and methods for cooling and transferring wafers from low pressure environment to high pressure environment are provided. An apparatus may include a cooling pedestal and a set of supports for holding the wafer above the cooling pedestal. The average gap between the wafer and the cooling pedestal may be no greater than about 0.010 inches. Venting gases may be used to increase the pressure inside the apparatus during the transfer. In certain embodiment, venting gases comprise nitrogen.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: Defect selective passivation in semiconductor fabrication for reducing defects.

Abstract: A substrate clamped to a stage is moved in a rastering motion in a site-isolated deposition chamber. The raster pattern may be a radial pattern, predetermined X-Y pattern, horizontal/vertical pattern or random (free-form) pattern. The chamber includes a sputter source to generate the sputtered material which is delivered through an aperture positioned over the substrate. By moving the substrate in a rastering motion, the sputtered material is deposited more equally and uniformly.

Abstract: Elemental fluorine is often manufactured electrochemically from a solution of KF in hydrogen fluoride and contains varying amounts of entrained electrolyte salt in solid form as impurity. The invention concerns a process for the purification of such impure elemental fluorine by contact with liquid hydrogen fluoride, e.g., in a jet gas scrubber or by bubbling the raw fluorine through liquid hydrogen fluoride. After this purification step, any entrained hydrogen fluoride is removed by adsorption, condensing it out or both. After passing through a filter with very small pores, the purified fluorine is especially suited for the semiconductor industry as etching gas or as chamber cleaning gas in the manufacture of semiconductors, TFTs and solar cells, or for the manufacture of micro-electromechanical systems (“MEMS”).

Abstract: Semiconductor substrate transfer treatment/processing tunnel-arrangement, containing such means, that thereby also during the uninterrupted operation thereof the uninterruptedly taking place of the establishing of a (sub) micrometer high layer of semiconductor substances with an optimum uniform height thereof upon the successive semiconductor substrate-sections, uninterruptedly displacing therethrough and such by means of through a strip-shaped supply-section of the uppertunnelclock in its central semiconductor section the uninterruptedly taking place of a supply of the combination of fluidic support-medium and parts of a semiconductor substance in a solid- or fluidic form thereof and in the thereupon following strip-shaped semiconductor treatment/processing section underneath a vibrating transducer-arrangement, located in a transducer-compartment of this block, the also by means of the in addition developed heat of this vibrating transducer the taking place of evaporation of this support-medium under an at-l

Abstract: The present invention discloses a TFT, an array substrate, a device and a manufacturing method. The TFT comprises a conductive metal layer; an insulting oxidizing layer is formed on the surface of the metal layer. In the present invention, because the oxidation treatment is conducted on the surface of the metal layer, the insulating oxidizing layer is formed and can substitute for the silicon nitride as a TFT barrier layer; compared with the preparation of a silicon nitride barrier layer needing the drilling crew and the material cost, the preparation of the oxidizing layer needs cheap equipment without increasing further materials so that the cost is saved; in addition, the oxidizing layer only exists on the surface of the metal layer, and has small obstruction for light and low requirement for the penetration rate; thus, the process control is relatively simple and the cost can be further reduced.

Abstract: A method of patterning nanostructures comprising printing an ink comprising the nanostructures onto a solvent-extracting first surface such that a pattern of nanostructures is formed on the first surface.

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.