Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Publication number: 20140120735
    Abstract: A semiconductor processing apparatus includes a process chamber, a pedestal and a showerhead. The pedestal is inside the process chamber and holds a semiconductor wafer. The showerhead supplies process gas to the process chamber.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shing Ann LUO, Yung Tai HUNG, Chin-Ta SU
  • Publication number: 20140120731
    Abstract: An ICP A plasma reactor having an enclosure wherein at least part of the ceiling forms a dielectric window. A substrate support is positioned within the enclosure below the dielectric window. An RF power applicator is positioned above the dielectric window to radiate RF power through the dielectric window and into the enclosure. A plurality of gas injectors are distributed uniformly above the substrate support to supply processing gas into the enclosure. A circular baffle is situated inside the enclosure and positioned above the substrate support but below the plraity of gas injectors so as to redirect the flow of the processing gas.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 1, 2014
    Applicant: Advanced Micro-Fabrication Equipment Inc, Shanghai
    Inventors: Songlin XU, Gang SHI, Tuqiang NI
  • Patent number: 8709202
    Abstract: Components of a plasma processing apparatus includes a backing member with gas passages attached to an upper electrode with gas passages. To compensate for the differences in coefficient of thermal expansion between the metallic backing member and upper electrode, the gas passages are positioned and sized such that they are misaligned at ambient temperature and substantially concentric at an elevated processing temperature. Non-uniform shear stresses can be generated in the elastomeric bonding material, due to the thermal expansion. Shear stresses can either be accommodated by applying an elastomeric bonding material of varying thickness or using a backing member comprising of multiple pieces.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 29, 2014
    Assignee: Lam Research Corporation
    Inventors: Anthony De La Llera, Allan K. Ronne, Jaehyun Kim, Jason Augustino, Rajinder Dhindsa, Yen-Kun Wang, Saurabh J. Ullal, Anthony J. Norell, Keith Comendant, William M. Denty, Jr.
  • Patent number: 8709887
    Abstract: A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Bernie Roque, Jr., Steven M. Shank, Beth A. Ward
  • Patent number: 8709955
    Abstract: A pattern transfer apparatus according to one embodiment includes a transfer region selecting part that performs operation in which when performing pattern transfer from a template provided with N transfer regions (N is an integer of 2 or larger) to a transferring substrate a plurality of times, 1 to N?1 transfer regions, which are to be used to perform the transfer to regions of the transferring substrate corresponding to part of the N transfer regions, are selected such that the number of the transfer to be performed using each of the N transfer regions is evened out.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuji Kobayashi
  • Publication number: 20140113395
    Abstract: A vapor deposition apparatus for depositing a thin film on a substrate includes a cover having an accommodation portion and a communicated portion, which communicated portion is connected to the accommodation portion and faces a direction of the substrate, and includes a body in the accommodation portion, which body includes a first portion and a second portion. The first portion is disposed at a first location of the body and connected to a first injection portion for injecting a first material onto the substrate, the second portion is disposed at a second location of the body and connected to a second injection portion for injecting a second material onto the substrate, and the body rotates in at least one direction so that the first portion and the second portion are alternately connected to each other with respect to the communicated portion.
    Type: Application
    Filed: March 12, 2013
    Publication date: April 24, 2014
    Inventors: In-Kyo KIM, Myung-Soo HUH, Suk-Won JUNG, Cheol-Min JANG, Jae-Hyun KIM, Jin-Kwang KIM, Chang-Woo SHIM, Sung-Hun KEY
  • Patent number: 8703622
    Abstract: A flat panel display device includes a substrate having a display unit, a metal sealing substrate including a first metal layer, a second metal layer, and an insulating layer therebetween, a sealing member between the substrate and the metal sealing substrate, and a power supply device including a magnet, the power supply being positioned on the metal sealing substrate and further including a first power supply unit configured to supply a first power to the first metal layer of the metal sealing substrate, a second power supply unit configured to supply a second power to the second metal layer of the metal sealing substrate, and an insulating unit between the first power supply unit and the second power supply unit, the insulating unit being configured to insulate the first and second power supply units from each other.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 22, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kuen-Dong Ha
  • Publication number: 20140106571
    Abstract: A plasma processing apparatus includes a process chamber housing defining a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate plasma in the process chamber, and a biasing system. The biasing system is configured to bias the platen to attract ions from the plasma towards the workpiece during a first processing time interval and configured to bias the platen to repel ions from the platen towards interior surfaces of the process chamber housing during a cleaning time interval. The cleaning time interval is separate from the first processing time interval and occurring after the first processing time interval.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Bon-Woong Koo, Richard M. White
  • Patent number: 8697582
    Abstract: A substrate-conveying roller includes a first shell, a second shell, an internal block, a manifold, and a clearance. The first shell has a plurality of first through holes serving as supply paths for a gas. The internal block is disposed inside the first shell. The manifold is formed in the internal block so as to guide the gas to the first through holes within the region of a specific angle. The clearance is formed so as to guide the gas to the first through holes outside the region of the specific angle. The second shell has second through holes for guiding the gas from the manifold to the first through holes, and is disposed between the first shell and the internal block. The central axes of the first through hole are offset from the central axes of the second through holes.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Sadayuki Okazaki, Kazuyoshi Honda
  • Patent number: 8691636
    Abstract: A method for removing germanium suboxide between a germanium (Ge) substrate and a dielectric layer made of metal oxide includes causing a supercritical fluid composition that includes a supercritical carbon dioxide fluid and an oxidant to diffuse into the germanium suboxide such that metal residues in the dielectric layer, the germanium suboxide and the oxidant are subjected to a redox reaction so as to reduce the germanium suboxide into germanium.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: April 8, 2014
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Chen-Shuo Huang
  • Patent number: 8691016
    Abstract: A deposition mask 601 is used to form a thin film 3 in a prescribed pattern on a substrate 10 by deposition. Each of a plurality of improved openings 62A of the deposition mask 601 has a protruding opening portion 64, and is formed so that the opening amount at an end in a lateral direction is larger than that in a central portion in the lateral direction. In a deposition apparatus 50, the deposition mask 601 is held in a fixed relative positional relation with a deposition source 53 by a mask unit 55. In the case of forming the thin film 3 in a stripe pattern on the substrate 10 by the deposition apparatus 50, deposition particles are sequentially deposited on the substrate 10 while relatively moving the substrate 10 along a scanning direction with a gap H being provided between the substrate 10 and the deposition mask 601.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: April 8, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Nobuhiro Hayashi, Shinichi Kawato
  • Patent number: 8691706
    Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai, Jiung Wu
  • Patent number: 8691667
    Abstract: This invention relates to a process for forming a continuous pattern on a substrate with a liquid media. Upon the deposition of the liquid media on the substrate, a portion the continuous pattern is evaporated upon contact with the substrate.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 8, 2014
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Charles Douglas MacPherson, Dennis Damon Walker, Matthew Stainer
  • Patent number: 8691707
    Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: April 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Yiming Li
  • Patent number: 8685867
    Abstract: Provided herein are novel pre-metal dielectric (PMD) integration schemes. According to various embodiments, the methods involve depositing flowable dielectric material to fill trenches or other gaps between gate structures in a front end of line (FEOL) fabrication process. The flowable dielectric material may be partially densified to form dual density filled gaps having a low density region capped by a high density region. In certain embodiments, the methods include further treating at least a portion of the gap fill material after subsequent process operations such as chemical mechanical planarization (CMP) or contact etching.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 1, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Michal Danek, Bart van Schravendijk, Nerissa Draeger, Lakshminarayana Nittala
  • Publication number: 20140087565
    Abstract: A method of manufacturing a semiconductor device includes forming thin films on substrates by performing a cycle a predetermined number of times. The cycle includes: supplying a process gas into a process container and confining the gas in the container including an outer reaction tube and an inner reaction tube having a flat top inner surface at an upper end portion covering a portion of a top surface of the support arranging and supporting the substrates and including a communication section connecting an inside of the inner reaction tube to an inside of the outer reaction tube, wherein the communication section is disposed at a region other than a region horizontally encompassing a substrate arrangement region; maintaining a state where the gas is confined in the container; and exhausting the gas from the container via the communication section and a space between the inner and outer reaction tubes.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Daigo Yamaguchi, Tsuyoshi Takeda, Taketoshi Sato, Hidenari Yoshida
  • Publication number: 20140080314
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times after supplying a nitriding gas to the substrate. The cycle includes performing the following steps in the following order: supplying a carbon-containing gas to the substrate; supplying a predetermined element-containing gas to the substrate; supplying the carbon-containing gas to the substrate; supplying an oxidizing gas to the substrate; and supplying the nitriding gas to the substrate.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 20, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Ryota SASAJIMA, Yoshinobu NAKAMURA
  • Patent number: 8673076
    Abstract: Disclosed is a substrate processing apparatus which comprises reaction tubes (3,4) for processing multiple substrates (27), a heater (5) for heating the substrates, and gas introducing nozzles (6,7,8,9,10) for supplying a gas into the reaction tubes. Each of the gas introducing nozzles (6,7,8,9) is structured so that at least the channel cross section of a portion facing the heater (5) is larger than those of the other portions.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: March 18, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Naoharu Nakaiso
  • Patent number: 8673702
    Abstract: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: March 18, 2014
    Assignee: Creator Technology B.V.
    Inventors: Fredericus Johannes Touwslager, Gerwin Hermanus Gelinck
  • Patent number: 8673790
    Abstract: A method of manufacturing a semiconductor device includes supplying a process gas into a process vessel accommodating a substrate to form a thin film on the substrate and supplying a cleaning gas into the process vessel to clean an inside of the process vessel, after the supplying the process gas to form the thin film is performed a predetermined number of times. When cleaning the inside of the process vessel, a fluorine-containing gas, an oxygen-containing gas and a hydrogen-containing gas are supplied as the cleaning gas into the process vessel heated and kept at a pressure less than an atmospheric pressure to remove a deposit including the thin film adhering to the inside of the process vessel through a thermochemical reaction.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 18, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Kotaro Murakami
  • Patent number: 8673746
    Abstract: The present invention includes methods directed to improved processes for producing a monolayer of sulfur on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 18, 2014
    Assignee: Sematech, Inc.
    Inventors: Joel Myron Barnett, Richard James William Hill
  • Patent number: 8673077
    Abstract: Vapor deposition particles (91) discharged from at least one vapor deposition source opening (61) pass through a plurality of limiting openings (82) of a limiting unit (80) and a plurality of mask openings (71) of a vapor deposition mask (70), and adhere to a substrate (10) that relatively moves along a second direction (10a) so as to form a coating film. The limiting unit includes a plurality of plate members stacked on one another. Accordingly, it is possible to efficiently form a vapor deposition coating film in which edge blurring is suppressed on a large-sized substrate at a low cost.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: March 18, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Shinichi Kawato, Satoshi Inoue, Satoshi Hashimoto
  • Patent number: 8669191
    Abstract: A method for the formation of an Ni film is herein disclosed, which comprises the steps of maintaining the temperature of an Si substrate at a desired level in a vacuum chamber; introducing, into the vacuum chamber, a nickel alkylamidinate (in this organometal compound, the alkyl group is a member selected from the group consisting of a methyl group, an ethyl group, a butyl group and a propyl group), H2 gas and NH3 gas; and then forming an Ni film according to the CVD technique, wherein the film-forming temperature is set at a level between higher than 280° C. and not higher than 350° C.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 11, 2014
    Assignee: Ulvac, Inc.
    Inventors: Toshimitsu Uehigashi, Yasushi Higuchi, Michio Ishikawa, Harunori Ushikawa, Naoki Hanada
  • Patent number: 8669192
    Abstract: First and second vapor deposition particles (91a, 91b) discharged from first and second vapor deposition source openings (61a, 61b) pass through first and second limiting openings (82a, 82b) of a limiting plate unit (80), pass through mask opening (71) of a vapor deposition mask (70) and adhere to a substrate (10) so as to form a coating film. If regions on the substrate to which the first vapor deposition particles and the second vapor deposition particles adhere if the vapor deposition mask is assumed not to exist are respectively denoted by a first region (92a) and a second region (92b), the limiting plate unit limits the directionalities of the first vapor deposition particles and the second vapor deposition particles in a first direction (10a) that travel to the substrate such that the second region is contained within the first region. Accordingly, it is possible to form a light emitting layer with a doping method by using vapor deposition by color.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: March 11, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinichi Kawato, Satoshi Inoue, Tohru Sonoda
  • Publication number: 20140065835
    Abstract: A flexible polymer or elastomer coated RF return strap to be used in a plasma chamber to protect the RF strap from plasma generated radicals such as fluorine and oxygen radicals, and a method of processing a semiconductor substrate with reduced particle contamination in a plasma processing apparatus. The coated RF strap minimizes particle generation and exhibits lower erosion rates than an uncoated base component. Such a coated member having a flexible coating on a conductive flexible base component provides an RF ground return configured to allow movement of one or more electrodes in an adjustable gap capacitively coupled plasma reactor chamber.
    Type: Application
    Filed: July 30, 2013
    Publication date: March 6, 2014
    Applicant: Lam Research Corporation
    Inventors: Bobby Kadkhodayan, Jon McChesney, Eric Pape, Rajinder Dhindsa
  • Publication number: 20140065837
    Abstract: A method of bonding together at least two aligned layers, at least one having an active surface, in a semiconductor manufacturing process using a holding member having spaced sections. Each layer has a bonding surface opposite a back surface. The method includes preparing at least two bonding pads on the back surface of each layer and positioning close together the bonding surface of each layer. Aligning the bonding pads of the layers together and inserting the aligned layers between sections of at least one holding member and aligning the sections with the bonding pads of the layers. Applying bonding compound to the aligned bonding pads adjacent the aligned sections of the holding member.
    Type: Application
    Filed: August 15, 2013
    Publication date: March 6, 2014
    Applicant: EMAGIN CORPORATION
    Inventor: ILYAS KHAYRULLIN
  • Patent number: 8664116
    Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 4, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Kazuhiko Fuse, Shinichi Kato
  • Publication number: 20140057448
    Abstract: A substrate-conveying roller includes a first shell, a second shell, an internal block, a manifold, and a clearance. The first shell has a plurality of first through holes serving as supply paths for a gas. The internal block is disposed inside the first shell. The manifold is formed in the internal block so as to guide the gas to the first through holes within the region of a specific angle. The clearance is formed so as to guide the gas to the first through holes outside the region of the specific angle. The second shell has second through holes for guiding the gas from the manifold to the first through holes, and is disposed between the first shell and the internal block. The central axes of the first through hole are offset from the central axes of the second through holes.
    Type: Application
    Filed: October 30, 2012
    Publication date: February 27, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Sadayuki Okazaki, Kazuyoshi Honda
  • Patent number: 8658545
    Abstract: A vapor deposition source (60), a limiting plate unit (80), and a vapor deposition mask (70) are disposed in this order. The limiting plate unit includes a plurality of limiting plates (81) disposed along a first direction. At least a portion of surfaces (83) defining a limiting space (82) of the limiting plate unit and surfaces (84) of the limiting plate unit opposing the vapor deposition source is constituted by at least one outer surface member (110, 120) capable of attaching to and detaching from a base portion (85). Accordingly, a vapor deposition device that is capable of forming a coating film in which edge blur is suppressed on a large-sized substrate and that has excellent maintenance performance can be obtained.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: February 25, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinichi Kawato, Satoshi Inoue, Tohru Sonoda
  • Patent number: 8658440
    Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 25, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ji-Hao Liang, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa
  • Patent number: 8658951
    Abstract: In-plane temperature of each substrate is uniformly controlled at the time of heating substrates placed on a plurality of susceptors, respectively. A heat treatment apparatus is provided with susceptors, i.e., conductive members for placing wafers thereon, having an induction heating body electrically divided into a center portion thereof and a peripheral portion thereof; a quartz boat supporting the susceptors arranged in a row; an induction coil, which is arranged inside a processing chamber to surround the circumference of each of the susceptors and configured such that the temperature of the induction coil can be freely adjusted; and a control unit which performs temperature control by changing the ratio between heat value at the center portion of the induction heating body and that at the peripheral portion, by controlling two high frequency currents of different frequencies to be applied to the induction coil from a high frequency current circuit.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: February 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tomihiro Yonenaga, Yumiko Kawano
  • Patent number: 8652360
    Abstract: The present invention aims to provide a method of use for surface-modifying a semiconductor nanocrystal comprising at least the steps consisting in having a semiconductor nanocrystal, the organic coating layer of which is provided, at the outer surface of the nanocrystal, with at least one reactive group G1 that reacts according to a cycloaddition reaction of click chemistry type; and bringing said nanocrystal together with an adjoining material provided at the surface with at least one G2 group complementary to the G1 group with respect to said click chemistry reaction, under conditions favorable to the interaction of said G1 and G2 groups, characterized in that said G1 and G2 groups are respectively an azide and a strained cycloalkynyl radical, or vice versa.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: February 18, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Isabelle Texier-Nogues, Aude Bernardin
  • Publication number: 20140045340
    Abstract: A method of processing a semiconductor workpiece includes placing a back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, and the back surface is in fluid communication with a back region having an associated back gas pressure. The method further includes performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1-Pc1, and performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 13, 2014
    Applicant: SPTS TECHNOLOGIES LIMITED
    Inventors: STEPHEN R. BURGESS, ANTHONY P. WILBY
  • Patent number: 8647439
    Abstract: Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: February 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Publication number: 20140038421
    Abstract: A system and method are disclosed for processing semiconductors. An embodiment comprises a reaction chamber for processing wafers and having walls tapering at an angle that is greater than 0 degrees and less than about 35 degrees from a first end optionally having a diameter of 341 to 380 millimeters to a second end optionally having a diameter of 300 to 340 millimeters at a second end, with gas flow from the first end to the second end, and having at least one deposition injector near the first end of the reaction chamber and having a plurality of injector openings that disperse injection material across a cross section of the reaction chamber for forming a deposition layer.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Lun Kuo, Ming-Te Chen, Hsing-Jui Lee, Yu-Yen Lin, Yen-Chen Lin
  • Publication number: 20140038423
    Abstract: In the present invention, a masking solution is supplied to an edge portion of a front surface of a substrate rotated around a vertical axis to form a masking film at the edge portion of the substrate, a hard mask solution is supplied to the front surface of the substrate to form a hard mask film on the front surface of the substrate, a hard mask film removing solution dissolving the hard mask film is supplied to the hard mask film formed at the edge portion of the substrate to remove the hard mask film formed at the edge portion of the substrate, and a masking film removing solution dissolving the masking film is supplied to the masking film to remove the masking film at the edge portion of the substrate.
    Type: Application
    Filed: July 29, 2013
    Publication date: February 6, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Fumiko IWAO, Satoru SHIMURA, Kousuke YOSHIHARA
  • Publication number: 20140038422
    Abstract: A non-contact edge coating apparatus includes an applicator for applying a coating material on an edge of a solar cell substrate and a control system configured to drive the applicator. The control system may drive the applicator along an axis to maintain a distance with an edge of the substrate as the substrate is rotated to have the edge coated with a coating material. The applicator may include a recessed portion into which the edge of the substrate is received for edge coating. For example, the applicator may be a roller with a groove. Coating material may be introduced into the groove for application onto the edge of the substrate. A variety of coating materials may be employed with the apparatus including hot melt ink and UV curable plating resist.
    Type: Application
    Filed: October 31, 2012
    Publication date: February 6, 2014
    Applicant: SunPower Corporation
    Inventor: SunPower Corporation
  • Patent number: 8642488
    Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Junjun Liu, Eric M. Lee, Dorel L. Toma
  • Patent number: 8637410
    Abstract: Methods for formation and treatment of pure metal layers using CVD and ALD techniques are provided. In one or more embodiments, the method includes forming a metal precursor layer and treating the metal precursor layer to a hydrogen plasma to reduce the metal precursor layer to form a metal layer. In one or more embodiments, treating the metal precursor layer includes exposing the metal precursor layer to a high frequency-generated hydrogen plasma. Methods of preventing a hydrogen plasma from penetrating a metal precursor layer are also provided.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: January 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Anantha K. Subramani, John C. Forster, Seshadri Ganguli, Michael S. Jackson, Xinliang Lu, Wei W. Wang, Xinyu Fu, Yu Lei
  • Publication number: 20140024223
    Abstract: The invention relates to method including operating a plasma atomic layer deposition reactor configured to deposit material in a reaction chamber on at least one substrate by sequential self-saturating surface reactions, and allowing gas from an inactive gas source to flow into a widening radical in-feed part opening towards the reaction chamber substantially during a whole deposition cycle. The invention also relates to a corresponding apparatus.
    Type: Application
    Filed: April 7, 2011
    Publication date: January 23, 2014
    Applicant: Picosun Oy
    Inventors: Vaino Kilpi, Wei-Min Li, Timo Malinen, Juhana Kostamo, Sven Lindfors
  • Patent number: 8633562
    Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: January 21, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Yiming Li
  • Publication number: 20140017903
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first surface. In the method, a stress is applied to the semiconductor substrate to change inter-atomic spacing at the first surface of the semiconductor substrate to a stressed inter-atomic spacing. Then, the semiconductor substrate is processed. Thereafter, the stress is released and the first surface of the processed semiconductor substrate retains the stressed inter-atomic spacing.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Abner Bello, Abhijeet Paul
  • Publication number: 20140000476
    Abstract: The present invention describes the highly advantageous properties of a mixture of thiol-perfluoropolyether (PFPE) molecules with perfluorinated bisphosphonic compounds (BP-PF). This mixture in fact makes it possible to obtain a lipophobic and hydrophobic behaviour on numerous materials, including metals, inter alia gold and alloys thereof. It makes it possible to prevent corrosion, and to limit deposition of soiling and microbiological contamination on these surfaces, while at the same time conferring good mechanical strength and resistance to ageing and to cleaning products. It also makes it possible to lubricate the metal parts that it covers.
    Type: Application
    Filed: December 21, 2011
    Publication date: January 2, 2014
    Applicant: SURFACTIS TECHNOLOGIES
    Inventors: David Portet, Gregory Lecollinet
  • Publication number: 20140004709
    Abstract: Nanoporous polymers with gyroid nanochannels can be fabricated from the self-assembly of degradable block copolymer, polystyrene-b-poly(L-lactide) (PS-PLLA), followed by the hydrolysis of PLLA blocks. A well-defined nanohybrid material with SiO2 gyroid nanostructure in a PS matrix can be obtained using the nanoporous PS as a template for the sol-gel reaction. After subsequent UV degradation of the PS matrix, a highly porous inorganic gyroid network remains, yielding a single-component material with an exceptionally low refractive index (as low as 1.1).
    Type: Application
    Filed: August 7, 2013
    Publication date: January 2, 2014
    Applicant: National Tsing Hua University
    Inventors: Rong-Ming HO, Han-Yu HSUEH, Ming-Shiuan SHE, Hung-Ying CHEN, Shangjr GWO
  • Publication number: 20140004710
    Abstract: A substrate processing apparatus of the present invention includes a substrate placement stage installed in the process chamber, and configured to place the substrate on a substrate placement surface, with a flange provided on its side face; a heating element arranged in the substrate placement stage and configured to heat the substrate; a plurality of struts configured to support the flange from below, and an exhaust unit configured to exhaust an atmosphere in the process chamber, wherein the supporting member is provided between the substrate placement stage and the plurality of struts.
    Type: Application
    Filed: January 16, 2012
    Publication date: January 2, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masakazu Sakata, Hidehiro Yanai
  • Patent number: 8618003
    Abstract: Electronic devices can be prepared by forming a patterned thin film on a suitable receiver substrate. A cyanoacrylate polymer is used as a deposition inhibitor material and applied first as a deposition inhibitor material. The deposition inhibitor material can be patterned to provide selected areas on the receiver substrate where the deposition inhibitor is absent. An inorganic thin film is then deposited on the receiver substrate using a chemical vapor deposition technique only in those areas where the deposition inhibitor material is absent. The cyanoacrylate polymer deposition inhibitor material can be applied by thermal transfer from a donor element to a receiver substrate before a patterned thin film is formed.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 31, 2013
    Assignee: Eastman Kodak Company
    Inventors: Mitchell S. Burberry, David H. Levy
  • Patent number: 8617993
    Abstract: A method is provided for treating the surface of high aspect ratio nanostructures to help protect the delicate nanostructures during some of the rigorous processing involved in fabrication of semiconductor devices. A wafer containing high aspect ratio nanostructures is treated to make the surfaces of the nanostructures more hydrophobic. The treatment may include the application of a primer that chemically alters the surfaces of the nanostructures preventing them from getting damaged during subsequent wet clean processes. The wafer may then be further processed, for example a wet cleaning process followed by a drying process. The increased hydrophobicity of the nanostructures helps to reduce or prevent collapse of the nanostructures.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: December 31, 2013
    Assignee: Lam Research Corporation
    Inventors: Amir A. Yasseri, Ji Zhu, Seokmin Yun, David S. L. Mui, Katrina Mikhaylichenko
  • Publication number: 20130344703
    Abstract: In a film forming method, a coating composition containing film components is coated on a plastic substrate to form a coating film. By irradiating electromagnetic waves to the coating film, the coating film is dried and/or modified to form a film. The film can be a conductor film, a semi-conductor film or a dielectric film. When forming a conductor film, a coating composition containing metallic nanoparticles is used as the coating composition; when forming a semi-conductor film, an organic semi-conductor material is used as the coating composition; and when forming a dielectric film, an organic dielectric material is used as the coating composition.
    Type: Application
    Filed: August 23, 2013
    Publication date: December 26, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masahiro SHIMIZU, Hitoshi Itoh
  • Patent number: 8614500
    Abstract: According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Sato, Hiroyasu Kondo, Naoaki Sakurai, Katsuyuki Soeda, Kenichi Ooshiro, Shuichi Kimura
  • Publication number: 20130330930
    Abstract: A substrate processing apparatus includes: a processing chamber that accommodates a substrate; a heating portion that is provided so as to surround a accommodating region of the substrate within the processing chamber; a gas nozzle that is provided inside the heating portion and that supplies a processing gas to the accommodating region of the substrate; and a gas heating mechanism that is provided inside the heating portion and that supplies the processing gas from an upstream side of the gas nozzle into the gas nozzle. A ratio of a flow channel circumferential length to a flow channel cross-sectional area in a gas flow channel of the gas heating mechanism is larger than a ratio of a flow channel circumferential length to a flow channel cross-sectional area in a gas flow channel of the gas nozzle.
    Type: Application
    Filed: February 22, 2012
    Publication date: December 12, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Shuhei Saido, Daisuke Hara, Takafumi Sasaki