Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 8614500
    Abstract: According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Sato, Hiroyasu Kondo, Naoaki Sakurai, Katsuyuki Soeda, Kenichi Ooshiro, Shuichi Kimura
  • Publication number: 20130330930
    Abstract: A substrate processing apparatus includes: a processing chamber that accommodates a substrate; a heating portion that is provided so as to surround a accommodating region of the substrate within the processing chamber; a gas nozzle that is provided inside the heating portion and that supplies a processing gas to the accommodating region of the substrate; and a gas heating mechanism that is provided inside the heating portion and that supplies the processing gas from an upstream side of the gas nozzle into the gas nozzle. A ratio of a flow channel circumferential length to a flow channel cross-sectional area in a gas flow channel of the gas heating mechanism is larger than a ratio of a flow channel circumferential length to a flow channel cross-sectional area in a gas flow channel of the gas nozzle.
    Type: Application
    Filed: February 22, 2012
    Publication date: December 12, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Shuhei Saido, Daisuke Hara, Takafumi Sasaki
  • Publication number: 20130323934
    Abstract: [Problem] To significantly reduce processing time of a step of adsorbing dye in a porous semiconductor layer on a substrate surface. [Solution] A flow of a dye solution is formed in a gap between solution guide surface (92L, 92R) of a nozzle (20) and a substrate (G) during the treatment, and a porous semiconductor layer of a treated surface of the substrate is subject to dye adsorption treatment in this flow of the dye solution. Furthermore, impact pressure from slit-like discharge openings (88L, 88R) and pressure of turbulent flow in groove-like uneven sections (92L, 92R) act in the vertical direction in addition to the flow of the dye solution. Thus, aggregation and association of the dye are hardly caused on a surface part of the porous semiconductor layer of the treated surface of the substrate, the dye efficiently penetrates deeply into the porous semiconductor layer, and the dye adsorption into the porous semiconductor layer proceeds at high speed.
    Type: Application
    Filed: October 12, 2011
    Publication date: December 5, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Norio Wada, Takashi Terada, Yoshiteru Fukuda, Goro Furutani
  • Patent number: 8598046
    Abstract: The present invention relates to a method and apparatus for the synthesis of nanostructures using at least one solution providing at least one chemical element appropriate for the type of nanostructure, the method comprising the steps of: a) adding (admixing) a reducing agent to the at least one solution, b) bringing a suitable substrate into contact with the at least one solution before or after step a), c) forming nucleation growth sites on the substrate and d) maintaining the temperature at a suitable level for the growth of the nanostructures, characterized by the further steps of e) providing at least one space having at least one dimension in the micron range, e.g. in the range from 1 ?m to 500 ?m, adjacent a surface of the substrate, f) growing said nanostructures in said at least one space, g) periodically separating said nanostructures from the substrate and removing them.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 3, 2013
    Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventors: Vivek Pachauri, Ashraf Ahmad, Kannan Balasubramanian, Klaus Kern
  • Patent number: 8598047
    Abstract: A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O3) are alternately fed into the reaction tubeto generate Al2O3 film on the surface of the wafer. The apparatus also includes supply tubes and for flowing the ozone and TMA and a nozzle supplying gas into the reaction tube. The two supply tubes are connected to the nozzle disposed inside the heater in a zone inside the reaction tube where a temperature is lower than a temperature near the wafer, and the ozone and TMA are supplied into the reaction tube through the nozzle.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 3, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Masanori Sakai, Toru Kagaya, Hirohisa Yamazaki
  • Patent number: 8598018
    Abstract: The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Azdakani, Shafaat Ahmed, Hariklia Deligianni, Dario L. Goldfarb, Stefan Harrer, Hongbo Peng, Stanislav Polonsky, Stephen Rossnagel, Xiaoyan Shao, Gustavo A. Stolovitzky
  • Publication number: 20130316541
    Abstract: The invention relates to a process for manufacturing a self-assembled injection monolayer (SAM) on the surface of a metal supporting member, the SAM comprising molecules with a thiol end group. The manufacturing process of the invention comprises the following steps: a) depositing the SAM of desired molecules on a zone in relief of a buffer; and b) transferring the SAM onto the surface of the supporting member by hot pressing of the zone in relief of the buffer obtained in step a). The invention is applicable in particular to the field of electronics.
    Type: Application
    Filed: February 2, 2012
    Publication date: November 28, 2013
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Mohammed Benwadih, Jamal Tallal
  • Publication number: 20130309876
    Abstract: A method of manufacturing a semiconductor device includes: housing a substrate into a processing chamber; and forming a metal nitride film on the substrate by supplying a source gas containing a metal element, a nitrogen-containing gas and a hydrogen-containing gas into the processing chamber; wherein in forming the metal nitride film, the source gas and the nitrogen-containing gas are intermittently supplied into the processing chamber, or the source gas and the nitrogen-containing gas are intermittently and alternately supplied into the processing chamber, or the source gas is intermittently supplied into the processing chamber in a state that supply of the nitrogen-containing gas into the processing chamber is continued, and the hydrogen-containing gas is supplied into the processing chamber during at least supply of the nitrogen-containing gas into the processing chamber.
    Type: Application
    Filed: November 29, 2011
    Publication date: November 21, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Arito Ogawa
  • Patent number: 8586474
    Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ritwik Chatterjee, Eddie Acosta, Sam S. Garcia, Varughese Mathew
  • Patent number: 8586484
    Abstract: A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hideaki Matsuyama, Takehito Wada
  • Publication number: 20130302992
    Abstract: An apparatus for plasma treatment contains a process vessel provided with a mounting table for mounting a substrate, a first gas supplying unit configured to supply a first gas into the process vessel, a first plasma generating unit configured to convert at least a part of the first gas to a first plasma, a second gas supplying unit configured to supply a second gas into the process vessel, and a second plasma generating unit configured to convert at least a part of the second gas to a second plasma. A height of ea an inlet of the second gas from the mounting table is lower than a height of an inlet of the first gas from the mounting table.
    Type: Application
    Filed: November 16, 2011
    Publication date: November 14, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Nozawa, Caizhong Tian, Masaru Sasaki, Naoki Mihara, Naoki Matsumoto, Kazuki Moyama, Jun Yoshikawa
  • Publication number: 20130302996
    Abstract: Embodiments described herein relate to a method for processing a substrate. In one embodiment, the method includes introducing a gas mixture comprising a hydrocarbon source and a diluent gas into a deposition chamber located within a processing system, generating a plasma from the gas mixture in the deposition chamber at a temperature between about 200° C. and about 700° C. to form a low-hydrogen content amorphous carbon layer on the substrate, transferring the substrate into a curing chamber located within the processing system without breaking vacuum, and exposing the substrate to UV radiation within the curing chamber at a curing temperature above about 200° C.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 14, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Patrick REILLY, Shahid SHAIKH, Tersem SUMMAN, Deenesh PADHI, Sanjeev BALUJA, Juan Carlos ROCHA-ALVAREZ, Thomas NOWAK, Bok Hoen KIM, Derek R. WITTY
  • Publication number: 20130292806
    Abstract: Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer.
    Type: Application
    Filed: May 30, 2013
    Publication date: November 7, 2013
    Inventors: Paul F. Ma, Jennifer Meng Tseng, Mei Chang, Annamalai Lakshmanan, Jing Tang
  • Patent number: 8575665
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
  • Publication number: 20130288480
    Abstract: Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Applicant: Applied Materials, Inc.
    Inventors: ERROL ANTONIO C. SANCHEZ, YI-CHIAU HUANG
  • Publication number: 20130288483
    Abstract: A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically tunable process kit are provided. The dynamically tunable process kit allows one or both of the electrical and thermal state of the process kit to be changed without changing the phyisical construction of the process kit, thereby allowing plasma properties, and hence processing results, to be easily changed without replacing the process kit. The processing chamber having a dynamically tunable process kit includes a chamber body that includes a portion of a conductive side wall configured to be electrically controlled, and a process kit. The processing chamber includes a first control system operable to control one or both of an electrical and thermal state of the process kit and a second control system operable to control an electrical state of the portion of the side wall.
    Type: Application
    Filed: February 13, 2013
    Publication date: October 31, 2013
    Inventors: S.M. Reza Sadjadi, Dmitry Lubomirsky, Hamid Noorbakhsh, John Zheng Ye, David H. Quach, Sean S. Kang
  • Patent number: 8569183
    Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dielectric layers that have been deposited and/or flowed by the application of microwave energy (“MW dielectric layers”). The dielectric layers can be made by providing a substrate in a reaction chamber, flowing a precursor gas mixture (containing atoms that react to form a dielectric material) in the reaction chamber, and then subjecting the gas mixture to microwave energy at a frequency and power density sufficient to cause the atoms of the precursor gas mixture to react and deposit to form a dielectric layer on the substrate. As well, the devices can be made by applying microwave energy to an already-deposited dielectric film at a frequency and power density sufficient to cause the atoms of the deposited dielectric material to flow.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 29, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Robert J. Purtell
  • Publication number: 20130280840
    Abstract: A vapor deposition device (50) in accordance with the present invention is a vapor deposition device for forming a film on a film formation substrate (60), the vapor deposition device including a vapor deposition source (80) that has an injection hole (81) from which vapor deposition particles are injected, a vapor deposition particle crucible (82) for supplying the vapor deposition particles to the vapor deposition source (80), and a rotation motor (86) for changing a distribution of the injection amount of the vapor deposition particles by rotating the vapor deposition source (80).
    Type: Application
    Filed: December 19, 2011
    Publication date: October 24, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Shinichi Kawato, Satoshi Inoue, Satoshi Hashimoto
  • Publication number: 20130280917
    Abstract: A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.
    Type: Application
    Filed: June 14, 2013
    Publication date: October 24, 2013
    Inventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
  • Publication number: 20130273746
    Abstract: A vapor deposition device (50) includes a mask (60) having periodic patterns, and only a region of the mask (60) where a one-period pattern is formed is exposed. A length of the mask base material along a direction perpendicular to a long-side direction of the mask base material is shorter than a length of a film formation substrate (200) along a direction of scanning of the film formation substrate (200). The mask (60) is provided so that the long-side direction of the mask base material is perpendicular to the direction of scanning and that the exposed region is allowed to move in a direction perpendicular to the direction of scanning by rotation of a wind-off roll (91) and a wind-up roll (92).
    Type: Application
    Filed: December 28, 2011
    Publication date: October 17, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Shinichi Kawato, Nobuhiro Hayashi, Tohru Sonoda, Satoshi Inoue
  • Patent number: 8557681
    Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 15, 2013
    Assignee: International Rectifier Corporation
    Inventors: Thomas Herman, Robert Beach
  • Publication number: 20130267098
    Abstract: A plasma processing apparatus is offered which has evacuable vacuum vessel, processing chamber disposed inside the vacuum vessel and having inside space in which plasma for processing sample to be processed is generated and in which the sample is placed, unit for supplying gas for plasma generation into processing chamber, vacuum evacuation unit for evacuating inside of processing chamber, helical resonator configured of helical resonance coil disposed outside the vacuum vessel and electrically grounded shield disposed outside the coil, RF power supply of variable frequency for supplying RF electric power in given range to the resonance coil, and frequency matching device capable of adjusting frequency of the RF power supply so as to minimize reflected RF power. The resonance coil has electrical length that is set to integral multiple of one wavelength at given frequency. The helical resonance coil has feeding point connected to ground potential using variable capacitive device.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 10, 2013
    Inventors: Kenji MAEDA, Ken YOSHIOKA, Hiromichi KAWASAKI, Takahiro SHIMOMURA
  • Publication number: 20130267100
    Abstract: An amount of particles generated when a source material is used is suppressed. A substrate is loaded into a process chamber, and the source material is sequentially flowed into an evaporator, and a mist filter constituted by assembling a plurality of at least two types of plates including holes disposed at different positions to be evaporated and supplied into the process chamber to process the substrate, and then, the substrate is unloaded from the process chamber.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 10, 2013
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Kosuke TAKAGI, Yuji TAKEBAYASHI
  • Publication number: 20130267096
    Abstract: Systems for and methods of laser-enhanced plasma processing of semiconductor materials are disclosed. The method includes supporting a semiconductor material in a processing chamber interior and subjecting the semiconductor material to a plasma process. The method also includes simultaneously heating the wafer surface with a laser beam through a window in the processing chamber to increase the reaction rate of the plasma process. Other methods include performing laser heating of the semiconductor material before or after the plasma process but while the semiconductor material resides in the same chamber interior.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Inventors: Andrew M. Hawryluk, Arthur W. Zafiropoulo
  • Patent number: 8551248
    Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Brian E. Goodlin, Qidu Jiang
  • Patent number: 8551890
    Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Brian E. Goodlin, Qidu Jiang
  • Publication number: 20130260569
    Abstract: An apparatus and method for liquid treatment of wafer-shaped articles comprises a process unit comprising a chuck for holding a wafer-shaped article in a predetermined orientation, and a liquid recovery system that receives used process liquid recovered from the process unit. The liquid recovery system supplies process liquid to a dispenser in the process unit. A supply of fresh process liquid supplies fresh process liquid to the liquid recovery system and also supplies fresh process liquid to a dispenser in the process unit while bypassing the liquid recovery system.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: LAM RESEARCH AG
    Inventors: Michael GANSTER, Philipp ZAGORZ, Alois GOLLER
  • Publication number: 20130260571
    Abstract: The objects of the present invention are to provide a treatment liquid able to inhibit pattern collapse in a microstructure such as a semiconductor device or a micromachine, as well as a method of manufacturing a microstructure using the same. Means to solve the problems is to treat a microstructure with a treatment liquid for inhibiting pattern collapse in a metal microstructure comprising an alkylphosphonic acid or salt thereof in which said alkyl moiety contains 6 to 18 carbon atoms, water, and a water soluble solvent.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 3, 2013
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Hiroshi MATSUNAGA, Kimihiro AOYAMA
  • Publication number: 20130260572
    Abstract: In a continuous processing system, a controller of a heat treatment apparatus calculates a weight of each layer from input target film thicknesses of a phosphorous-doped polysilicon film (D-poly film) and an amorphous silicon film (a-Si film), and calculates activation energy of stacked films based on the calculated weight and activation energy. The controller prepares a stacked film model based on the calculated activation energy and a relationship of a temperature of each zone and film thicknesses of the D-poly film and the a-Si film, and calculates an optimum temperature of each zone by using the prepared stacked film model. The controller controls power controllers of heaters to set a temperature in a reaction tube to be the calculated temperature of each zone and forms stacked films on a semiconductor wafer by controlling a pressure adjusting unit, flow rate adjusting units, etc.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 3, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yuichi TAKENAGA, Yukio TOJO
  • Patent number: 8545631
    Abstract: A mask device, a method of fabricating the mask device with improved reliability, a method of manufacturing a large-sized division mask device by forming a striped aperture parallel to the roll direction, and a method of fabricating an organic light emitting display device (OLED) using the mask device. The mask device includes: at least one mask alignment mark formed on a mask; a blocking region formed on the mask and blocking a deposition material; and an aperture region formed on the mask and through which the deposition material passes, wherein the at least one mask alignment mark is formed outside the aperture region, the aperture region has a stripe pattern, and the roll direction of the mask substrate is parallel to the longitudinal direction of the stripe pattern.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: October 1, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eui-Gyu Kim, Tac-Hyung Kim, Wook Han
  • Patent number: 8546270
    Abstract: An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyun Kim, Ki-Vin Im, Hoon-Sang Choi, Moon-Hyeong Han
  • Publication number: 20130252433
    Abstract: A method of manufacturing a semiconductor device includes: accommodating a substrate having an oxide film formed thereon into a processing chamber; supplying a process gas to the substrate; performing a preprocessing step in which the process gas is excited in a state that a pressure within the processing chamber is kept at a first pressure and an electric potential of the substrate is kept at a first electric potential; and performing a main processing step by which the process gas is excited in a state that the pressure within the processing chamber is kept at a second pressure and the electric potential of the substrate is kept at a second electric potential, wherein the first pressure is lower than the second pressure and the first electric potential is lower than the second electric potential.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 26, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Tatsushi UEDA
  • Publication number: 20130252435
    Abstract: An object of the present invention is to form a good thin film while suppressing generation of foreign substances in a low temperature region.
    Type: Application
    Filed: March 19, 2013
    Publication date: September 26, 2013
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Satoshi SHIMAMOTO, Yugo ORIHASHI, Yoshitomo HASHIMOTO, Yoshiro HIROSE
  • Publication number: 20130252424
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Publication number: 20130252434
    Abstract: A method of manufacturing a semiconductor device includes carrying a substrate into a process container, forming a thin film on the substrate by supplying a source gas into the process container with the substrate accommodated therein, performing a first modification treatment to a byproduct adhered to an inside of the process container by supplying an oxygen-containing gas and a hydrogen-containing gas into the heated process container under a pressure less than an atmospheric pressure, while accommodating the thin film-formed substrate in the process container, carrying the thin film-formed substrate out of the process container, and performing a second modification treatment to the byproduct adhered to the inside of the process container after the first modification treatment by supplying an oxygen-containing gas and a hydrogen-containing gas into the heated process container under the pressure less than the atmospheric pressure, while not accommodating the substrate in the process container.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 26, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuhiro YUASA, Naonori AKAE
  • Patent number: 8541317
    Abstract: A substrate is mounted onto an elevated substrate support of a substrate carrier plate. The substrate carrier plate with the substrate is then placed in a plasma reactor. Due to the elevated substrate support, both opposite sides of the substrate are exposed to the plasma and are therefore coated with an electrical passivation layer.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: September 24, 2013
    Assignee: ABB Technology AG
    Inventors: Kranthi Akurati, Magnus Kunow, Andreas Zimmermann, Ron Jervis
  • Patent number: 8540543
    Abstract: The invention is a method for continuously manufacturing a liquid crystal display panel. In the method, the manufacturing step and the inspection step are performed on a continuous feeder. The inspection step includes applying a line-shaped light beam from one side with respect to the feeder to the liquid crystal display panel being fed; and imaging a region irradiated with the line-shaped light beam in the liquid crystal display panel, wherein the imaging is continuously performed in a line pattern parallel to a width direction of the feeder and performed at a position that is on another side with respect to the feeder and tilted at a predetermined angle to a feed direction of the feeder or a direction opposite thereto with respect to a direction in which the line-shaped light beam is applied.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 24, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Satoshi Hirata, Takuya Nakazono, Tomokazu Yura
  • Publication number: 20130244922
    Abstract: The present disclosure provides azeotropic and azeotrope-like compositions comprised of methylperfluoropentene ethers and at least one of methanol, ethanol, 2-propanol, hexane, heptane, trans-1,2-dichloroethylene, ethyl formate, methyl formate, HFE-7100, HFE-7200 and 1-bromopropane or combinations thereof. The present disclosure also provides for methods of use for the azeotropic and azeotrope-like compositions.
    Type: Application
    Filed: September 11, 2012
    Publication date: September 19, 2013
    Applicant: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Joan Ellen Bartelt, Barbara Haviland Minor
  • Publication number: 20130240871
    Abstract: A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer.
    Type: Application
    Filed: May 6, 2011
    Publication date: September 19, 2013
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Tatsuya Shimoda, Eisuke Tokumitsu, Takaaki Miyasako, Toshihiko Kaneda
  • Patent number: 8536073
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 17, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Patent number: 8536491
    Abstract: A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of rotatable heaters arranged and operative to heat the chamber. In one embodiment, spacing between the sidewall heaters is adjustable. The heating system controls temperature variations within the chamber and promotes uniform film deposit thickness on the wafers.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zin-Chang Wei, Hsin-Hsien Wu, Chun-Lin Chang
  • Patent number: 8535571
    Abstract: Water-soluble electrically conductive polymers and a composition comprising such polymers are provided. Also, an electrically conductive layer or film formed from the composition, and articles comprising the electrically conductive layer or film are provided. The electrically conductive polymers according to the present disclosure have one or more hydrophilic side chains. Hydrophilic side chains are covalently bonded to the conductive polymers, which allow the polymer to be stable at high temperature. Thus, the stability of electrical conductivity is prolonged. Depending on the concentration of hydrophilic side chains, the conductivity may be changed. The hydrophilic side chains provide a successful way to fabricate a ductile film exhibiting tunable conductivity. Furthermore, high levels of surface-resistance uniformity can be achieved in the field of coating technology that uses eco-friendly water-based solvents to uniformly and quickly coat the conductive polymer on to plastic film surfaces.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 17, 2013
    Assignee: Korea University Research and Business Foundation
    Inventor: Dong Hoon Choi
  • Patent number: 8536065
    Abstract: Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a method of processing a substrate in a processing chamber is provided. The method comprises providing a substrate in a processing volume, flowing a hydrocarbon containing gas mixture into the processing volume, generating a plasma of the hydrocarbon containing gas mixture by applying power from an RF source, flowing a boron containing gas mixture into the processing volume, and depositing a boron containing amorphous carbon film on the substrate in the presence of the plasma, wherein the boron containing amorphous carbon film contains from about 30 to about 60 atomic percentage of boron.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Martin Jay Seamons, Sudha Rathi, Kwangduk Douglas Lee, Deenesh Padhi, Bok Hoen Kim, Chiu Chan
  • Publication number: 20130237064
    Abstract: A method of manufacturing a semiconductor device, includes: forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a raw material gas to a substrate in a process chamber, exhausting the raw material gas remaining in the process chamber through an exhaust line, supplying an amine-based gas; and exhausting the amine-based gas through the exhaust line with the supply of the amine-based gas stopped. A degree of valve opening of an exhaust valve disposed in the exhaust line is changed in multiple steps in the process of exhausting the amine-based gas.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 12, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kaori KIRIKIHIRA, Yugo ORIHASHI, Satoshi SHIMAMOTO
  • Publication number: 20130237063
    Abstract: A split-pumping system and method for semiconductor fabrication process chambers is provided. The split pumping method may provide two separate exhaust paths, each configured to evacuate a different process gas. The exhaust paths may be configured to not evacuate process gases other than the process gas that the exhaust path is configured to evacuate.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 12, 2013
    Inventors: SESHASAYEE VARADARAJAN, ANTONIO XAVIER, Ramesh CHANDRASEKHARAN, DIRK RUDOLPH
  • Patent number: 8530269
    Abstract: A method of forming a polymer device including the steps (i) of depositing on a substrate a solution containing a polymer or oligomer and a crosslinking moiety, to form a layer, and, (ii) curing the layer formed in step (i) under conditions to form an insoluble crosslinked polymer, wherein the crosslinking moiety is present in step (i) in an amount in the range of from 0.05 mol % to 5 mol % based on the total number of moles or repeat units of the polymer or oligomer and the crosslinking moiety in the solution.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: September 10, 2013
    Assignee: Cambridge Enterprise Ltd
    Inventors: Lay-Lay Chua, Peter Kian-Hoon Ho, Richard H. Friend
  • Patent number: 8525123
    Abstract: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Kam L. Lee, Robert L. Wisnieff
  • Patent number: 8524611
    Abstract: In manufacturing a semiconductor device, a first chamber is provided. An opening couples the first chamber to a first environment through which at least one substrate can pass. A first seal environmentally isolates the first chamber from the first environment. A process chamber is coupled to the first chamber. Another seal environmental isolates the first and the process chambers. The substrate is placed within the first chamber, and the first chamber and the outside environment are isolated. The second opening is opened, and the substrate moves into the semiconductor process chamber. The first chamber is again environmentally isolated from the second volume. A semiconductor processing step is performed on the substrate within the processing chamber. While the substrate is processed, the substrate is rotated and translated through the processing chamber.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 3, 2013
    Assignee: Solyndra LLC
    Inventor: Ratson Morad
  • Publication number: 20130224963
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus includes a substrate stage, a transfer unit, and a control unit. A substrate is settable on the substrate stage. The transfer unit is configured to transfer a pattern having an uneven configuration onto a major surface of the substrate by attachably and removably holding a template. The pattern is provided in the transfer surface. The control unit is configured to acquire information relating to a number of foreign objects on the major surface prior to the transferring of the pattern. The control unit adds the number for a plurality of the substrates including the pattern transferred by the transfer unit. The control unit causes the transfer unit not to implement the transferring of the pattern in the case where the sum has reached the upper limit.
    Type: Application
    Filed: August 30, 2012
    Publication date: August 29, 2013
    Inventors: Masayuki HATANO, Hiroshi TOKUE
  • Publication number: 20130224952
    Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang