Abstract: An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials.

Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

Abstract: Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Abstract: A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile hydrophobic film. The ILD layer further includes a low-k dielectric layer, and the single tensile hydrophobic film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.

Abstract: A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal layer. A sacrificial oxide layer can be formed on the IMD layer, and a planarization process can be performed on the sacrificial oxide layer and the IMD layer to substantially eliminate a height difference of the IMD layer.

Abstract: A method for producing an interconnection structure including at least one insulating layer having a low dielectric constant and at least one metal connection element coated with a support layer and capable of connecting to at least one conductive area of a microelectronic device. The interconnection structure has an improved low dielectric constant. The interconnection structures may be a metal interconnection structure in a variety of integrated circuits.

Abstract: A packaged electronic device includes a die, a flexible circuit structure, and a barrier film disposed on the die. The die includes die circuitry and electrical contacts. The flexible circuit structure is bonded directly to the die, and includes electrical conductors encapsulated by structural layers. Each electrical conductor contacts a respective electrical contact. The electronic device is encapsulated by the barrier film and one or more of the structural layers.

Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

Abstract: A method of making an integrated circuit comprises providing a substrate and forming a structure on the substrate comprising a first enclosed portion of a carbon material and a second portion of the carbon material, wherein an intersection of the first and second portion of the carbon material has a defined dimension. The method further comprises processing the substrate with a plasma comprising hydrogen in order to etch the second portion of the carbon material, wherein the defined dimension of the intersection of the first and second portion of the carbon material substantially suppresses etching of the first enclosed portion of the carbon material in a self-limiting way.

Abstract: In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.

Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices.

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.

Abstract: A first insulating film is formed on or above a substrate, and a first conductor is formed in an upper portion of the formed first insulating film. Then, a second insulating film is formed on the first insulating film so as to cover the first conductor. Then, a film quality alteration process is performed for the second insulating film. Moreover, a third insulating film is formed on the second insulating film, and a curing process is performed for the formed third insulating film.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.

Abstract: Films having high hermeticity and a low dielectric constant can be used as copper diffusion barrier films, etch stop films, CMP stop films and other hardmasks during IC fabrication. Hermetic films can protect the underlying layers, such as layers of metal and dielectric, from exposure to atmospheric moisture and oxygen, thereby preventing undesirable oxidation of metal surfaces and absorption of moisture by a dielectric. Specifically, a bi-layer film having a hermetic bottom layer composed of hydrogen doped carbon and a low dielectric constant (low-k) top layer composed of low-k silicon carbide (e.g., high carbon content hydrogen doped silicon carbide) can be employed. Such bi-layer film can be deposited by PECVD methods on a partially fabricated semiconductor substrate having exposed layers of dielectric and metal.

Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over the substrate layer.

Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract: Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

Abstract: A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided.

Abstract: Improved methods for preparing a low-k dielectric material on a substrate using microwave radiation are provided. The use of microwave radiation allows the preparation of low-k films to be accomplished at low temperatures. According to various embodiments, microwave radiation is used to remove porogen from a precursor film and/or to increase the strength of the resulting porous dielectric layer. In a preferred embodiment, methods involve (a) forming a precursor film that contains a porogen and a structure former on a substrate, (b) exposing the precursor film to microwave radiation to remove the porogen from the precursor film to thereby create voids within the dielectric material and form the porous low-k dielectric layer and (c) exposing the dielectric material to microwave radiation in a manner that increases the mechanical strength of the porous low-k dielectric layer.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.

Abstract: Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer.

Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

Abstract: A semiconductor device manufacturing method including: forming a first interlayer insulating film on a semiconductor substrate; forming a first hole in the first interlayer insulating film; forming a barrier film inside the first hole; filling a conductive material in the first hole to form a first plug; forming a second interlayer insulating film on the first interlayer insulating film; forming a second hole reaching the first plug in the second interlayer insulating film; selectively etching an upper end of the barrier film inside the second hole; and forming a second plug for connection to the first plug inside the second hole.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.

Abstract: A sensing device includes an optical cavity having two substantially opposed reflective surfaces. At least one nanowire is operatively disposed in the optical cavity. A plurality of metal nanoparticles is established on the at least one nanowire.

Abstract: A method for fabricating a dielectric layer structure includes providing a substrate, forming at least a low-k dielectric layer on the substrate, forming a single tensile layer on the low-k dielectric layer, and performing a moisture preventing treatment on the single tensile film. The single tensile layer possesses a stress comparative to a stress of the low-k dielectric layer and a hydrophobic characteristic that prevents itself from absorbing moisture.

Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.

Abstract: A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device regions (224).

Abstract: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.

Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

Abstract: A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a contact pad at a first main side of the first substrate; providing a second substrate with a main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the contact pad.

Abstract: The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures.

Abstract: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

Abstract: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided.

Abstract: Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.

Abstract: A power-supply wiring structure for a multilayer wiring according to an embodiment of the present invention includes one intermediate wiring layer with a first direction set as a priority wiring direction including a position converting and connecting wire, which has crossing-position forming sections formed in crossing positions of upper-layer power supply wires and lower-layer power supply wires of the same kind and projecting sections projecting from the crossing-position forming sections to sides of upper-layer power supply wires of different kinds, and includes a wire connecting section that connects between the upper layer wires and the crossing-position forming section and connects between the projecting section and the lower layer wires via vias.

Abstract: Methods of forming electrical interconnects include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insulating layer is then formed on the first electrically insulating layer. The second electrically insulating layer is then etched to expose the first electrically insulating layer and then a third electrically insulating layer is formed on the first electrically insulating layer. The first and third electrically insulating layers are then etched to define a contact hole therein which exposes a portion of the first electrically conductive layer. A barrier metal layer is then formed. The barrier metal layer is preferably formed to extend on the third electrically insulating layer and on the exposed portion of the first electrically conductive layer.

Abstract: A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film, a second wiring layer formed in the second insulating film and coupled to the first wiring layer through a first connection section, and a third insulating film formed above the second wiring layer and the second insulating film and serving as one of an interlayer insulating film and a passivation film, and at least one of the first and third insulating films being one of a film formed mainly of SiON, a film formed mainly of SiN, and a laminated film being the films formed mainly of SiON or SiN respectively.