Abstract: The present invention provides a semiconductor device and manufacturing method of the semiconductor device which can prevent breaks in an interlayer insulation film (12) and electrode (13) that arise with bonding while maintaining bonding strength. A semiconductor element (1) mounted on a semiconductor device including an interlayer insulation film (12) which has an aperture part (123) having an opening shape which is defined by an extension part (121) which covers the gate electrode (116) and extends in the first direction, a connection part (122), the extension part (121) and the connection part (122) which connects at fixed intervals in the first direction a pair of extension parts (121) which are adjacent to the second direction, and which exposes a main surface of a base region (112) and a main surface of an emitter region (113).

Abstract: A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other.

Abstract: A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line.

Abstract: A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.

Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a paddle, an inner post adjacent to the paddle, a jumper pad, and an outer post, with the jumper pad between the inner post and the outer post; mounting an integrated circuit over a paddle first side, the paddle first side co-planar with the outer post; connecting a first jumper interconnect between the integrated circuit and the jumper pad; connecting a second jumper interconnect between the jumper pad and the outer post; and forming an encapsulation over paddle, the integrated circuit, the first jumper interconnect, the jumper pad, and the second jumper interconnect.

Abstract: A semiconductor device includes contact structures and conductive wires formed over the contact structures and coupled to the respective contact structures. Part of each of the conductive wires crosses the contact structure.

Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.

Abstract: A microelectronic package includes a substrate having a first region, a second region, a first surface, and a second surface remote from the first surface. At least one microelectronic element overlies the first region on the first surface. First electrically conductive elements are exposed at one of the first surface and the second surface of the substrate within the second region with at least some of the first conductive elements electrically connected to the at least one microelectronic element. Substantially rigid metal elements overlie the first conductive elements and have end surfaces remote therefrom. A bond metal joins the metal elements with the first conductive elements, and a molded dielectric layer overlies at least the second region of the substrate and has a surface remote from the substrate. The end surfaces of the metal elements are at least partially exposed at the surface of the molded dielectric layer.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

Abstract: Semiconductor devices comprising a flip-chip having passive circuits such as spiral inductors on the back side are disclosed. Provision is made for connection with the spiral inductors using vias and/or bondwires. Further aspects of the invention provide for methods of making such devices.

Abstract: A semiconductor device includes a first semiconductor device and second semiconductor device stacked on the first semiconductor device. The first semiconductor device includes a first interconnect substrate, a first semiconductor element provided on an upper surface of the first interconnect substrate, a first electrode provided on the upper surface of the first interconnect substrate, and an insulating layer having an opening portion through which part of the first electrode is exposed. The second semiconductor device includes a second interconnect substrate, a second semiconductor element provided on an upper surface of the second interconnect substrate, a second electrode provided on a lower surface of the second interconnect substrate, and an inter-device connection terminal connected to the second electrode. Part of the first electrode exposed through the opening portion has a smaller area than an area of the opening portion.

Abstract: A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.

Abstract: A memory device having die-stacking modules that are interchangeable within a Package-on-Package (PoP) and provide separate Chip Enable (CE) signals for all memory die in the die-stacking modules.

Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

Abstract: After forming a pressure-bonded ball and a ball neck by bonding an initial ball to a pad, a capillary is moved upward, away from a lead, and then downward, thereby the ball neck is trodden on by a face portion that is on the lead side of the capillary. Subsequently, the capillary is moved upward and then toward the lead until the face portion of the capillary is positioned above the ball neck, thereby a wire is folded back toward the lead. Then, the capillary is moved downward such that a side of the wire is pressed by the capillary against the ball neck that has been trodden on. After the capillary is moved obliquely upward toward the lead and then looped toward the lead, the wire is pressure-bonded to the lead.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a horizontal ridge at a lead top side; forming a connection layer having an inner pad and an outer pad directly on the lead top side, the inner pad having an inner pad bottom surface; mounting an integrated circuit over the inner pad; applying a molding compound, having a molding bottom surface, over the integrated circuit, the inner pad, and the outer pad; and applying a dielectric directly on the molding bottom surface and the inner pad bottom surface.

Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

Abstract: Provided is a lead frame that may include a frame, a lead structure, and a dam bar. The frame may include a plurality of openings configured to receive semiconductor chips. The lead structure may be in the openings. The lead structure may also include inner leads and outer leads. The inner leads may be configured to electrically connect to the semiconductor chips and the outer leads may extend from the inner leads. In example embodiments, the lead structure may extend in a first direction. The dam bar may be arranged between the inner leads and the outer leads. In accordance with example embodiments, the dam bar may extend along a second direction which is substantially perpendicular to the first direction. In example embodiments, the dam bar may have a first strength-reinforcing portion extending along the second direction. Also provided is a semiconductor package having the lead frame.

Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

Abstract: A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at least a respective first microelectronic element having a face and a respective second microelectronic element having a face overlying and parallel to a face of the first microelectronic element. Each of the first and second microelectronic elements has edges extending away from the respective face. A plurality of traces at the respective face extend about at least one respective edge. Each of the first and second stacked subassemblies includes contacts connected to at least some of the plurality of traces. Bond wires conductively connect the contacts of the first stacked subassembly with the contacts of the second stacked subassembly.

Abstract: All interface pins for transmitting and receiving a signal having a predetermined function of a semiconductor integrated circuit element are formed on an outer periphery of the semiconductor integrated circuit element along one side of the semiconductor integrated circuit element. The one side of the semiconductor integrated circuit element is adjacent to two of sides of a BGA substrate, the two sides being not parallel to the one side. Of balls provided on the BGA substrate, balls electrically connected to the interface pins for transmitting and receiving a signal having a predetermined function are provided between the one side of the semiconductor integrated circuit element and the two sides of the BGA substrate.

Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Abstract: A semiconductor device and a method of fabricating the same. An interposer used for the semiconductor device includes integrated circuits therein to realize the functions of a decoupling capacitor, an ESD preventing circuit, an impedance matching circuit, and termination. The semiconductor device may include a semiconductor die with a through silicon via (TSV) structure having two or more through electrodes that pass through the semiconductor die, in which each of the through electrodes are connected to a respective bond pad of the semiconductor die.

Abstract: A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor to substrate to a second predetermined thickness, thereby exposing the bottom of the hole.

Abstract: A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern, and a first hard mask. The second conductive structure is formed in a second region of the substrate and has a thickness substantially the same as that of the first conductive structure. The second conductive structure includes a second polysilicon layer pattern, a second conductive layer pattern having a resistance smaller than that of the second polysilicon layer pattern and having a thickness different from that of the first conductive layer pattern, and a second hard mask.

Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Abstract: A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals coupled to the lands, the bond terminals being wire-bonded to respective ones of the die pads, and at least one capacitor having respective terminals mounted to respective ones of the lands.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die disposed within the die receiving through hole; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.

Abstract: A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures.

Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.

Abstract: A wiring structure may include a first wiring having a first width that extends in a first direction, and a second wiring intersecting the first wiring, the second wiring extending in a second direction and having a second width that is equal to or less than the first width. Furthermore, the first wiring may have a third width that is smaller than the first width and the second wiring may have a fourth width that is smaller than the second width. Portions of the first and second wirings having the third and fourth widths may extend from an intersecting region in which the first wiring and the second wiring intersect each other.

Abstract: In one embodiment, a semiconductor package includes an isolating container having a recess, which forms an inner membrane portion and an outer rim portion. The rim portion is thicker than the membrane portion. The package includes a semiconductor chip disposed in the recess and a backplane disposed under the membrane portion of the isolating container.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A semiconductor arrangement includes first and second integrated circuits (dies), an electrically conductive intermediate element, and one or more bond conductors. The first and the second integrated circuits are arranged in a package. The first integrated circuit has a first contact pad. The second integrated circuit has a second contact pad. The intermediate element is disposed on the second contact pad. The conductors electrically connect the first and the second integrated circuits. At least one of the bond conductors has a first end electrically connected to the first contact pad, and a second wedge shaped end electrically connected to the intermediate element. The bond conductor is made of a first material and the intermediate element is made of a second material which is softer than the first material.

Abstract: Provided are a method of forming a conductive layer on an inner portion of a through-electrode in which uniform adhesion property of plating in the inner portion of a through-hole is enhanced and a tact time is short, and a semiconductor device. The method of forming a conductive layer includes: a first plating step of forming a first plating layer on the inner portion of the through-hole; a plating suppression layer forming step of forming a plating suppression layer including a material different from a material of the first plating layer in an opening portion of the through-hole after the first plating step; and a second plating step of forming a second plating layer by plating on the inner portion of the through-hole after the plating suppression layer forming step.

Abstract: A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Abstract: A solid-state imaging device includes an imaging element and a logic element. The imaging element includes a first semiconductor substrate, a first wiring layer, and a first metal layer, in which a pixel region which is a light sensing surface is formed. The logic element includes a second semiconductor substrate, a second wiring layer, and a second metal layer, in which a signal processing circuit that processes a pixel signal obtained at the pixel region is formed. The logic element is laminated to the imaging element so that the first metal layer and the second metal layer are bonded to each other, and the first metal layer and the second metal layer are formed on a region excluding a region in which a penetrating electrode layer penetrating a bonding surface of the imaging element and the logic element is formed.

Abstract: A discrete circuit component has copper block electrodes and that utilizes a simple copper substrate as the basis for the component. The component is made by providing an electrode separation hole preformed in the main substrate. The electrode separation hole results in a simple fabrication for the construction of the discrete component product. With the presence of the electrode separation hole, two solid blocks of copper automatically come into shape for each fabricated device at the final phase of production when each device is cut loose from the main production matrix.

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract: Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient conductive polymer material, wherein the elements traverse the insulating layer to a given depth, and are connected to at least one conductive line of a given interconnection level.

Abstract: A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit.