Abstract: A software decoder for converting standard composite video to RGB color components without a phase-locked loop. Subcarrier phase recovery for each video line is accomplished by performing a single DFT computation on the color burst samples for the frequency closest to the subcarrier frequency. The recovered subcarrier phase is added for each line to the orthogonal subcarriers which are mixed with the modulated chrominance for decoding of color difference signals I and Q. Digital composite video capture and store circuitry may be used to buffer the acquisition of real-time video to the speed of a DSP used for software processing. Interpolation can be used in the processing of digital composite video to improve vertical line alignment. Multiple composite video formats, such as NTSC and PAL, can be decoded with minor modifications in the software decoder operation.

Abstract: A plurality of data items are received in each frame period, and a digital signal processor (DSP) checks a flag corresponding to each data item in each frame period before the DSP applies processing to the received data. When the checked flag allows the corresponding data item to be processed, the process is performed. When the execution of the process is finished, the flag is reset. When all the flags are reset, the DSP enters a sleep state.

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: The invention relates to a television set which offers additional functions. For this purpose the television set has a screen saver.

Abstract: A semiconductor device has a multiplicity of DAC channels for performing digital-to-analog conversion of video signals. Signal processing means for delaying processing of signals by a predetermined delay time is provided in at least one DAC channel. The signal processing means functions as a phase inversion means to reduce cross talks between the DAC channels. The signal processing means also functions as a delay circuit to reduce voltage fluctuations in the power supply.

Abstract: An analog-to-digital converter for converting an analog television signal to a signal in compliance with a digital encoding standard is provided.

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: A television control system and method of controlling a television are disclosed. The system includes a host device in communication with one or more televisions. Each of the host devices and televisions use infrared transmitters and receivers. The host device, which may be provided in the form of a computer, receives inputs from a variety of devices, and generates command signals for transmission to each of the televisions. Each of the televisions receive the command signal, as by infrared transmission, and performs the commanded function. Once the commanded function is successfully performed, each of the televisions generates and transmits a confirmation signal to the host device to notify the host device, and ultimately the user, that the requested function has been performed.

Abstract: In a display device, under a analog display mode, an analog image signal amplified by an analog amplifier is outputted to a liquid crystal display panel. Under an digital display mode, after being processed by a signal processing circuit, the digital image signal is outputted to the liquid crystal display panel through a DA converter and an amplifier. For writing a “white” image signal, the signal processing circuit converts the input digital signal so that all bits of the signal are a “1.” Also, for writing a “black” image signal, the signal processing circuit converts the input digital signal so that all bits of the signal are a “0.

Abstract: An arrangement for processing video signals comprises at least one linear filter and at least one non-linear filter with inputs for an input signal and selection means for receiving output signals of the at least one linear and of the at least one non-linear filter and for generating a selected output signal which corresponds to a selected one of the output signals whereby the selection is performed according to a predetermined rank order. The arrangement can be used in various video signal processing applications, especially image restoration or noise reduction, image or pattern recognition, image compression, image enhancement (contour sharpening or softening), image interpolation (up or down sampling), and flicker compensation.

Abstract: High efficiency coding method and apparatus of a video data, in which even from video data in a fade-in or fade-out state, coded video data which does not cause a deterioration of a picture quality upon decoding of said video data can be obtained. When the image based on the video data is in the fade-in or fade-out state and many outline components are included in the image, a motion vector is detected from the luminance adjusted video data obtained by adjusting the luminance of the video data. When the number of outline components included in the image is small, the motion vector is directly detected from the video data and the video data is encoded by a motion compensation prediction according to the motion vector.

Abstract: This invention is an apparatus and method for processing television signals and in particular high quality video type signals in analog or digital form. The preferred embodiments utilizes digital storage along with oversampling, interpolation and various filtering in recursive and nonrecursive form to provide fixed or variably delayed output video signals wherein the artifacts and distortion of the video is kept to low levels.

Abstract: In a video signal capturing apparatus with a simple construction capable of distinguishing fields in units of a color field, a separation circuit separates from input video signals, vertical synchronizing signals that lead fields in a one-to-one relationship. A field counter formed by, for example, a scale-of-four counter, counts the number of vertical synchronizing signals. Based on the count value of the field counter and values set in a register, a timing generating circuit performs data capture in such a manner that color fields are distinguished from each other. If color field 3 is to be captured, a value “3” is set the register. The timing generation circuit compares a count value from the field counter with the set value “13”. When the count value equals 3, the timing generation circuit starts capture of digital video data in the determined field. An even-odd number determining circuit may be provided for distinguishing (i.e.

Abstract: An upgradable television, in accordance with the present invention, includes a plurality of modules for providing operating functions for the upgradable television, each module capable of identifying itself to a processor. The processor is coupled to each of the modules. The processor is for recognizing changes in the modules in accordance with the identification of the modules. A receiver is operatively connected to the processor for receiving information for upgrading the upgradable television in accordance with new modules introduced into the upgradable television. A method for upgrading is also described.

Abstract: A video information processing apparatus for selecting a representative video image from a group of video images in dependence upon a frequency of occurrence of a plurality of possible values of at least one image property.

Abstract: In order to be able to identify television or video images (V1,V2) as identical, predeterminable parameters (H1, H2) of the images (V1, V2) to be tested are compared with each other. Images whose parameters, preferably the average brightness (H1, H2), fall within a predeterminable tolerance range, are identified as identical images. Thus, e.g. in a television reception equipment, particularly a mobile one, the images of all receivable transmitters are tested. Images identified as identical are allocated to the same transmitters or the same programs, the channels of which are stored as alternative channels. When there is bad reception or bad image quality an alternative channel is switched to.

Abstract: Digital filter for filtering a digital input signal with a variable filter length (1), it being possible to switch over the filter length (1) of the digital filter (8) as a function of a variable input clock frequency (fin) of the digital input signal without the ratio between the input clock frequency (fin) and an output clock frequency (fout) of the filtered digital output signal which is output by the digital filter (8) changing.

Abstract: A method and apparatus for sectioning an image into a plurality of regions, by which regions of an image having various features can be extracted stably in a form similar to what humans can perceive, are provided.

Abstract: A detector circuit (1) for detecting the presence or absence of a television (2) on an output (3) of a video DAC (4) comprises a comparator (11) for comparing a voltage developed by the video signal on a control resistor R2 with a reference voltage of 0.5 volts. The resistor R2 is of 75 ohms and matches the internal impedance R1 of 75 ohms of the television (2). A latch (12) latches the output from the comparator (11) onto an output pin Q when the voltage developed across the control resistor R2 is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television (2) the voltage developed across the control resistor R2 is 0.35 volts, which pulls the output of the comparator (11) low, while in the absence of a television (2) the voltage developed across the control resistor R2 is 0.7 volts which pulls the output of the comparator (11) high.

Abstract: Coded image data having a DTS (decode time stamp) appended for each frame are written into an input buffer. A portion of the storage area of the input buffer is scanned to produce identification information (ID) for each frame of image data. For each frame of image data, the ID, DTS, storage location in the buffer and coding type are held in the form of a mapping table. The system time clock (STC) is compared with the DTSs in the table. When a match occurs, the storage location for the corresponding frame of image data is read from the table and sent to a decoder, which in turn reads the corresponding image data from the buffer and decodes it.

Abstract: An information-processing device receives and processes predetermined program data. The information-processing device includes an extracting unit for extracting image data and audio data of a program selected by a user, an obtaining unit for obtaining information related to the selected program, and a setting unit for setting a control parameter for controlling an image data display or an audio data output of the selected program in accordance with the related information.

Abstract: A signal processing device contains a plurality of processing elements with inputs and outputs coupled via a switch-matrix for communication of signal streams between a set of processes. An arbiter selects the connections made by the switch-matrix. The arbiter makes allocations of inputs and outputs that are to be connected to each other in each of successive time-slots. The allocations for communication of signal streams between the set of processes for a plurality of time-slots are made in advance. The arbiter can also receive requests for making further connections between inputs and outputs. In that case, the arbiter makes said further connection in a time-slot in which the requested inputs and outputs are not used by the set of processes. A method of planning is provided which ensures that full utilization of the switch-matrix is possible.

Abstract: Each of plural image processing means is informed of address information of storage means in which image data to be read is stored upon request of the image data to be read by each of the plural image processing means. Consequently, each of the image processing means can read each of image data to be read directly from the storage means based on the informed address information so as to subject it to predetermined image processing. Thus, it is possible to perform plural independent image processing in parallel at a high speed with the simple configuration.

Abstract: A letter-box filtering circuit and a method of using the same that includes a preprocessing filter circuit and a filtering circuit to reduce or correct the round-off errors generated when displaying an image of 16:9 on a screen of 4:3 in a digital image processing. The letter-box filtering circuit can display the down sampled image based on the 16:9 image without any distortion or reduced distortion.

Abstract: Simplifying functions representing raised sine or cosine curves to functions representing simple sine or cosine curves makes it possible to implement an electrical equivalent circuit for a ramp generator. The core of the ramp generator with an output power level controller is second-order direct-form feedback structure (60), which forms a digital sinusoidal oscillator. The initial values of two state variables x2(n), x2(n+1) of the oscillator are chosen so that they both contain a predetermined first constant value. This first constant value will emerge as the amplitude value of the pure sine wave generated by the oscillator. Particularly the first constant value is equal to the desired nominal level A of the ramp minus the starting level. A second constant value (A+dc) is added to the oscillator output. The added result is scaled (66) so that the nominal power level is A. A multiplexer (67) keeps the power level between the ramps constant.

Abstract: A TV receiver with selectable signal processing systems in which main controller 103 selects a proper signal processing system according to signal processing unit 120 based on the results of monitoring the type and the number of the input signals by input signal monitor 102 and the monitor result for user's request by signal display monitor 123. Main controller 103 downloads the instruction program from program memory 104, and then transfers the instruction program to signal processing unit 120. Accordingly, signal processing unit 120 performs one unit of the three-dimensional Y/C separation, two units of the two-dimensional Y/C separations or three units of the one-dimensional Y/C separation on the NTSC video signal.

Abstract: A digital AV signal processing apparatus includes a buffer for storing digital data input to the digital AV signal processing apparatus, and outputting the digital data as output digital data, a D/A converter for converting the output digital data to analog data, a voltage-controlled oscillator for generating a clock signal to control a conversion rate of the D/A converter, and a voltage-controlled oscillator controller for detecting a data amount of the digital data stored in the buffer, and controlling a frequency of the clock signal based on a deviation in the detected data amount from a first predetermined value and a time integral of the deviation value.

Abstract: An interface circuit 13 is provided for a display apparatus 3 such as a television. The display apparatus 3comprises a video signal processing circuit 8 for processing a composite video signal to derive color component signals having variable black and white levels; a linear amplifier 10 for amplifying the color component signals; and a display device 4 such as a CRT driven by the output of the linear amplifier 10. The interface circuit 13 is provided to interface the color component signals with a digital signal processor 14. The interface circuit 13 includes a modification circuit 22 arranged to perform a modification of voltage levels of the color component signals and to output the modified color component signals to the digital signal processor 14 via an A/D convertor 18.

Abstract: A method and apparatus for the processing of video data in which the appearance characteristics of picture elements are modified using digital apparatus such as a color processor which provides a plurality of channels having respective processing means, each channel being adapted normally to operate to process a discrete range of characteristics, wherein the method comprises the step of operating the apparatus in an alternative mode in which at least two of the channels are used to carry out identical processing steps, spatial segments of the video data being split between said at least two channels to thereby increase the speed of processing.

Abstract: A method of simultaneously providing A/D conversion and multiplication in a Bit-Serial ADCs and single slope ADCs. A bit serial ADC uses a RAMP signal and a BITX signal input to a comparator and 1-bit latch, respectively. When RAMP exceeds an analog input value, the comparator triggers the latch to output the value of BITX. The bits are output serially. The RAMP signal has a staircase shape with voltage levels and voltage steps. In the present invention, multiplication by two coefficients is possible. One coefficient is determined by properly designing RAMP, and the other coefficient is determined by properly designing BITX. Multiplication via RAMP is accomplished by changing the voltage levels by a factor of 1/X, where X is the multiplying coefficient (i.e., multiplication by a factor of 0.5 is accomplished by doubling the voltage of the voltage levels). Multiplication via BITX is accomplished by slowing the frequency of BITX by a factor of X.

Abstract: A display system that can be calibrated and re-calibrated with a minimal amount of manual intervention. To accomplish this, one or more cameras are provided to capture an image of the display screen. The resulting captured image is processed to identify any non-desirable characteristics, including visible artifacts such as seams, bands, rings, etc. Once the non-desirable characteristics are identified, an appropriate transformation function is determined. The transformation function is used to pre-warp the input video signal that is provided to the display such that the non-desirable characteristics are reduced or eliminated from the display. The transformation function preferably compensates for spatial non-uniformity, color non-uniformity, luminance non-uniformity, and other visible artifacts.

Abstract: A self-device on a network is designed not to be unintentionally operated from a remote device. For this purpose, in a network including a self-device for performing processing corresponding to a received AV/C command and one or more remote devices for sending out AV/C commands (excluding commands containing only statuses), the self-device has mode 1 of giving a high priority to control on itself and mode 2 of accepting control from remote devices as well. Mode 1 or mode 2 is set by a user. In mode 1, the self-device rejects AV/C commands supplied from the remote devices.

Abstract: Viewing of a program is enabled at optimum image quality. A correspondence table of an image signal processing parameter and a combination of TMCC information and transmission errors is stored in a RAM. A CPU reads out an image signal processing parameter corresponding to a combination of TMCC information supplied from an IF demodulator and transmission errors supplied from the IF demodulator, a demultiplexer and an MPEG video decoder from the correspondence table stored in the RAM, and controls signal processing in an image signal processing portion and display processing in an image display portion based on the image signal processing parameter.

Abstract: The invention provides technology to generate a graphical depiction on a video display device (VDD) for a stream of packets. Such a graphical depiction can take the form of a matrix of geometric shapes, e.g., squares, each geometric shape representing a packet. Each geometric shape can have an appearance that is indicative of what type the corresponding packet is. Colors can be assigned to the geometric shapes to denote the types of the corresponding packets, respectively. Such technology can also generate a graphical depiction on the VDD of a legend explaining color and packet type relations. Each color in the legend can be depicted in the form of the geometric shape, and each geometric shape can be operable as a pointing-device-clickable button so that, in response to a user clicking on one of the geometric shapes, an interface can be generated by which the color assigned to the geometric shape can be changed by the user.

Abstract: A video transmission apparatus in which an n (the n represents an integer of 2 or more) number of different video data (13), (15), (17), (19) are transmitted via a single transmission line (8) from a plurality of video signal output sections (14), (16), (18), (20) to a video display device (5) and on the video display device (5), the video data that is indicated by a video data switching device (1) is selectively displayed, wherein the video display device (5) comprising; a latch signal generation circuit (40) for generating a latch signal (27) for latching either one of the n number of different video data (13), (15), (17), (19) on the transmission line (8) in accordance with a video switching signal output (2) from the video data switching device (1), and a latch circuit (37) for latching a prescribed video data on the transmission line (8) by the latch signal (27).

Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Abstract: A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by other processing units. A timing generator responds to a base clock and to a data valid signal, that indicates arrival of a portion of the interlaced video data, to cause generation of a plurality of enable signals. Each of the enable signals operate to enable a corresponding one of the clocking rates required by the processing units. Video capture can be performed by causing capture of video frames that meet or exceed a specified quality level. The quality of the captured, still image, video can be improved by disabling certain enhancement functions performed to improve moving video images.

Abstract: The present invention provides a technique for appropriately adjusting a dot clock for video signals by a simple process. A process of adjusting a phase of the dot clock first obtains two image data by two dot clocks having different phases, carries out a certain operation for the two image data to calculate a phase-related index representing the relative phase of the dot clock to a video signal with respect to the two image data, and determines a delay that gives a desirable phase to the dot clock based on these phase-related indexes. A first process of adjusting the frequency of the dot clock first obtains image data by a dot clock that has been generated with a provisional factor, calculates a length of an effective signal area on one line of the image data, and determines a desirable factor based on the ratio of a known length to the measured length of the effective signal area.

Abstract: A video filter processes pixel data by storing multiple lines of pixel data in a memory buffer and computes a weighted average of the data using a plurality of multipliers and accumulators. The pixel data which, for example, may represent luminance and/or chrominance values is stored in the buffer in an interleaved fashion. Preferably multiple lines of pixel data is stored in a single buffer, thereby reducing the number of traces that would otherwise be required if a separate buffer was used for each line of pixel data.

Abstract: An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.

Abstract: A signal processing device which selects a signal, using for example, a channel selector in a television receiver or a source selection circuit in an amplifier, and compensates automatically for differences in signal parameters, such as volume of sound or picture brightness, between the signal sources. Corrections which are applied to the relevant parameter within a given time interval after source selection are divided within the time interval between a global value and a local value (for example an offset) for the relevant signal source.

Abstract: A video signal processing device comprising an operating element array for processing video signals according to commands given from the outside, memories for temporarily storing the video signals according to commands given from the outside, and a network 3 for connecting the operating element array and the storage units according to commands given from the outside, thereby making it possible to switch ways of processing digitized video signals according to commands from the outside.

Abstract: A video signal processing apparatus comprising an oscillating unit for outputting a signal of a stable frequency, a counting unit for counting the period of a cycle of a signal supplied from the outside based on the signal output by the oscillating unit, a clock number calculating unit for calculating the number of clocks in a line based on a result of counting by the counting unit, a comparing unit for comparing the number of clocks calculated by the clock number calculating unit with a threshold to decide which is larger, a switching unit for deciding the number of clocks in the next operation by switching to the number of clocks calculated by the clock number calculating unit if the calculated number of clocks is larger than the threshold, or deciding the number of clocks in the next operation by holding the number of clocks in a line in the current operation as it is, and a synchronizing signal generating unit for, based on the number of clocks in operation decided by the switching unit and the signal out

Abstract: An image information processing apparatus of this invention receives an information signal, converts the input information signal into digital data, temporarily stores the converted digital data, parallel/serial-converts the temporarily stored digital data, and controls the operation of the parallel/serial processing in accordance with the contents of information indicated by the temporarily stored digital data when the parallel/serial-converted digital data is converted into an analog signal and the analog signal is transmitted onto the transmission path, thereby allowing easy transmission of image information and a control code using a smaller number of transmission path and realizing a cost reduction.

Abstract: A conversion unit having a bidirectional conversion function of converting analog video signals into digital image data and vice versa and a processing unit having a function of encoding image data and of decoding encoded data are provided. A data transmission control unit switches the flow direction of each of image data and encoded data in response to an encoder/decoder switch signal. A process control unit performs switching of the receiving/transmitting of a control signal such as a transmission clock signal relating to encoded data in response to a master/slave set signal.

Abstract: A video processing system that processes vertical column of pixels from individual fields is disclosed. The video processing system processes pixels from an even field independent of the pixels in the odd field, and vice versa. The video processing system preferably includes a system memory for storing fields of input video images and a vertical filter coupled to the system memory via a data bus. The field data is retrieved from the system memory by the vertical filter and processed as individual fields. The vertical filter preferably calculates a 2.times. enlargement of the input image, although the filter can be adapted to enlarge by different factors if desired. The enlargement process generally involves representing an input image with twice as many lines of pixels values as the initial image. The values that are used to represent the enlarged pixels are preferably weighted averages of the pixels from an input pixel field.

Abstract: A computer video signal distributor receives as inputs the video signals of a computer, and then processes and distributes these video signals to a plurality of monitors. The computer video signal distributor includes three transistor common based voltage amplifying circuits for inputting red, green, blue video signals of the computer respectively, then amplifying these video signals for outputting. Three sets of transistor emitter follower current amplifying circuits are provided for connecting respectively with one of the outputs of the three voltage amplifying circuits, and provide sufficient frequency response for inputted video signals, and distributing the inputted video signals according to the number of monitors. A synchronous signal buffering device is provided for receiving synchronous signals of the computer, and generating a plurality of sets of synchronous signals according to the number of the monitors.

Abstract: The present invention provides a technique for appropriately adjusting a dot clock for video signals by a simple process. A process of adjusting a phase of the dot clock first obtains two image data by two dot clocks having different phases, carries out a certain operation for the two image data to calculate a phase-related index representing the relative phase of the dot clock to a video signal with respect to the two image data, and determines a delay that gives a desirable phase to the dot clock based on these phase-related indexes. A first process of adjusting the frequency of the dot clock first obtains image data by a dot clock that has been generated with a provisional factor, calculates a length of an effective signal area on one line of the image data, and determines a desirable factor based on the ratio of a known length to the measured length of the effective signal area.

Abstract: A broadcast recording and playback device employing a "circular buffer" which constantly records one or more incoming audio or video program signals and a microprocessor for accessing the memory to read a playback signal from the circular buffer to display programming material delayed from its receipt by a selectable delay interval. The circular buffer is implemented by a digital memory. Subsystem comprising the combination of a semiconductor RAM memory and a disk memory operated under the control of a microprocessor such that incoming signals are constantly recorded as received while, at the same time, delayed signals are being read from the memory subsystem at a different memory location selected by a microprocessor to provide a user-selected time delay.