Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.

Abstract: Methods of forming a pattern in a semiconductor device may be provided. The methods may include sequentially forming a first hard mask layer and a second hard mask layer on an etching target layer including first and second regions, forming a first spacer layer on the second hard mask layer, forming a second hard mask pattern layer by etching the second hard mask layer using the first spacer layer, forming a second spacer layer on a sidewall of the second hard mask pattern layer, forming a first hard mask pattern layer by etching the first hard mask layer using the second spacer layer, and etching the etching target layer using the first hard mask pattern layer.

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract: Technology that achieves high integration of a semiconductor device employing TSV technology is provided. A through electrode is configured by a small-diameter through electrode having a first diameter and being formed on a main surface side of a semiconductor wafer, and a large-diameter through electrode having a second diameter larger than the above-described first diameter and being formed on a back surface side of the semiconductor wafer, and the small-diameter through electrode is arranged inside the large-diameter through electrode in a planar view so that a center position of the small-diameter through electrode and a center position of the large-diameter through electrode do not overlap with each other in the planar view.

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure formed on a first portion of the active region, and at least one local interconnection layer formed on a portion of the substrate, wherein the at least one local interconnection layer is located on a side of the gate structure, and covers at least a second portion of the active region and a portion of the groove isolation region adjoining the active region.

Abstract: A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.

Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.

Abstract: A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches.

Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.

Abstract: An embodiment method of forming and a bump structure are disclosed. The bump structure includes a passivation layer formed over a metal pad, the passivation layer having a recess exposing a portion of the metal pad, and a metal bump formed over the metal pad, the metal bump having a lip extending beneath the passivation layer, the lip anchoring the metal bump to the passivation layer.

Abstract: A microelectronic device includes a substrate having at least one microelectronic component on a surface thereof, a conductive via electrode extending through the substrate, and a stress relief structure including a gap region therein extending into the surface of the substrate between the via electrode and the microelectronic component. The stress relief structure is spaced apart from the conductive via such that a portion of the substrate extends therebetween. Related devices and fabrication methods are also discussed.

Abstract: A method of manufacturing a support body includes: (a) preparing a support substrate; (b) preparing a metal foil on which a peeling layer is provided; (c) providing an adhesion adjusting layer on the support substrate in a certain region of the support substrate excluding an outer peripheral portion of the support substrate, wherein the adhesion adjusting layer is configured to adjust a contact area between the peeling layer and the support substrate; and (d) providing the metal foil on the support substrate such that the peeling layer provided on the metal foil faces the support substrate via the adhesion adjusting layer. In step (d), the adhesion adjusting layer is adhered to the support substrate, and the peeling layer is adhered to the outer peripheral portion of the support substrate, and is in contact with the adhesion adjusting layer but is not adhered to the adhesion adjusting layer.

Abstract: Embodiments of the invention relate generally to methods and compositions for forming porous low refractive index coatings on substrates. In one embodiment, a method for forming a porous coating on a substrate is provided. The method comprises coating a substrate with a sol-gel composition, comprising at least one porosity forming agent, wherein the porosity forming agent is selected from at least one of dendrimers and organic nanocrystals and removing the at least one porosity forming agent to form the porous coating. Use of at least one of the dendrimers and organic nanocrystals leads to the formation of stable pores with larger volume fraction in the film. Further, the size and interconnectivity of the pores may be controlled via selection of the organic nanocrystal or dendrimer structure, the total organic nanocrystal or dendrimer molecule fraction, polarity of the organic nanocrystal or dendrimer molecule and solvent, and other physiochemical properties of the gel phase.

Abstract: A method for forming electrical-contact interface regions on a wafer including a silicon-carbide substrate having a surface with at least one conductive region facing the surface. The method includes forming a first and a second resist layer; forming; removing portions of the second resist layer to form a through opening partially aligned to the conductive region; removing, selective portions of the first resist layer to expose the surface of the substrate; removing portions of the first resist layer that extend laterally staggered with respect to the through opening; depositing a nickel layer on the wafer to form a nickel region on the substrate in an area corresponding to the conductive region; removing the first and second resist layers; and carrying out a step of thermal treatment of the wafer to form nickel-silicide regions in electrical contact with the conductive region.

Abstract: Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The air gaps may be located between copper lines on the same layer. A sacrificial patterned dielectric layer is used as a template to form a layer of copper by physical vapor deposition in a substrate processing system (i.e. a mainframe). Without breaking vacuum, the copper is redistributed into the gaps with a copper reflow process. Dielectric material from the template is removed, again in the same mainframe, using a remote fluorine etch process leaving the gapfill copper as the structural material. A conformal capping layer (such as silicon carbon nitride) is then deposited (e.g. by ALD) to seal the patterned substrate before removing the patterned substrate from the mainframe.

Abstract: A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.

Abstract: An integrated circuit device includes a substrate, at least one transistor, at least one metal layer, a conductive pillar, and a connecting structure. The substrate has at least one via passing therethrough. The transistor is at least partially disposed in the substrate. The metal layer is disposed on or above the substrate. The conductive pillar is disposed in the via. The connecting structure is at least partially disposed in the via and connecting the conductive pillar and the metal layer. At least a first portion of the connecting structure is made of a stress releasing material having a coefficient of thermal expansion less than a coefficient of thermal expansion of the conductive pillar. A projection of the transistor in the via overlaps with the connecting structure.

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a substrate, a first conductive structure, a second conductive structure, a dielectric structure, a dielectric layer, a first conductive plug, and a second conductive plug. The first conductive plug passes through only an upper dielectric portion of the dielectric structure, the dielectric layer and a lower dielectric portion of the dielectric structure to physically and electrically contact with the first conductive structure. The second conductive plug passes through the upper dielectric portion, the dielectric layer and the lower dielectric portion to physically and electrically contact with the second conductive structure.

Abstract: A method of forming a conductive pattern on a metallic frame for manufacturing a stack frame for electrical connections is disclosed. In one embodiment, a recess is formed in the metallic frame and a conductive element is bonded in the recess to make a stack frame for electrical connections. In another embodiment, the process can be performed on both top surface and bottom surface of metallic frame to make another stack frame for electrical connections. In yet another embodiment, a package structure and a manufacturing method of forming a conductive pattern on a lead frame for electrical connections are disclosed.

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract: Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract: A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract: A method of producing a semiconductor device includes the step of forming a through hole in a semiconductor substrate. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface, and includes a first conductive layer formed on the second main surface. The through hole penetrates through the semiconductor substrate from the first main surface to the second main surface, so that the first conductive layer formed on the second main surface is exposed at a bottom portion of the through hole. The method further includes the steps of forming a seed layer on a side surface of the through hole from the bottom portion of the through hole to the first main surface; forming a second conductive layer on the seed layer through a first plating process; and forming a third conductive layer selectively on the second conductive layer.

Abstract: A semiconductor device containing an MIM capacitor and its fabrication method are provided. A metal-insulator-metal (MIM) capacitor is formed on a first interlayer dielectric layer covering a substrate. The MIM capacitor includes a bottom electrode layer and a top electrode layer that are isolated from and laterally staggered with one another. A second interlayer dielectric layer is formed to cover both the MIM capacitor and the first interlayer dielectric layer. A first conductive plug and a second conductive plug are formed each passing through the second interlayer dielectric layer. The first conductive plug contacts a sidewall and a surface portion of the top electrode layer of the MIM capacitor and the second conductive plug contacts a sidewall and a surface portion of the bottom electrode layer of the MIM capacitor.

Abstract: A semiconductor device is provided in which reliability of the semiconductor device is improved by improving an EM characteristic, a TDDB characteristic, and a withstand voltage characteristic of the semiconductor device. An average diameter of first vacancies in a lower insulating layer which configures an interlayer insulating film of a porous low-k film for embedding a wiring therein, is made smaller than an average diameter of second vacancies in an upper insulating layer, and thereby an elastic modulus is increased in the lower insulating layer. Further, a side wall insulating layer which is a dense layer including the first vacancies having an average diameter smaller than the second vacancies is formed on the surface of the interlayer insulating film exposed on a side wall of a wiring trench.

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract: Provided is a method of forming large-area directionally aligned nanowires on a silicon wafer surface with hydrophobic silicon pillars so as to form microelectrode-pair arrays, which belongs to the field of electronic circuit.

Abstract: Passive devices fabricated on glass substrates, methods of manufacture and design structures are provided. The method includes forming an opaque or semi-opaque layer on at least a first side of a glass substrate. The method further includes forming one or more passive devices on the opaque or semi-opaque layer on a second side of the glass substrate.

Abstract: The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract: An organic light emitting display is capable of preventing brightness from being non-uniform due to IR drop so as to improve reliability of the organic light emitting display. The organic light emitting display comprises: a display panel having a display region and a non-display region; a plurality of sub pixels defined by perpendicularly intersecting a plurality of gate lines and a plurality of data lines formed in the display region of the display panel; and a power source supply pad unit provided in the non-display region of the display panel for supplying a power source voltage to the plurality of sub pixels. A resistance value of sub pixels arranged in a first region adjacent to the power source supply pad unit is higher than a resistance value of sub pixels of a second region which is separated from the power source supply pad unit, with the first region interposed therebetween.

Abstract: A fabrication method for semiconductor devices is provided. The method comprises: depositing a dielectric layer that includes a plurality of functional layers, and forming a contact hole, or through hole, and a metal layer. The forming of the contact hole, or through hole, and the metal layer comprises performing photolithography on regions corresponding to a marking label for the photolithography of the dielectric layer and the metal layer. On at least one of the functional layers, the performing photolithography on regions corresponding to a marking label for the photolithography comprises limiting the photolithography to the metal layer thereof. A semiconductor device thus fabricated is also provided. The method and device do not affect the reading of the marking label, and also can avoid the problem of defocusing in the vicinity of the marking label.

Abstract: Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 ?m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.

Abstract: A semiconductor device and methods directed toward preventing a leakage current between a contact plug and a line adjacent to the contact plug, and minimizing capacitance between adjacent lines.

Abstract: A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.

Abstract: A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.

Abstract: An integrated circuit device and a method for making it are provided. The integrated circuit device comprises plural conductive layers, plural dielectric layers and plural first stopping layers. The conductive layers are extending in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers.

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.

Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.