Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 8445363
    Abstract: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 21, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Tsuo-Wen Lu, I-Ming Lai, Tsung-Yu Hou, Chien-Liang Lin, Wen-Yi Teng, Shao-Wei Wang, Yu-Ren Wang, Chin-Cheng Chien
  • Publication number: 20130122718
    Abstract: A disclosed film deposition apparatus includes a turntable including a substrate receiving area; a first reaction gas supplier for supplying a first reaction gas to a surface of the turntable having the substrate receiving area; a second reaction gas supplier, arranged away from the first reaction gas supplier along a circumferential direction of the turntable, for supplying a second reaction gas to the surface; a separation area located along the circumferential direction between a first process area of the first reaction gas and a second process area of the second reaction gas; a separation gas supplier for supplying a first separation gas to both sides of the separation area; a first heating unit for heating the first separation gas to the separation gas supplier; an evacuation opening for evacuating the gases supplied to the turntable; and a driver for rotating the turntable in the circumferential direction.
    Type: Application
    Filed: January 7, 2013
    Publication date: May 16, 2013
    Applicant: Tokyo Electron Limited
    Inventor: Tokyo Electron Limited
  • Publication number: 20130122708
    Abstract: Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.
    Type: Application
    Filed: January 4, 2013
    Publication date: May 16, 2013
    Applicant: SEMATECH, INC.
    Inventor: SEMATECH, INC.
  • Publication number: 20130123382
    Abstract: To provide a curable composition which is sufficiently cured even without a heating step at high temperature and from which a low dielectric constant cured film excellent in the solvent resistance is obtained. A curable composition comprising a fluorinated polyarylene prepolymer (A) having a crosslinkable functional group, a compound (B) having a number average molecular weight of from 140 to 5,000, having at least two crosslinkable functional groups and having no fluorine atoms, a copolymer (C) having the following units (c1) and (c2) and a radical polymerization initiator (D): unit (c1): a unit having a fluoroalkyl group having at most 20 carbon atoms, which may have an etheric oxygen atom between carbon atoms, and having no crosslinkable functional group; unit (c2): a unit having a crosslinkable functional group.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 16, 2013
    Applicant: Asahi Glass Company, Limited
    Inventor: Asahi Glass Company, Limited
  • Publication number: 20130122707
    Abstract: Methods of polymer deposition for forming reduced critical dimensions are described. In one embodiment, a substrate is provided into a chamber, the substrate having a patterned layer disposed on an underlying layer formed thereon. The patterned layer includes a plurality of openings, each opening having a sidewall, a bottom, and a critical dimension. A gas mixture is provided into the chamber, the gas mixture having an etching gas and a polymer control gas. The polymer control gas includes a polymerizing fluorocarbon CxFy gas and a C—H bond containing gas. A plasma is formed with the gas mixture and a conformal polymer layer is deposited in the presence of the plasma on the patterned layer to form a reduced critical dimension in each opening. The reduced critical dimension is smaller than the corresponding critical dimension of the opening.
    Type: Application
    Filed: October 19, 2012
    Publication date: May 16, 2013
    Inventors: Daisuke Shimizu, Jong Mun Kim
  • Patent number: 8441077
    Abstract: A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: May 14, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Sam Yang
  • Patent number: 8440556
    Abstract: Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging the chamber of excess reaction by-products.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Scott Bruce Clendenning, Niloy Mukherjee
  • Publication number: 20130115776
    Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: Lam Research Corporation
    Inventors: Mirzafer Abatchev, Camelia Rusu, Brian McMillin
  • Publication number: 20130115751
    Abstract: A composition includes a boron-containing hydrogen silsesquioxane polymer having a structure that includes: silicon-oxygen-silicon units, and oxygen-boron-oxygen linkages in which the boron is trivalent, wherein two silicon-oxygen-silicon units are covalently bound by an oxygen-boron-oxygen linkage therebetween.
    Type: Application
    Filed: January 2, 2013
    Publication date: May 9, 2013
    Applicant: CHEIL INDUSTRIES, INC.
    Inventor: CHEIL INDUSTRIES, INC.
  • Publication number: 20130115780
    Abstract: A plasma processing apparatus has a circular chamber having an opening portion which serves as a plasma ejection port surrounded by a dielectric member, a gas supply pipe for introducing gas into the inside of the chamber, a coil provided in the vicinity of the chamber, a high-frequency power supply connected to the coil, and a base material mounting table.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 9, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Panasonic Corporation
  • Patent number: 8435353
    Abstract: According to one embodiment, the thin film forming apparatus includes a boat capable of holding two wafers, in each of which a cutout portion is provided in an outer peripheral edge portion, in a groove portion for holding a wafer in a state where back surfaces face each other. Moreover, the thin film forming apparatus includes a reactor that accommodates the boat and form a coating on each of surfaces of the two wafers by a vapor deposition reaction. The positions in the groove portion, at which the two wafers are held, respectively, are displaced in a direction parallel to the surfaces of the wafers.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuyoshi Sato
  • Patent number: 8435873
    Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Vladimir Frank Drobny
  • Publication number: 20130109192
    Abstract: A susceptor including a generally circular body having a face with a radially inward section and a radially outward section proximate a circumference of the body, the radially outward section having at least one ring extending upward for contacting a bottom surface of a substrate, and wherein the radially inward section lacks a ring extending upward from the face.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Applicant: ASM America, Inc.
    Inventors: Mark Hawkins, Matthew G. Goodman, Shawn Thomas
  • Publication number: 20130109193
    Abstract: A substrate processing apparatus comprises a processing chamber for storing a substrate and performing a specified processing on the substrate, a substrate holding jig for holding the substrate in the processing chamber, a placement stand capable of moving the substrate holding jig inside and outside the processing chamber while mounting the substrate holding jig, a substrate holding jig movement mechanism for moving the substrate holding jig to a location different from the placement stand while holding the substrate holding jig, and a substrate holding jig movement suppression mechanism for suppressing vertical and horizontal movement of the substrate holding jig in order to keep the substrate holding jig mounted on the placement unit of the substrate holding jig movement mechanism.
    Type: Application
    Filed: November 30, 2012
    Publication date: May 2, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: HITACHI KOKUSAI ELECTRIC INC.
  • Patent number: 8431493
    Abstract: A holding device adapted for holding a mask and a substrate during processing is described. The holding device includes a substrate carrier adapted for carrying the substrate; and a mask for masking the substrate, wherein the mask is releasably connected to the substrate carrier; wherein the substrate carrier or the mask has at least one recess adapted for receiving a cover for covering the substrate carrier during deposition.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 30, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Ralph Lindenberg
  • Patent number: 8431344
    Abstract: A method of fabrication or manufacture at micrometer and nanometer scale by spatially selective deposition of chemical substances so as to form a solid phase array on a substrate (10) which includes the steps of defining a region (15) on the substrate by forming an electrostatic charge on that region which is different from the electrostatic charge on other regions of the substrate such as by formation of a latent electrostatic image thereon, applying an emulsion to the substrate. The emulsion (16) has an electrically charged discontinuous phase and a component to be selectively deposited carried in or comprising the discontinuous phase. The discontinuous phase of the emulsion is attracted to the preselected region by attraction by the electrostatic charge on the region and deposition obtained with or without reaction. The electrostatic image may be formed by the use of photoconductor.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 30, 2013
    Assignee: Raustech Pty Ltd
    Inventors: Peter John Hastwell, Timothy Mark Kaethner
  • Publication number: 20130102159
    Abstract: To provide a substrate processing apparatus, including: a plurality of process chambers in which a prescribed number of each type of substrates is processed; and a controller configured to decide the number of dummy substrates so that the number of the dummy substrates used in each process chamber is approximately the same between the process chambers, when the number of the dummy substrates used in each process chamber is decided so that the number of each type of substrates used in each process chamber reaches the prescribed number.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 25, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: HITACHI KOKUSAI ELECTRIC INC.
  • Patent number: 8426320
    Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: April 23, 2013
    Assignee: Wostec, Inc.
    Inventors: Valery K. Smirnov, Dmitry S. Kibalov
  • Publication number: 20130095668
    Abstract: Provided is a semiconductor device manufacturing method of forming a film of less than one atomic layer on a substrate. The method includes (a) supplying a source gas into a processing chamber accommodating the substrate to adsorb the source gas on the substrate; (b) supplying a reactive gas different from the source gas into the processing chamber to cause a reaction of the reactive gas with the source gas adsorbed on the substrate before the source gas is saturatively adsorbed on the substrate; (c) removing an inner atmosphere of the processing chamber; and (d) supplying a modifying gas into the processing chamber to modify the source gas adsorbed on the substrate.
    Type: Application
    Filed: December 4, 2012
    Publication date: April 18, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: HITACHI KOKUSAI ELECTRIC INC.
  • Publication number: 20130087362
    Abstract: The invention relates to a polymer composition with improved DC electrical properties, to the use of the composition for producing a cable layer and to a cable surrounded by at least one layer comprising the polymer composition.
    Type: Application
    Filed: March 1, 2011
    Publication date: April 11, 2013
    Applicant: BOREALIS AG
    Inventors: Ulf Nilsson, Per-Ola Hagstrand, Villgot Englund, Andreas Farkas, Janis Ritums
  • Patent number: 8414787
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation. In one example an electron beam array such as a carbon nanotube array is used to selectively expose a surface during a processing operation.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: April 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Publication number: 20130084459
    Abstract: A curable adhesive composition is disclosed comprising: at least one free radically polymerizable oligomer component; optionally at least one diluent monomer; at least one perfluorinated ether monomer; and a photoinitiator. The curable liquid adhesive is easily removable with low force and low adhesive transfer.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Inventors: Eric G. Larson, Blake R. Dronen, Miguel A. Guerra, Wayne S. Mahoney, Richard J. Webb
  • Patent number: 8409353
    Abstract: A method and apparatus for oxidizing materials used in semiconductor integrated circuits, for example, for oxidizing silicon to form a dielectric gate. An ozonator is capable of producing a stream of least 70% ozone. The ozone passes into an RTP chamber through a water-cooled injector projecting into the chamber. Other gases such as hydrogen to increase oxidation rate, diluent gas such as nitrogen or O2, enter the chamber through another inlet. The chamber is maintained at a low pressure below 20 Torr and the substrate is advantageously maintained at a temperature less than 800° C. Alternatively, the oxidation may be performed in an LPCVD chamber including a pedestal heater and a showerhead gas injector in opposition to the pedestal.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: April 2, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yoshitaka Yokota, Sundar Ramamurthy, Vedapuram Achutharaman, Cory Czarnik, Mehran Behdjat, Christopher Olsen
  • Patent number: 8410000
    Abstract: The method for producing a photovoltaic cell includes applying, on a partial region of one surface side of a semiconductor substrate, a first p-type diffusion layer forming composition including a p-type impurity-containing glass powder and a dispersion medium; applying, on at least a region other than the partial region on the surface of the semiconductor substrate, a second p-type diffusion layer forming composition which includes a p-type impurity-containing glass powder and a dispersion medium and in which a concentration of the p-type impurity is lower than that of the first p-type diffusion layer forming composition, where the first p-type diffusion layer forming composition is applied; heat-treating the semiconductor substrate on which the first p-type diffusion layer forming composition and the second p-type diffusion layer forming composition are applied to form a p-type diffusion layer; and forming an electrode on the partial region.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: April 2, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Youichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Akihiro Orita, Tetsuya Satou, Keiko Kizawa
  • Publication number: 20130078817
    Abstract: According to an embodiment, a method of forming a film is provided. In the method of forming a film, a reversed pattern which is the reverse of a desired layout pattern is formed on a first substrate. Subsequently, a pattern material of the desired layout pattern is supplied to a second substrate as a reversal material. Thereafter, the reversed pattern is brought into contact with the reversal material such that the reversed pattern faces the reversal material, so that the reversed pattern is filled with the reversal material by a capillary phenomenon.
    Type: Application
    Filed: March 8, 2012
    Publication date: March 28, 2013
    Inventor: Tsukasa AZUMA
  • Publication number: 20130078776
    Abstract: The inventive concept provides methods of manufacturing three-dimensional semiconductor devices. In some embodiments, the methods include forming a stack structure including sacrificial layers and insulation layers, forming a trench penetrating the stack structure, forming a hydrophobic passivation element on the surfaces of the insulation layers that were exposed by the trench and selectively removing the sacrificial layers.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Inventors: Young-Hoo Kim, San Won Bae, Kuntack Lee, Hyosan Lee
  • Patent number: 8404600
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Patent number: 8404562
    Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 8404599
    Abstract: The method for producing a photovoltaic cell includes applying, on a partial region of one surface side of a semiconductor substrate, a first n-type diffusion layer forming composition including an n-type impurity-containing glass powder and a dispersion medium; applying, on at least a region other than the partial region on the surface of the semiconductor substrate, a second n-type diffusion layer forming composition which includes an n-type impurity-containing glass powder and a dispersion medium and in which a concentration of the n-type impurity is lower than that of the first n-type diffusion layer forming composition, where the first n-type diffusion layer forming composition is applied; heat-treating the semiconductor substrate on which the first n-type diffusion layer forming composition and the second n-type diffusion layer forming composition are applied to form an n-type diffusion layer; and forming an electrode on the partial region.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: March 26, 2013
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Youichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Akihiro Orita, Tetsuya Satou, Keiko Kizawa
  • Patent number: 8399362
    Abstract: A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: March 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara
  • Publication number: 20130065401
    Abstract: Methods for depositing metal-polymer composite materials atop a substrate are provided herein. In some embodiments, a method of depositing a metal-polymer composite material atop a substrate disposed in a hot wire chemical vapor deposition (HWCVD) chamber may include flowing a current through a plurality of filaments disposed in the HWCVD chamber, the filaments comprising a metal to be deposited atop a substrate; providing a process gas comprising an initiator and a monomer to the HWCVD chamber; and depositing a metal-polymer composite material on the substrate using species decomposed from the process gas and metal atoms ejected from the plurality of filaments.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 14, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: SUKTI CHATTERJEE, AMIT CHATTERJEE
  • Publication number: 20130065402
    Abstract: A method of cleaning an inside of a processing chamber is provided according to an embodiment of the present disclosure. The method includes supplying a fluorine-based gas and a nitrogen oxide-based gas as the cleaning gas, into the processing chamber heated to a first temperature, and removing a deposit by a thermochemical reaction. The method further includes changing a temperature in the processing chamber to a second temperature higher than the first temperature, and supplying the fluorine-based gas and the nitrogen oxide-based gas as the cleaning gas, and removing extraneous materials, remaining on the surface of the member in the processing chamber, by a thermochemical reaction.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 14, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kenji Kameda, Yuji Urano
  • Publication number: 20130065399
    Abstract: A plasma processing method includes holding a wafer on a holding stage, generating plasma inside the processing chamber by a plasma generator to define a first processing region having an electron temperature higher than a predetermined value and a second processing region having an electron temperature lower than the predetermined value, moving the holding stage for the wafer to be positioned in the first processing region, performing the plasma processing of the wafer positioned in the first processing region, moving the holding stage for the wafer to be positioned in the second processing region, and stopping to generate plasma when the wafer is positioned in the second processing region after completion of the plasma processing.
    Type: Application
    Filed: November 5, 2012
    Publication date: March 14, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Tokyo Electron Limited
  • Publication number: 20130065403
    Abstract: A wafer carrier used in wafer treatments such as chemical vapor deposition has pockets for holding the wafers and support surfaces for supporting the wafers above the floors of the pockets. The carrier is provided with thermal control features such as trenches which form thermal barriers having lower thermal conductivity than surrounding portions of the carrier. These thermal control features promote a more uniform temperature distribution across the wafer surfaces and across the carrier top surface.
    Type: Application
    Filed: November 9, 2012
    Publication date: March 14, 2013
    Inventors: Ajit Paranjpe, Boris Volf, Eric A. Armour, Sandeep Krishnan, Guanghua Wei, Lukas Urban
  • Patent number: 8394725
    Abstract: A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Timothy A. Quick
  • Patent number: 8389419
    Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Sunil Shanker, Tony P. Chiang
  • Publication number: 20130052835
    Abstract: A pattern transfer apparatus according to one embodiment includes a transfer region selecting part that performs operation in which when performing pattern transfer from a template provided with N transfer regions (N is an integer of 2 or larger) to a transferring substrate a plurality of times, 1 to N?1 transfer regions, which are to be used to perform the transfer to regions of the transferring substrate corresponding to part of the N transfer regions, are selected such that the number of the transfer to be performed using each of the N transfer regions is evened out. ened out.
    Type: Application
    Filed: March 16, 2012
    Publication date: February 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yuji KOBAYASHI
  • Publication number: 20130052834
    Abstract: A wafer holder and temperature controlling arrangement has a metal circular wafer carrier plate, which covers a heater compartment. In the heater compartment a multitude of heater lamp tubes is arranged, which directly acts upon the circular wafer carrier plate. Latter is drivingly rotatable about the central axis. A wafer is held on the circular wafer carrier plate by means of a weight-ring residing upon the periphery of a wafer deposited on the wafer carrier plate.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: OC Oerlikon Balzers AG
    Inventors: Juergen Kielwein, Bart Scholte Von Mast, Rogier Lodder
  • Patent number: 8377831
    Abstract: A method for size selection of nanostructures comprising utilizing a gas-expanded liquids (GEL) and controlled pressure to precipitate desired size populations of nanostructures, e.g., monodisperse. The GEL can comprise CO2 antisolvent and an organic solvent. The method can be carried out in an apparatus comprising a first open vessel configured to allow movement of a liquid/particle solution to specific desired locations within the vessel, a second pressure vessel, a location controller for controlling location of the particles and solution within the first vessel, a inlet for addition of antisolvent to the first vessel, and a device for measuring the amount of antisolvent added. Also disclosed is a method for forming nanoparticle thin films comprising utilizing a GEL containing a substrate, pressurizing the solution to precipitate and deposit nanoparticles onto the substrate, removing the solvent thereby leaving a thin nanoparticle film, removing the solvent and antisolvent, and drying the film.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: February 19, 2013
    Assignee: Auburn University
    Inventors: Christopher B. Roberts, Marshall Chandler McLeod, Madhu Anand
  • Patent number: 8377803
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 19, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua, Sandeep Nijhawan
  • Publication number: 20130041170
    Abstract: Organometallic complexes and use thereof in thin film deposition, such as CVD and ALD are provided herein. The organometallic complexes are (alkyl-substituted ?3-allyl)(carbonyl)metal complexes.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 14, 2013
    Applicant: Sigma-Aldrich Co. LLC
    Inventors: Rajesh Odedra, Neil Boag, Jeff Anthis, Ravi Kanjolia, Mark Saly
  • Publication number: 20130040460
    Abstract: A method of depositing a thin film by atomic layer deposition (ALD) on a substrate surface is disclosed. The disclosed method includes placing an ALD deposition proximity head above the substrate with at least one gas channel configured to dispense a gas to an active process region of the substrate surface. The ALD deposition proximity head extends over and is being spaced apart from the active process region of the substrate surface when present. After a pulse of a first reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head, a pulse of a second reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head to react with the first reactant gas to form a portion of the thin layer of ALD film on the surface of substrate underneath the proximity head.
    Type: Application
    Filed: September 6, 2012
    Publication date: February 14, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Hyungsuk Alexander Yoon, Mikhail Korolik, Fritz C. Redeker, John M. Boyd, Yezdi Dordi
  • Patent number: 8372481
    Abstract: The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate within a chamber from a gaseous first precursor. The first species monolayer is discontinuously formed over the substrate. The substrate having the discontinuous first species monolayer is exposed to a gaseous second precursor different from the first precursor effective to react with the first species to form a second species monolayer, and effective to form a reaction product of the second precursor with substrate material not covered by the first species monolayer. The substrate having the second species monolayer and the reaction product is exposed to a third gaseous substance different from the first and second precursors effective to selectively remove the reaction product from the substrate relative to the second species monolayer. Other implementations are contemplated.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: February 12, 2013
    Inventor: Gurtej S. Sandhu
  • Patent number: 8372758
    Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 12, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Sunil Shanker, Tony Chiang
  • Publication number: 20130034467
    Abstract: A microfabricated device is fabricated by depositing a first metal layer on a substrate to provide a first electrode of an electrostatic actuator, depositing a first structural polymer layer over the first metal layer, depositing a second metal layer over said first structural polymer layer to form a second electrode of the electrostatic actuator, depositing an insulating layer over said first structural polymer layer, planarizing the insulating layer, etching the first structural polymer layer through the insulating layer and the second metal layer to undercut the second metal layer, providing additional pre-formed structural polymer layers, at least one of which has been previously patterned, and finally bonding the additional structural layers in the form of a stack over the planarized second insulating layer to one or more microfluidic channels. The technique can also be used to make cross over channels in devices without electrostatic actuators, in which case the metal layers can be omitted.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Applicant: TELEDYNE DALSA SEMICONDUCTOR, INC.
    Inventors: Robert Johnstone, Stephane Martel
  • Patent number: 8367525
    Abstract: A process for forming nanostructures comprises generating charged nanoparticles with an electrospray system and introduction of the charged nanoparticles to a substrate, so that the particles adhere to the substrate in order to form the desired structure. The charged nanoparticles may be directed to a target position by at least one deflector in the electrospray apparatus, which may also include a column optic system. The adhered nanoparticles may be sintered to form the structure. The electrospray apparatus may be single source, multi-source injection, or multi-source selection. An array of electrospray apparatuses with deflectors may be used concurrently to form the structure.
    Type: Grant
    Filed: January 23, 2010
    Date of Patent: February 5, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Joseph M. Jacobson, Jae-bum Joo, Jon Varsanik, Vikrant Agnihotri
  • Publication number: 20130029496
    Abstract: A gas panel according to various aspects of the present invention is configured to deliver a constant flow rate of gases to a reaction chamber during a deposition process step. In one embodiment, the gas panel comprises a deposition sub-panel having a deposition injection line, a deposition vent line, and at least one deposition process gas line. The deposition injection line supplies a mass flow rate of a carrier gas to a reactor chamber. Each deposition process gas line may include a pair of switching valves that are configured to selectively direct a deposition process gas to the reactor chamber or a vent line. The deposition vent line also includes a switching valve configured to selectively direct a second mass flow rate of the carrier gas that is equal to the sum of the mass flow rate for all of the deposition process gases to the reactor chamber or a vent line.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Inventors: Matthias Bauer, Gregory M. Bartlett
  • Publication number: 20130029497
    Abstract: A method is developed to crystallize amorphous silicon (a-Si) thin films, in cold environment, by combining microwave-absorbing materials (MAM) and microwave irradiation. The MAM is set on top or around of the a-Si thin film. MAM composes of dielectric, magnetic, semiconductor, ferroelectric and carbonaceous material oxides, carbides, nitrides and borides, which will absorb and concentrate electric or magnetic field of the microwave. The microwave frequency is selected from 1 to 50 GHz, at a power density not less than 5 W/cm2. Temperature rise of the MAM is monitored and controlled by an optical pyrometer to be less than 600° C., and better be within 400-500° C. The application of MAM at patterned local areas leads to localized heating and crystallization of a-Si film right at the patterns to facilitate manufacture of semiconductor devices.
    Type: Application
    Filed: February 17, 2012
    Publication date: January 31, 2013
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tsung-Shune Chin, Tsun-Hsu Chang, Shih-Chieh Fong, Hsien-Wen Chao
  • Patent number: 8361910
    Abstract: Embodiments of the invention provide methods for forming dielectric materials on a substrate. In one embodiment, a method includes exposing a substrate surface to a first oxidizing gas during a pretreatment process, wherein the first oxidizing gas contains a mixture of ozone and oxygen having an ozone concentration within a range from about 1 atomic percent to about 50 atomic percent and forming a hafnium-containing material on the substrate surface by exposing the substrate surface sequentially to a deposition gas and a second oxidizing gas during an atomic layer deposition (ALD) process, wherein the deposition gas contains a hafnium precursor, the second oxidizing gas contains water, and the hafnium-containing material has a thickness within a range from about 5 ? to about 300 ?. In one example, the hafnium-containing material contains hafnium oxide having the chemical formula of HfOx, whereas x is less than 2, such as about 1.8.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: January 29, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Maitreyee Mahajani
  • Patent number: 8362571
    Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 29, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Haiying Fu, Pramod Subramonium, Jon Henri, Sirish Reddy