Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Abstract: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics.

Abstract: A method of circuit design performed in which a description of a multi-clock-domain circuit is analyzed to locate clock domain crossings. A processor automatically identifies, for at least one of the located clock domain crossings, one or more elements of a synchronization circuit of the clock domain crossing, which require constraining. The processor then generates a constraint for implementation of the identified one or more elements in a design of the circuit.

Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Abstract: The process of implementing a belief propagation network in software and/or hardware can begin with a factor-graph-designer who designs a factor graph that implements that network. A development system provides a user with a way to specify a factor graph at a high or abstract level, and then solve the factor graph, or make an instance of the factor graph in software and/or hardware based on the specification. Factor graphs enable designers to create a graphical model of complicated belief propagation networks such as Markov chains, hidden Markov models, and Bayesian networks.

Abstract: A reconfigurable sensor front-end includes a logic block having a storage circuit to store hardware description information and a reconfigurable block including a plurality of circuits. The plurality of circuits are to be set in a first configuration based on the hardware description information and are to be set in a second configuration when the hardware description information changes. The first hardware description information corresponds to a first sensor and the changed hardware description information corresponding to a second sensor.

Abstract: An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.

Abstract: A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.

Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

Abstract: An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

Abstract: A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.

Abstract: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Abstract: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal.

Abstract: An exemplary embodiment may provide a repository for containing representations that represent a model or a portion of the model. A user may store the representations in the repository, for example, as functions. The functions stored in the repository may be shared and used for processing another model that includes a pattern performing the same or similar function as the representations stored in the repository. A checksum may be compared to determine an equivalent function in the repository. In a different embodiment, the intermediate representation of the pattern may be compared to determine an equivalent function in the repository.

Abstract: A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved.

Abstract: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

Abstract: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

Abstract: A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.

Abstract: An intelligent defect diagnosis method for manufacturing fab is provided. The intelligent defect diagnosis method comprises: receiving pluralities of defect data, design layouts and fabrication data; analyzing the defect data, design layouts, and the fabrication data by a defect analysis system, wherein the analyzing step further contains the sub-steps: segmenting and grouping the design layouts into pluralities of multi-pattern group cells to construct LPG cell based pattern groups; introducing the defect data; segmenting defect image into pluralities of defect and pattern contours; mapping the defect data to each multi-pattern group cell to form the LPG based defect composite pattern group; performing coordinate conversion and pattern match between image contour and design layout for coordinate correction; fulfilling CAA with defect contour, pattern contour and design layout, and obtaining corresponding defect yield; classifying the defect type of defect data through defect image classification analysis.

Abstract: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.

Abstract: A method includes identifying at a first instantiation of a device design and a second instantiation of the device design, determining a first value of an electrical performance characteristic of the first instantiation and a second value of the electrical performance characteristic of the second instantiation, determining that the first instantiation matches the second instantiation, wherein the determining is based on the first value, the second value, and a tolerance, and in response to determining that the first and second instantiations do not match, then identifying a first feature of the first instantiation and changing the first feature of the first instantiation.

Abstract: A high-level synthesis device, which converts a behavior description file describing a function of an integrated circuit using a high-level language without timing description, into a hardware description file describing the integrated circuit including timing description, has: a processor; a high-level synthesis unit in which the processor converts a behavior description file having a functional portion describing the function and a control portion controlling timing, into a first hardware description file; a variable extraction unit; a loop information generation unit; a static latency extraction unit; a latency calculation circuit generation unit in which the processor generates a second hardware description file describing a latency calculation circuit which generates the latency information based on loop count and static latency; and an insertion unit in which the processor inserts the second hardware description file into the first hardware description file to generate a third hardware description file.

Abstract: Methods, systems, and computer program products may provide planning for hardware-accelerated functional verification in data processing systems. A method may include receiving, by a computer system, a description of architecture of a hardware accelerator for accelerating functional verification of a circuit design, the architecture including a plurality of logical processors. The method may additionally include receiving, by the computer system, a description of the circuit design having a plurality of gates, and representing, by the computer system, each gate, each stage of the functional verification, and each logical processor as a separate object based on the received description of the architecture and the circuit design.

Abstract: Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.

Abstract: A method for patterning a workpiece in a direct write machine in the manufacturing of a multilayer stack, wherein a first circuit pattern comprising patterns for connection points is transformed according to determined fitting tolerances to fit to connection points of a second circuit pattern and to circuit pattern(s) of specific features such as random placed dies, or group of dies, on or in the workpiece. The second layer may be a previously formed layer or a layer to be formed on the same workpiece or on a different workpiece for the stack. Pattern data associated with selected die is transformed into adjusted circuit pattern data using the transformation defined by the transformed positions such that the circuit pattern is fitted to the selected die(s).

Abstract: A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes.

Abstract: An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

Abstract: Embodiments of the present invention provide an integrated circuit having analog front end (AFE) circuitry to convert an analog signal to a digital signal, the analog signal being associated with an image captured by a sensor of an imaging device, illumination drive circuitry to drive an illumination source of the imaging device, and one or more transformation elements to operate on the digital signal to provide image correction of the captured image, wherein the AFE circuitry, the illumination drive circuitry, and the one or more transformation elements are integrated on a single chip. Other embodiments may be described and/or claimed.

Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit.

Abstract: The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated circuit that uses complex functions and simple functions, with the complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic pattern minimization.

Abstract: Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are laid out for a given design. Based on the voltage drop calculations and the voltage and current requirement of the various system components, the layout tool may determine if a given system component will remain within its required operating range. The layout tool may additionally be operable to verify proper spacing between traces that make up a differential signal and to verify that certain pins of integrated circuit are properly connected.

Abstract: A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.

Abstract: A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

Abstract: To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and a second power switch configured to decouple a subset of the OTP memory cells from the programming voltage.

Abstract: A variable is allocated to a statement that designates an event associated with a function call in an assertion. Generation of the event at an arbitrary time on a continuous time series is detected, and a value corresponding to a meaning of the statement is assigned to the variable. Whether or not a condition corresponding to the meaning of the statement is satisfied is determined based on the value of the variable at each time on a discrete time series.

Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.

Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

Abstract: A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.

Abstract: In an electronic device and a method of generating composite electrical signals, a plurality of post-processing software is installed. An output file, which comprises times and voltages of data points that represent an electrical signal, of an electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the electrical signal is obtained by selecting an output type of the electrical signal. The worst bit combination of outputs of the electrical signal is analyzed according to the times, the voltage, and the time interval, and a composite electrical signal is generated according to the worst bit combination.

Abstract: A semiconductor platform for implementing multiple-frequency operations includes multiple physical resources comprising embedded functions and a configurable transistor fabric. The transistor fabric includes at least first and second portions, the first portion being programmable to instantiate a first function having higher frequency operations than the second portion. The platform further includes multiple logical resources corresponding to the physical resources of the semiconductor platform and a configurable power mesh to support multiple frequency operations configurable from the transistor fabric. The power mesh includes at least first and second configurable grids. The first configurable grid is operable at a different frequency than the second configurable grid. The power mesh is modifiable, as a function of a desired performance of a customer's requirements, in a vicinity of the first portion of the configurable transistor fabric to support the first function having higher frequency operations.

Abstract: A BiCMOS device structure, method of manufacturing the same and design structure thereof are provided. The BiCMOS device structure includes a substrate having a layer of semiconductor material upon an insulating layer. The BiCMOS device structure further includes a bipolar junction transistor structure formed in a first region of the substrate having an extrinsic base layer formed at least partially from a portion of the layer of semiconductor material.

Abstract: An optical device includes an objective, an eyepiece and a power corrector, each of which includes one or more lenses, and each of which has a respective focal length. The input focal length of the device is defined jointly by the focal lengths of the objective and the power corrector. The magnification of the device is the ratio of the input focal length to the eyepiece focal length. The combined aberration of the eyepiece and the power corrector is less than the characteristic aberration of the eyepiece. The objective, the eyepiece and the power corrector together define an apparent field of view of at least 75 degrees and an exit pupil. The eyepiece lens diameter(s) is/are no greater than twelve times the pupil diameter and three times the eyepiece focal length.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Abstract: A design data dependency managing apparatus comprises an input/output data storing unit for storing design input/output dependency information indicating a dependency between design input/output data, which becomes an input/output of a design, and other design input/output data in association with the design input/output data, and a design execution environment constructing unit for generating design data dependency information indicating a version number, on which a dependency is made, of the design input/output data required for the design by using the design input/output dependency information, and for constructing a design execution environment.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.