Abstract: A method for manufacturing a sloped structure is disclosed. The method includes the steps of: (a) forming a sacrificial film above a substrate; (b) forming a first film above the sacrificial film, the first film having a first portion connected to the substrate, a second portion located above the sacrificial film, a third portion located between the first portion and the second portion, and a thin region in a portion of the third portion or in a boundary section between the second portion and the third portion and having a thickness smaller than the first portion; (c) removing the sacrificial film; and (d) bending the first film in the thin region, after the step (c), thereby sloping the second portion of the first film with respect to the substrate.

Abstract: Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with a small number of processing steps.

Abstract: Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.

Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Abstract: A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.

Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Abstract: One aspect of the invention relates to a method for deposition of a film having a predetermined film composition. The method comprises: in a deposition chamber: providing a substrate at a fixed temperature; depositing a film; flowing a mixture of two gases, wherein the ratio of the two gases is selected such that the mixture has a redox potential to provide a predetermined film composition. In some embodiments, depositing a film occurs via an atomic layer deposition process or chemical vapor deposition process. Methods for chemical vapor deposition of a metal or lanthanide oxide layer are provided featuring a mixture of oxidizing and reducing gases is flowed over the transition metal oxide or lanthanide oxide layer. The mixture of gases has an oxidation potential selected to produce a layer having a desired stoichiometry of a deposited film.

Abstract: A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.

Abstract: Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions.

Abstract: A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.

Abstract: Methods of forming a dielectric layer are described. The methods include the steps of mixing a silicon-containing precursor with a plasma effluent, and depositing a silicon-and-nitrogen-containing layer on a substrate. The silicon-and-nitrogen-containing layer is converted to a silicon-and-oxygen-containing layer by curing in an ozone-containing atmosphere in the same substrate processing region used for depositing the silicon-and-nitrogen-containing layer. Another silicon-and-nitrogen-containing layer may be deposited on the silicon-and-oxygen-containing layer and the stack of layers may again be cured in ozone all without removing the substrate from the substrate processing region. After an integral multiple of dep-cure cycles, the conversion of the stack of silicon-and-oxygen-containing layers may be annealed at a higher temperature in an oxygen-containing environment.

Abstract: The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO2. Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared.

Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.

Abstract: A method for fabricating a semiconductor device, includes dividing a pattern region of a desired pattern that is to be formed on a semiconductor substrate into a plurality of sub-regions; calculating combination condition including a shape of illumination light for transferring and a mask pattern obtained by correcting a partial pattern in the sub-region of the desired pattern formed on a mask used during transferring for each of the plurality of sub-regions, to make a dimension error of the partial pattern of each of the plurality of sub-regions smaller when transferred to the semiconductor substrate; and forming the desired pattern by making multiple exposures on the semiconductor substrate in such a way that the partial patterns of the sub-regions divided are sequentially transferred by transferring a pattern to the semiconductor substrate using the combination conditions calculated for each of the sub-regions.

Abstract: A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.

Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.

Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.

Abstract: A template for imprinting in which a pattern is transferred onto a first substrate applied curable resin thereon, including a second substrate having a surface to be contacted with the curable resin, a concave portion provided on the surface and corresponding to a pattern to be transferred onto the first substrate, and at least one convex portion arranged in the concave portion to decrease volume of

Abstract: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.

Abstract: Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.

Abstract: Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with some embodiments, a deposited silicon nitride film is exposed to curing with plasma and ultraviolet (UV) radiation, thereby helping remove hydrogen from the film and increasing film stress. In accordance with other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

Abstract: Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.

Abstract: There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), and one or more kinds of compounds, represented by the following general formulae (2-1) and/or (2-2), and/or equivalent bodies thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.

Abstract: According to a method for transferring a functional region, at least part of functional regions on separation layers arranged on a first substrate is transferred onto a second substrate, the separation layers being capable of being brought into a separable state by treatment. In a first bonding step, the first substrate is bonded to the second substrate with a dry film resist arranged between the second substrate and the at least part of the functional regions above the first substrate. In an exposure step, at least part of the dry film resist is exposed. In a patterning step, the exposed dry film resist is patterned.

Abstract: A method and apparatus for forming low-k dielectric layers that include air gaps is provided. In one embodiment, a method of processing a substrate is provided. The method comprises disposing a substrate within a processing region, reacting an organosilicon compound, with an oxidizing gas, and a porogen providing precursor in the presence of a plasma to deposit a porogen containing low-k dielectric layer comprising silicon, oxygen, and carbon on the substrate, depositing a porous dielectric capping layer comprising silicon, oxygen and carbon on the porogen containing low-k dielectric layer, and ultraviolet (UV) curing the porogen containing low-k dielectric layer and the porous dielectric capping layer to remove at least a portion of the porogen from the porogen containing low-k dielectric layer through the porous dielectric capping layer to convert the porogen containing low-k dielectric layer to a porous low-k dielectric layer having air gaps.

Abstract: There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or general formula (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.

Abstract: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate, forming a liner layer on a surface of the first trench, forming a sacrificial spacer pattern covering one sidewall of the first trench over the liner layer, forming a second trench by etching the substrate under the first trench using the sacrificial spacer pattern and the liner layer as etch barriers, forming a protection layer on a surface of the second trench, and forming a side contact region by selectively removing the protection layer formed on an upper portion of one sidewall of the second trench.

Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

Abstract: In one example, we describe a new high performance AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET), which was fabricated using HfO2 as the surface passivation and gate insulator. The gate and drain leakage currents are drastically reduced to tens of nA, before breakdown. Without field plates, for 10 ?m of gate-drain spacing, the off-state breakdown voltage is 1035V with a specific on-resistance of 0.9 m?-cm2. In addition, there is no current slump observed from the pulse measurements. This is the best performance reported on GaN-based, fast power-switching devices on sapphire, up to now, which efficiently combines excellent device forward, reverse, and switching characteristics. Other variations, features, and examples are also mentioned here.

Abstract: A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.

Abstract: Disclosed is a heat treatment unit 4 serving as a heat treatment apparatus, which includes a chamber 42 for containing a wafer W on which a low dielectric constant interlayer insulating film is formed, a formic acid supply device 44 for supplying gaseous formic acid into the chamber 42, and a heater 43 for heating the wafer W in the chamber 42 which is supplied with formic acid by the formic acid supply device 44.

Abstract: A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma environment to facilitate adhesion between the diffusion barrier layer and the dielectric layer at an interface region. Also, the method includes processing the semiconductor substrate while maintaining attachment between the dielectric layer and the diffusion barrier layer at the interface region. The subjecting the diffusion barrier layer to a plasma environment includes maintaining a thickness of the barrier diffusion layer.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: Methods of forming a dielectric layer are described. The methods include the steps of mixing a silicon-containing precursor with a plasma effluent, and depositing a silicon-and-nitrogen-containing layer on a substrate. The silicon-and-nitrogen-containing layer is converted to a silicon-and-oxygen-containing layer by curing in an ozone-containing atmosphere in the same substrate processing region used for depositing the silicon-and-nitrogen-containing layer. Another silicon-and-nitrogen-containing layer may be deposited on the silicon-and-oxygen-containing layer and the stack of layers may again be cured in ozone all without removing the substrate from the substrate processing region. After an integral multiple of dep-cure cycles, the conversion of the stack of silicon-and-oxygen-containing layers may be annealed at a higher temperature in an oxygen-containing environment.

Abstract: According to one embodiment, a pattern formation method includes: forming a first pattern in a first region on a substrate to be treated; coating a plurality of types of block copolymers which are different in composition ratio on a second region which is different from the first region; and forming in the second region, by a heat treatment, a second pattern including a plurality of types of structures based on the coated plurality of types of block copolymers.

Abstract: A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1021 cm?3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the <?2110> direction in the sidewall of the trench. A method of manufacturing the silicon carbide semiconductor device is also provided.

Abstract: Methods of nitridation and selective oxidation are provided herein. In some embodiments, a method of selectively forming an oxide layer on a semiconductor structure disposed on a substrate support in a process chamber is provided, wherein the semiconductor structure comprising a substrate, one or more metal-containing layers, and one or more non metal-containing layers. The method may include forming a first remote plasma from a first process gas comprising oxygen; and exposing the semiconductor structure to a reactive species formed from the first remote plasma to selectively form an oxide layer on the one or more non metal-containing layers, wherein a density of the reactive species is about 109 to about 1017 molecules/cm3 and wherein a pressure in the chamber during exposure of the first layer is about 5 mTorr to about 3 Torr.

Abstract: A material substrate is prepared which has a first surface and a second surface opposite to each other in a thickness direction and is made of silicon carbide. The material substrate is partially carbonized to divide the material substrate into a carbonized portion made of a material obtained by carbonizing silicon carbide, and a silicon carbide portion made of silicon carbide. This step of partially carbonizing the material substrate is performed to partially carbonize the second surface. In order to adjust a shape of the material substrate when viewed in a planar view, a portion of the material substrate is removed. This step of removing the portion of the material substrate includes the step of processing the carbonized portion. Accordingly, a silicon carbide substrate having a desired planar shape can be obtained readily.

Abstract: A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.

Abstract: A method of forming a boron nitride or boron carbon nitride dielectric produces a conformal layer without loading effect. The dielectric layer is formed by chemical vapor deposition (CVD) of a boron-containing film on a substrate, at least a portion of the deposition being conducted without plasma, and then exposing the deposited boron-containing film to a plasma. The CVD component dominates the deposition process, producing a conformal film without loading effect. The dielectric is ashable, and can be removed with a hydrogen plasma without impacting surrounding materials. The dielectric has a much lower wet etch rate compared to other front end spacer or hard mask materials such as silicon oxide or silicon nitride, and has a relatively low dielectric constant, much lower then silicon nitride.

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract: Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g.

Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

Abstract: There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern.

Abstract: When forming dielectric materials of reduced dielectric constant in sophisticated metallization systems, the creation of defect particles on the dielectric material may be reduced during a plasma enhanced deposition process by inserting an inert plasma step after the actual deposition step.

Abstract: A method of treating a nanoporous low-k dielectric material formed on a semiconductor substrate is provided. The low-k dielectric material has etched openings with an etch damaged region containing silanol groups on exterior surfaces of the etched openings and on interior surfaces of interconnected pores. First, the low-k dielectric material is contacted with a vapor phase catalyst in an amount effective to form hydrogen bonds between the catalyst and the silanol groups in the etch damaged region, forming a catalytic intermediary.

Abstract: A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillars; depositing a first protective film on the sidewalls of the pillar; first etching the semiconductor substrate with the pillar deposited with the first protective film as a mask; forming a first insulating film on the sidewalls of the pillar and the first etched semiconductor substrate; second etching the semiconductor substrate with the pillar including the first insulating film as a mask; forming a second protective film and a second insulating film on the surface of the second etched semiconductor substrate; depositing a barrier film on the sidewalls of the pillar including the second insulating film; and removing the first insulating film, the second insulating film and the barrier film disposed at one sidewall of the pillar to form a contact hole defined by the first protective film and the second protective film.

Abstract: Methods for reducing defects on the surface of a silicon oxynitride film are disclosed, in one embodiment, the methods include, forming a silicon oxynitride film on a semiconductor substrate and heating the silicon oxynitride film to increase a hydrophilicity of a surface of the silicon oxynitride film prior to treating the surface of the silicon oxynitride film with a hydrofluoric acid.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.