Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: A method of making a semiconductor chip assembly includes providing a post, a base, a support layer and an underlayer, wherein the post extends above the base and the support layer is sandwiched between the base and the underlayer, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a heat spreader that includes the post, the base, the underlayer and a thermal via that extends from the base through the support layer to the underlayer, then mounting a semiconductor device on the post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.

Abstract: A semiconductor device is manufactured using a lead frame for a mold array package (MAP) where multiple mount parts are arranged in the shape of an array, each configured to have a semiconductor chip mounted thereon. Multiple leads for coupling to the semiconductor chip are formed in each of the mount parts of the lead frame. The tips of the leads are mutually coupled by tie bars thinner than the leads. A dummy lead having a slot coupling to the tie bar is formed on a portion corresponding to a portion further outside the tie bar and corresponding to a portion where the lead is formed in the mount parts at predetermined locations among the mount parts. Once the resin is supplied, air in a tie bar part is pushed out into the slot of the dummy lead; therefore, generation of void in the tie bar part can be controlled.

Abstract: A semiconductor device includes a substrate having a conductor; a semiconductor chip disposed on the substrate and electrically connected to the conductor; a tubular electrode having one end electrically connected to the conductor; and a sealing resin sealing the substrate, the semiconductor chip and the electrode. The electrode is configured to be extendable and contractible in the stacking direction in which the substrate and the semiconductor chip are stacked in the state before sealing of the sealing resin. The edge of the other end of the electrode is exposed from the sealing resin. The electrode has a hollow space opened at the edge of the other end. Therefore, a semiconductor device reduced in size and a method of manufacturing this semiconductor device can be provided.

Abstract: Disclosed herein are a substrate for a semiconductor package and a manufacturing method thereof. The substrate for the semiconductor package, which has a single-sided substrate structure including circuit patterns having a connection pad formed on only an electronic component mounting surface, can directly connect a connection pad on the top of the substrate to external connection terminals on the bottom of the substrate through a connection via formed of a metal plating layer formed in an inner wall of the via hole and a conductive metal paste filled in the via hole.

Abstract: A semiconductor package structure and a package process are provided, wherein a lower surface of a die pad of a leadframe is exposed by an encapsulant so as to improve the heat dissipation efficiency of the semiconductor package structure. In addition, two chips are disposed at the same sides of the leadframe and the end portion of each of leads bonding to the upper chip is encapsulated by the encapsulant such that the scratch on the lead tips in wire bonding and die attach steps can be prevented and thus the wire bondability can be enhanced.

Abstract: A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.

Abstract: Disclosed is a granular resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, satisfying the following requirements (a) to (c) on condition that ion viscosity is measured with a dielectric analyzer under a measurement temperature of 175° C. and a measurement frequency of 100 Hz: (a) the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity is 20 seconds or shorter; (b) the lowest ion viscosity value is not more than 6.5; and (c) the time interval between the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity and the time from the initiation of the measurement until the ion viscosity reaching 90% of an ion viscosity value measured at 300 seconds is 10 seconds or longer.

Abstract: A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Abstract: A circuit board structure, a packaging structure and a method for making the same are disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Abstract: A method for making a laminated chip includes: (a) forming a first conductive layer on a substrate; (b) forming an insulating layer on the first conductive layer opposite to the substrate; (c) bombarding the insulating layer using an electron beam to form a plurality of holes that expose the first conductive layer; and (d) forming a second conductive layer on the insulating layer such that a part of the second conductive layer extends into the holes to electrically connect to the first conductive layer.

Abstract: A semiconductor device has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Abstract: A method of manufacturing a semiconductor package is provided, which can improve the quality of plating through reduction of plating deviation, and improve molding and soldering efficiencies in forming a molding compound and packaging the semiconductor package onto a printed circuit board.

Abstract: A contact that takes a structure to laminate a protective conductive film over a metal film has a high hardness of the protective conductive film; therefore, a damage of contact surface made by contacting with an electrode of an inspection apparatus can be prevented in an inspection before boding FPC. However, the protective conductive film has higher resistivity compared to the metal film; therefore, contact resistivity with FPC gets higher, and power consumption gets bigger in the condition of using the display device.

Abstract: A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads.

Abstract: A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.

Abstract: Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.

Abstract: A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.

Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: An electrical connection device and assembly method thereof includes a substrate with a plurality of contacting portions arranged on a surface thereof; a chip module having a plurality of terminals inclining in one direction and compressed and contacted with the contacting portions correspondingly; at least one restricting structure which restricts the chip module to move a distance relative to the substrate depending on the compression deformation of the terminals when the terminals are contacted with the contacting portions; and at least one elastic element just producing deformation when the chip module moves the distance. When the terminals are compressed and contacted with the contacting portions, the restricting structure restricts the chip module to move the distance depending on the compression deformation of the terminals, so that the elastic element just produces deformation, which make the chip module only move in the direction opposite to the deformation direction of the terminals.

Abstract: A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

Abstract: A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.

Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.

Abstract: A method of forming a microelectronic package including the steps of providing a three-layer metal plate, having a first layer, a second layer and a third layer. A plurality of conductive elements is formed from the first layer of the metal plate. A dielectric sheet is attached to the first layer of the metal plate, such that the dielectric sheet is remote from the third layer. A plurality of conductive features is then formed from the third layer of the metal plate which are also remote from the dielectric sheet. A microelectronic element is next electrically conducted to the conductive elements and a heat spreader is thermally connected the microelectronic element.

Abstract: A method and apparatus are described for fabricating a low-pin-count chip package (701) including a die pad (706) for receiving an integrated circuit device and a plurality of connection leads (702) having recessed lead ends (704) at the outer peripheral region of each contact lead. After forming the package body (202) over the integrated circuit device, unplated portions (104) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends (302) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated (402) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer first side and an interposer second side opposing the interposer first side; mounting an integrated circuit to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer; connecting first interconnects between the active side and the interposer first side, the first interconnects having a first density on the interposer first side; mounting the interposer over a package carrier with the interposer first side facing the package carrier; connecting second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density that is approximately the same as the first density; and forming an encapsulation over the package carrier covering the interposer and the second interconnects.

Abstract: A method for manufacturing an integrated circuit package system includes: providing a leadframe; forming a protruding pad on the leadframe; attaching a die to the leadframe; electrically connecting the die to the leadframe; and encapsulating at least portions of the leadframe, the protruding pad, and the die in an encapsulant.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed; and attaching a base substrate connector to the base substrate directly below the leadframe pillar.

Abstract: The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

Abstract: A wiring board has a structure where multiple wiring layers are stacked one on top of another with insulating layers interposed therebetween. A sheet-shaped member is buried in an outermost insulating layer located on a side of the structure opposite to a side on which a semiconductor element is to be mounted. The sheet-shaped member has a modulus of elasticity and a coefficient of thermal expansion which are similar to a modulus of elasticity and a coefficient of thermal expansion of the semiconductor element. The sheet-shaped member is made of a material having a modulus of elasticity and a coefficient of thermal expansion which are enough to bring respective distributions thereof into a substantially symmetric form in a direction orthogonal to a surface of the wiring board in the case where the semiconductor element is mounted.

Abstract: A method of manufacturing a semiconductor device or a substrate is described. The method includes providing a chip attached to a carrier or providing a substrate. A foil is held over the chip and the carrier or the substrate. A laser beam is directed onto the foil, and substance at the foil is ablated and deposited on the chip and the carrier or on the substrate.

Abstract: A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board.

Abstract: An integrated circuit (IC) package that includes a lead frame, and a die affixed to a first surface of a pad of the lead frame. The die is wire bonded to the lead frame. The package includes a heat sink spaced apart from a second surface of the pad, where the second surface opposes the first surface. Molding compound encapsulates the lead frame and the die. The molding compound is disposed between the heat sink and the second surface of the pad and is enabled access between the heat sink and the second surface through protruding features disposed on the heat sink, the second surface, and/or some combination of the two.

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Abstract: A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound.

Abstract: A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally, the method includes steps of: (i) mounting the die on which the device is fabricated to a die paddle of a leadframe; and (ii) encapsulating the die on the die paddle and at least a portion of the leadframe in a molding compound, wherein a difference between a first volume of molding compound above a plane of the leadframe and a second volume of molding compound below the plane of the leadframe is sufficiently reduced to substantially eliminate warpage of the finished package due to mismatch of CTEs of the device, lead frame and packaging compound. The die paddle may be etched or reduced to facilitate molding compound flowing under the plane of the leadframe. Other embodiments are also disclosed.

Abstract: An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least a portion of a loop; the wire ends (104a) are connected to the chips. The assembly is attached to a substrate (103), which may be a leadframe. The device may be encapsulated in molding compound (140) so that the inductor can double as a heat spreader (111c), enhancing the thermal device characteristics.

Abstract: Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a second surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semiconductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit device is described.

Abstract: A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.

Abstract: A semiconductor wafer has a plurality of semiconductor die. First and second conductive layers are formed over opposing surfaces of the semiconductor die, respectively. Each semiconductor die constitutes a WLCSP. A TSV is formed through the WLCSP. A semiconductor component is mounted to the WLCSP. The first semiconductor component is electrically connected to the first conductive layer. A first bump is formed over the first conductive layer, and a second bump is formed over the second conductive layer. An encapsulant is deposited over the first bump and first semiconductor component. A second semiconductor component is mounted to the first bump. The second semiconductor component is electrically connected to the first semiconductor component and WLCSP through the first bump and TSV. A third semiconductor component is mounted to the first semiconductor component, and a fourth semiconductor component is mounted to the third semiconductor component.

Abstract: An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

Abstract: A semiconductor package includes a semiconductor device and a substrate over which the semiconductor device is mounted, wherein the substrate includes: an internal ground electrode, formed in the one side of the substrate, which is connected to the semiconductor device; two external ground electrodes, located at the opposite side of the substrate opposite to the one side of the substrate, which are electrically connected to the internal ground electrode; at least one sub-ground electrode, located between the two external ground electrodes, when seen in a plan view, and located at the opposite side of the substrate, which is electrically connected to the internal ground electrode; an internal input electrode, formed in the one side of the substrate, which is connected to the semiconductor device; and an internal output electrode, formed in the one of the substrate, which is connected to the semiconductor device.

Abstract: A connecting pad producing method has a first process of projecting an insulating member in a surface of a base material such that a region where a connecting pad is formed is surrounded, a second process of forming a conductive layer in the surface of the base material such that the insulating member is coated with the conductive layer, and a third process of removing the conductive layer with which the insulating member is coated, exposing the insulating member over a whole periphery from the conductive layer, and forming the connecting pad including the conductive layer in a region surrounded by the insulating member.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a carrier having a cavity and a carrier top side adjacent to the cavity; mounting an integrated circuit in the cavity; forming an encapsulation surrounding the integrated circuit; and attaching a conductive channel to the carrier top side, the conductive channel over the encapsulation.

Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

Abstract: In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; attaching a base barrier on the base substrate adjacent a base perimeter thereof; mounting a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; and dispensing a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier.