Abstract: A probe apparatus exchanging signals with a target device, includes: a contact section electrically connected to the target device by contacting a terminal of the target device; a non-contact section that exchanges signals with the target device in a state not contacting the terminal of the target device; and a retaining section that retains the contact section and the non-contact section, in such a manner that a relative position between the contact section and the non-contact section in a connection direction connecting the non-contact section and a region corresponding to the target device is displaceable.

Abstract: The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening.

Abstract: Provided is a test apparatus for testing a plurality of devices under test formed on a semiconductor wafer, including: a probe card to be connected to respective contacts of the plurality of the devices under test on a connection surface to be overlapped on the semiconductor wafer, the probe card being provided with a plurality of corresponding contacts on a rear surface of the connection surface; and a test head that tests the plurality of devices under test on the semiconductor wafer by sequentially connecting to each part of the plurality of contacts of the probe card.

Abstract: An apparatus for testing electric characteristics of a test object including first connection terminals on a bottom surface and second connection terminals on a top surface, the apparatus comprises a test board comprising first pads on a predetermined surface; a socket configured to electrically connect the test object to the test board; and a handler configured to transport the test object to the socket. The socket comprises a first connection unit configured to be electrically connected to the first connection terminals of the test object and a second connection unit configured to be electrically connected to the second connection terminals of the test object.

Abstract: A four-wire ohmmeter connector includes a pair of elongated members spaced apart from each other by an interconnecting web. A pair of elongated contacts are mounted on forwardly projecting portions of each of the elongated members. An insulative housing surrounds the elongated members, contacts and web. The contacts mounted on one of the elongated members are connected through separate wires to a positive probe, and the contacts mounted on the other of the elongated members are connected through separate wires to a negative probe. The elongated members are inserted into respective terminal apertures of a four-wire ohmmeter. A pair of semi-cylindrical conductive sleeves are aligned with each of the apertures, and they make contact with and compress the respective contacts that are inserted into the aperture.

Abstract: A probe head for testing semiconductor wafers has a probe contactor substrate have a first side and a second side. A plurality of probe contactor tips are coupled to the first side and the plurality of tips lie in a first plane. A plurality of mounting structures are coupled to the second side with each of the mounting structures each having a top surface lying in a second plane, wherein the first plane is substantially parallel to the second plane.

Abstract: A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.

Abstract: A measuring equipment, such as a vector network analyzer, is provided. The measuring equipment includes a first port and a second port, a probe connected to the first port, an antenna connected to the second port, and a test board corresponding to a type of a device-under-test. A probe-effect is obtained by measuring the test board via the probe and the antenna.

Abstract: A needle trace transfer member to which needle traces of probes are transferred is installed at a movable mounting table to align the probes before electrical characteristics of a target object on the mounting table are inspected by bringing the probes into electrical contact with the target object. The needle trace transfer member is made of a shape memory polymer transformed reversibly and rapidly between a glass state with a high modulus elasticity and a rubber state with a low modulus of elasticity near its glass transition temperature. The glass transition temperature is set to a temperature close to a set temperature of the mounting table. The shape memory polymer is mainly made of polyurethane-based resin.

Abstract: A probe apparatus and method of terminating a probe that probes a semiconductor device with a signal cable from a tester side by side at a proximal end of the probe and a distal end of the signal cable. In one embodiment, the probe apparatus includes: a chassis; a dielectric block mounted in the chassis for retaining the probe, the probe extending on the chassis from a proximal end of the probe to the dielectric block, extending through the dielectric block, and projecting from the dielectric block towards the semiconductor device at a distal end of the probe; and a terminating apparatus, mounted in the chassis, for terminating the proximal end of the probe with a distal end of the signal cable side by side.

Abstract: A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.

Abstract: A test apparatus that test a device under test, comprising a test head that is arranged facing the device under test and that includes a test module for testing the device under test, and a probe assembly that transmits a signal and that is arranged between the test head and the device under test. The probe assembly includes a plurality of low voltage pins arranged at prescribed intervals from each other, and a plurality of high voltage pins that are arranged such that distance between each high voltage pin and each low voltage pin is greater than the prescribed interval, and that transmit a signal with a higher voltage than a signal transmitted by the low voltage pins. All of the high voltage pins are arranged in only one of two regions formed by dividing a surface of the probe assembly in half.

Abstract: A method of performing a function on a three-dimensional semiconductor chip package as well as on individual chips in the package is disclosed. That method involves the creation of an operative relationship between a function performer and an edge feature on the chip or chips wherein the edge feature consists of one or more of an electrically conductive pad, thermally conductive pad, a probe pad, a fuse, a resistor, a capacitor, an inductor, an optical emitter, an optical receiver, a test pad, a bond pad, a contact pin, a heat dissipator, an alignment marker, a metrology feature and a function performer may be any one or more of a test probe, the laser, a programming device, an interrogation device, a loading device or a tuning device. In addition, a chip per se with edge features is disclosed along with a three-dimensional stack of such chips in either of several different configurations.

Abstract: A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response to a corresponding base step signal. The signals outputs may be provided to a test fixture, for testing a multi-pin integrated circuit (IC).

Abstract: Probe pins related to the present invention are formed from a material which consists essentially of one or more elements selected from the group consisting of platinum, iridium, ruthenium, osmium, palladium and rhodium. A material obtained by adding one or more elements selected from the group consisting of tungsten, nickel and cobalt to this metal may also be used.

Abstract: An object of the present invention is to obtain a clear absorbed current image without involving the difference in gain of amplifier between inputs, from absorbed currents detected by using a plurality of probes and to improve measurement efficiency. In the present invention, a plurality of probes are brought in contact with a specimen. While irradiating the specimen with an electron beam, currents flowing in the probes are measured. Signals from at least two probes are input to a differential amplifier. An output of the differential amplifier is amplified. On the basis of the amplified output and scanning information of the electron beam, an absorbed current image is generated. According to the invention, a clear absorbed current image can be obtained without involving the difference in gain of amplifier between inputs. Thus, measurement efficiency in a failure analysis of a semiconductor device can be improved.

Abstract: Systems and methods for simultaneous optical testing of a plurality of devices under test. These systems and methods may include the use of an optical probe assembly that includes a power supply structure that is configured to provide an electric current to a plurality of devices under test (DUTs) and an optical collection structure that is configured to simultaneously collect electromagnetic radiation that may be produced by the plurality of DUTs and to provide the collected electromagnetic radiation to one or more optical detection devices. The systems and methods also may include the use of the optical probe assembly in an optical probe system to evaluate one or more performance parameters of each of the plurality of DUTs.

Abstract: An inspection unit includes: a metal block having a through hole; a contact probe for grounding which is coaxially arranged in through hole; and a coil spring having electrical conductivity at least on a surface thereof and provided between an inner peripheral face of the through hole and an outer peripheral face of the contact probe. The coil spring includes: a first coil part a part of which is in contact with the inner peripheral face of the through hole; and a second coil part a part of which is in contact with the outer peripheral face of the contact probe.

Abstract: A testing device suitable for a testing apparatus with light inspection of a display panel is provided, in which the testing device includes a main part and two contact parts. The testing device is fixed to the testing apparatus with light inspection by the main part. Two contact parts are respectively extended from two ends of the main part along a first direction, and each of the contact parts has a plurality of tips. The tips of each contact part have different heights. Besides, a testing apparatus is also provided. Therefore, the abovementioned testing device and the testing apparatus are able to drastically extend the user lifetime, improve the inspection accuracy and save cost.

Abstract: Installed in a probe device is a holding member for inspection which can be mounted on a chuck. The holding member for inspection includes a support plate capable of mounting thereon a chip in which the power device is formed; pins for positioning the chip mounted on the support plate; and a metal film formed on a surface of the support plate in a range from a mounting area on which the chip is mounted to an exposed area on which the chip is not mounted. When inspecting the power device, the chip is fixed onto the mounting area in the holding member for inspection, one probe pin is brought into contact with a terminal on a top surface of the chip; and another probe pin is brought into contact with the metal film in the exposed area.

Abstract: A method and system for testing a semiconductor package. At least some of the illustrative embodiments are methods comprising testing a semiconductor package unit (150, 420) by electrically coupling a top printed circuit board (208, 420) to a top-side of a semiconductor package unit (150, 420), the coupling using electrically conductive top-side pogo pins (201A, 420), and a pair of adjacent top-side pogo pins (201A, 420) bridged using an electrically conductive path (302, 420), electrically coupling a bottom printed circuit board (210, 430) to a bottom-side of the semiconductor package unit (150, 430), the coupling using electrically conductive bottom-side pogo pins (201B, 430), said top-side pogo pins (201A, 430) and said bottom-side pogo pins are of substantially equal height (201B, 430), and transmitting test signals from the bottom printed circuit board to the semiconductor device package by way of the bottom-side pogo pins (210, 440).

Abstract: Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.

Abstract: Embodiments of the present invention are directed to adjustable test probe tips that are indexable. In one embodiment a mechanism is coupled to a probe tip so that the mechanism may be used to index the probe tip to a plurality of particular positions. A label portion may be provided to communicate to a user that the length of the exposed probe tip is less than a particular length, such as the maximum length an exposed probe tip may be for a particular application.

Abstract: A probe card includes a probe head that holds a plurality of probes; a flat wiring board that has a wiring pattern corresponding to a circuit structure; an interposer that is stacked on the wiring board and relays wirings of the wiring board; a space transformer that is placed between the interposer and the probe head, transforms a space between the wirings relayed by the interposer, and leads the transformed wirings out to a surface facing the probe head; and a plurality of post members that are formed in a substantially columnar shape with a height larger than a sum of a thickness of the wiring board and a thickness of the interposer, and embedded to pierce through the wiring board and the interposer in a thickness direction such that one of end surfaces of each post member comes into contact with the space transformer.

Abstract: A probe card includes probes that come into contact with a semiconductor wafer to receive or output an electric signal; a probe head that holds the probes; a substrate that has a wiring pattern corresponding to a circuit structure for generating a signal for a test; a reinforcing member that reinforces the substrate; an interposer that is stacked on the substrate and includes a housing having connection terminals resilient in an axial direction thereof and hole portions each housing one of the connection terminals; and a space transformer that is stacked between the interposer and the probe head and transforms intervals among the wires.

Abstract: A contact apparatus can be made by providing a first substrate with electrically conductive terminals and second substrates each of which can have contact structures. Each of the contact structures can have a contact tip. The second substrates can be aligned such that contact tips of the contact structures are aligned substantially in a plane. An optical system can be used to monitor an actual position of the second substrates, and a mechanical system can be used to move the second substrates to aligned positions. The contact structures can be attached to ones of the terminals on the first substrate while the second substrates are in the aligned positions.

Abstract: An audit device according to one embodiment includes a substrate; at least one test element coupled to the substrate; a connector adapted for coupling the at least one test element to leads of a cable; and a probe for detecting at least one of: voltage across and current through the at least one test element. Additional systems and methods are also presented.

Abstract: [Problems to be solved] To provide a test-use individual substrate capable of improving testing accuracy and connecting reliability. [Means for solving the Problems] A test-use individual substrate 30 which is used for testing a semiconductor wafer, comprises a main body portion 31, thin portions 321, 322 extending from the main body portion 31 and being relatively thinner than the main body portion, and bumps 33 provided on the thin portions 321, 322. [Selected Drawing] FIG.

Abstract: The invention relates to a probe card assembly comprising a stiffener (1), comprising a PCB (2) disposed in the stiffener (1), and comprising a spider (3) supported by the stiffener and the PCB (2), said spider comprising at least one probe (30) to test a wafer (5). This probe card assembly of the PCB (2) is supported in a loosely decoupled manner in the stiffener (1) to prevent transmission of high thermally-induced warping effects.

Abstract: Embodiments of the invention describe forming a set of probes using semiconductor regions each including a plurality of vias. A first set of probe segments may be formed from a first set of vias on a first semiconductor region. A second set of probe segments may be formed from a second set of vias on a second semiconductor region and bonded to the first set of probe segments. At least one spring comprising a dielectric material may be formed to couple the first set of probe segments, while a set of metal tips disposed on the second set of probe segments.

Abstract: An improved knee probe for probing electrical devices and circuits is provided. The improved knee probe has a reduced thickness section to alter the mechanical behavior of the probe when contact is made. The reduced thickness section of the probe makes it easier to deflect the probe vertically when contact is made. This increased ease of vertical deflection tends to reduce the horizontal contact force component responsible for the scrub motion, thereby decreasing scrub length. Here “thickness” is the probe thickness in the deflection plane of the probe (i.e., the plane in which the probe knee lies). The reduced thickness probe section provides increased design flexibility for controlling scrub motion, especially in combination with other probe parameters affecting the scrub motion.

Abstract: The invention relates to a contacting unit for a test apparatus for testing printed circuit boards. The contacting unit comprises a full grid cassette and an adapter. The full grid cassette is provided with a plurality of spring contact pins arranged in the grid of contact points of a basic grid of a test apparatus. The adapter is provided with test needles for electrically connecting each of the spring contact pins of the full grid cassette to a circuit board test point of a printed circuit board to be tested, the spring contact pins being secured in the full grid cassette against falling out on the side remote from the adapter and the test needles being secured in the adapter on the side remote from the full grid cassette. The adapter and the full grid cassette are releasably joined to each other. In this way, both the spring contact pins and the test needles are secured against falling out of the contacting unit in the assembled state of the adapter and the full grid cassette.

Abstract: A test fixture (120) is disclosed for electrically testing a device under test (130) by forming a plurality of temporary mechanical and electrical connections between terminals (131) on the device under test (130) and contact pads (161) on the load board (160). The test fixture (120) has a replaceable membrane (150) that includes vias (151), with each via (151) being associated with a terminal (131) on the device under test (130) and a contact pad (161) on the load board (160). In some cases, each via (151) has an electrically conducting wall for conducting current between the terminal (131) and the contact pad (161). In some cases, each via (151) includes a spring (152) that provides a mechanical resisting force to the terminal (131) when the device under test (130) is engaged with the test fixture (120).

Abstract: A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.

Abstract: A charge eliminating apparatus eliminates, when an electrical characteristics test of a target object is performed by moving a mounting table mounting the target object thereon and a probe card relative to each other to bring the target object into electrical contact with the probe card, static electricity of the target object via the mounting table. The charge eliminating apparatus includes a grounding wiring for grounding the mounting table; a relay switch disposed on the grounding wiring; and a switch controller that controls the relay switch to be opened or closed.

Abstract: A contact for an electrical test comprises a first area to be bonded to a board, a second area extending in the right-left direction from the lower end portion of the first area, a third area projecting downward from the tip end portion of the second area, and a low light reflective film having lower light reflectance than that of the first area. The third area has a probe tip to be contacted an electrode of an electronic device. The low light reflective film is formed on a surface of at least the bonding part of the first area to the board and its proximity.

Abstract: An embodiment of a method is proposed for producing cantilever probes for use in a test apparatus of integrated electronic circuits; the probes are configured to contact during the test corresponding terminals of the electronic circuits to be tested. An embodiment comprises forming probe bodies of electrically conductive materials. In an embodiment, the method further includes forming on a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

Abstract: A radiofrequency contactor includes a testing circuit board having a dielectric substrate, a lower ground conductor on a lower surface of the dielectric substrate, and a radiofrequency signal wiring conductor on an upper surface of the dielectric substrate, a radiofrequency signal pin contactor located on the upper surface of the dielectric substrate and connected to the radiofrequency signal wiring conductor, a ground block located on the upper surface of the dielectric substrate and spaced apart from the radiofrequency signal wiring conductor and the radiofrequency signal pin contactor, and a first side ground conductor and a second side ground conductor provided on the upper surface of the dielectric substrate and spaced apart from the radiofrequency signal wiring conductor and the radiofrequency signal pin contactor.

Abstract: A probe test card assembly for testing a device under test includes interposer probes to connect a printed circuit board to a substrate. The probe test card assembly includes a printed circuit board, a substrate and a substrate holder. A plurality of test probes is connected to the substrate for making electrical contact with the device under test. A plurality of interposer probes is attached to the substrate for providing electrical connections between the substrate and the printed circuit board. The substrate holder holds the substrate in position with respect to the printed circuit board so that the interposer probes contact the printed circuit board. The interposer probes may be arranged in interposer probe groups to facilitate maintenance and replacement of the interposer probes. Hardstop elements may also be used to protect the interposer probes.

Abstract: A vertically folded probe is provided that can provide improved scrub performance in cases where the probe height is limited. More specifically, such a probe includes a base and a tip, and an arm extending from the base to the tip as a single continuous member. The probe arm is vertically folded, such that it includes three or more vertical arm portions. The vertical arm portions have substantial vertical overlap, and are laterally displaced from each other. When such a probe is vertically brought down onto a device under test, the probe deforms. During probe deformation, at least two of the vertical arm portions come into contact with each other. Such contact between the arm portions can advantageously increase the lateral scrub motion at the probe tip, and can also advantageously reduce the probe inductance.

Abstract: The invention relates to a contactless measuring system having at least one test probe forming part of a coupling structure for the contactless decoupling of a signal running on a signal waveguide, wherein the signal waveguide is designed as a conductor of the electric circuit on a circuit board and as part of an electric circuit. To this end, at least one contact structure is configured and disposed on the circuit board such that said contact structure is galvanically separated from the signal waveguide, forms part of the coupling structure, is displaced completely within the near field of the signal waveguide, and has at least one contact point, which may be electrically contacted by a contact of the test prod.

Abstract: This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

Abstract: An electronic component contactor includes a plurality of contact pins, a housing that encases and determines positions of the plurality of contact pins, and a buffer member that buffers against the behavior of the contact pins. The contact pins each includes a base portion, a stretch portion that stretches from the base portion in an arc shape, a contact portion that is formed in the stretch portion, and a load receiving portion. The housing includes a support base in which a surface supporting the buffer member is formed to be flat. The buffer member is formed in a sheet-like shape. A portion of the buffer member that faces the load receiving portion is supported by the support base.

Abstract: The voltage application probe and the voltage measurement probe are connected to the voltage application pad and the voltage measurement pad of the semiconductor device. The voltage application pad and the voltage measurement pad are connected by the conductor, measuring the voltage applied to the voltage application pad through the voltage measurement probe. The voltage compensation circuit in the voltage development device operates to make the voltage applied to the voltage application pad equal to the set voltage for the voltage development device. Even when the resistance between the voltage application probe and the voltage application pad increases, the accurate setting voltage is applied to the voltage application pad.

Abstract: A test configuration for double sided probing of a device under test includes a holder to secure the device under test in a first orientation, a calibration substrate secured in a second orientation and a probe capable of calibration using the calibration substrate and probing the device under test.

Abstract: A contactor includes a contactor base material including a first material and a conductor film including a second material. The conductor film is formed only on a contact surface with an electrode of a semiconductor apparatus at a tip of the contactor film.

Abstract: A system and method for identifying opens among parallel connections on a circuit assembly such as a printed circuit board (PCB). In a learn phase performed on a known good circuit assembly, a group of parallel connected pins are excited with a first signal. A second signal, out-of-phase with the first signal, is applied to a second group of pins associated with the component. The amplitude and/or the phase of the second signal and the number and/or specific pins in the second group of pins are selected so that first and second signals coupled to a detector plate proximal to the component substantially offset. During a manufacturing test, signals of comparable amplitude and phase are applied to like pins on a like component of a circuit assembly under test. If the response signal coupled to a like detector plate is below a threshold, it is determined that each pin in the group of parallel connected pins is connected.

Abstract: To facilitate connection between a narrow-pitched probe assembly and a coarse-pitched printed circuit board.

Abstract: One embodiment is a probe head for contacting microelectronic devices substantially lying in a test plane, the probe head including: (a) one or more substrate tiles having one or more probe tips disposed on a top surface thereof; and (b) a registration-alignment apparatus that holds the one or more substrate tiles: (i) in position so that the one or more probe tips are held in the test plane, and (ii) aligned so that the one or more probe tips are substantially coplanar to the test plane, which registration-alignment apparatus includes: (i) one or more capture elements affixed, directly or indirectly, to a frame; (ii) three or more posts mechanically supporting each of the one or more substrate tiles; and (iii) alignment actuators affixed, directly or indirectly, to the frame and the posts, which alignment actuators may be actuated to enable the posts to move in response to forces applied thereto from the one or more substrate tiles, and may be actuated to prevent the posts from moving.

Abstract: A probe for engaging a conductive pad is provided. The probe includes a probe contact end for receiving a test current, a probe retention portion below the contact end, a block for holding the probe retention portion, a probe arm below the retention portion, a probe contact tip below the arm, and a generally planar self-cleaning skate disposed perpendicular below the contact tip. The self-cleaning skate has a square front, a round back and a flat middle section. The conductive pad is of generally convex shape having a granular non-conductive surface of debris and moves to engage the skate, whereby an overdrive motion is applied to the pad causing the skate to move across and scrub non-conductive debris from the pad displacing the debris along the skate and around the skate round back end to a position on the skate that is away from the pad.