Connection Of Components To Board Patents (Class 361/760)
  • Patent number: 8982564
    Abstract: An electronic device includes a printed circuit board that has a prohibited region, in which arrangement of a wiring pattern is prohibited, in a fixed region from an outer periphery, an electronic component mounted on the printed circuit board, a heat dissipation fin provided on the electronic component, and a fixing unit that is made of a conductive material and fixes the heat dissipation fin by pressing the fin against the printed circuit board side, wherein a notch is formed in two sides of the printed circuit board that face each other with the electronic component therebetween, and the fixing unit exerts an elastic force that presses the heat dissipation fin against the printed circuit board side by being locked to the notch and is such that hook portions locked to the notch are arranged in the prohibited region.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: March 17, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noboru Nishihara, Koichi Tatsuyama, Hiroshi Mihara
  • Patent number: 8982561
    Abstract: A lightweight radio/CD player for vehicular application includes a case and frontal interface formed of polymer based material molded to provide details to accept audio devices and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: March 17, 2015
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris R. Snider, Vineet Gupta, Joseph K. Huntzinger, Michael G. Coady, Curtis Allen Stapert, Kevin Earl Meyer, Timothy D. Garner, Allen E. Oberlin
  • Publication number: 20150070861
    Abstract: According to certain aspects, a circuit board panel includes a first module circuit board and a second module circuit board arranged to define a space that runs between a first portion of the periphery of the first module circuit board and a portion of the periphery of the second module circuit board; and a plurality of shield components each extending across the space and including a first conductive portion mounted along the first portion of the periphery of the first module circuit board, a second conductive portion mounted along the portion of the periphery of the second module circuit board, and a non-conductive portion extending between the first conductive portion and the second conductive portion, the first and second conductive portions of each of the plurality of shield components configured to provide electromagnetic shielding for at least one electronic component mounted on the first and second module circuit boards, respectively.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 12, 2015
    Inventors: Philip H. Thompson, Larry D. Pottebaum
  • Publication number: 20150072196
    Abstract: A printed circuit board (PCB) assembly may include a PCB and a high current interconnect mounted on the PCB. The high current interconnect may be configured to electrically couple a first high current bladed component, a second high current bladed component, and a trace disposed on the PCB. The high current interconnect may include feet made of a conductive material that are coupled to the PCB. The trace may be coupled to the feet via a weld.
    Type: Application
    Filed: March 31, 2014
    Publication date: March 12, 2015
    Applicant: Johnson Controls Technology Company
    Inventors: Edward J. Soleski, Richard M. DeKeuster, Brian L. Thieme, Ronald J. Dulle, Mikhail S. Balk
  • Patent number: 8975755
    Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 10, 2015
    Assignee: Xintec Inc.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin
  • Patent number: 8975535
    Abstract: In a many-up wiring substrate including a base substrate having dividing grooves formed as part of main surfaces thereof, along boundaries of a plurality of wiring substrate regions, the plurality of wiring substrate regions being arranged in a matrix, when seen in a transparent plan view, dividing grooves of the main surface and dividing grooves of an opposite main surface are formed to be deviated in one direction of transverse direction or longitudinal direction, and a distance between bottoms of the dividing grooves of one main surface and bottoms of the dividing grooves of the opposite main surface is smaller than a distance between the bottoms of the dividing grooves of the one main surface and the opposite main surface and a distance between the bottoms of the dividing grooves of the opposite main surface and the one main surface.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: March 10, 2015
    Assignee: KYOCERA Corporation
    Inventors: Kazuhito Imamura, Yousuke Moriyama
  • Patent number: 8975529
    Abstract: There is provided an interposer which meets the need of improving electrical reliability of an electronic device. An interposer includes a substrate including a penetrating-hole in a thickness direction thereof, and a penetrating conductor disposed in the penetrating-hole. The substrate includes a first insulating layer and a second inorganic insulating layer which are separated from each other in the thickness direction, and a first resin layer interposed between the first inorganic insulating layer and the second inorganic insulating layer and being in contact with the first inorganic insulating layer and the second inorganic insulating layer. A coefficient of thermal expansion of the first resin layer in thickness and planar directions thereof is larger than those of the first inorganic insulating layer and the second inorganic insulating layer.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Kyocera Corporation
    Inventor: Katsura Hayashi
  • Publication number: 20150062846
    Abstract: Provided is a printed circuit board, including: a core substrate including an internal circuit pattern on an upper surface or a lower surface; electronic devices which are formed to pass through the core substrate; an external insulating layer which covers the internal circuit pattern and the electronic devices; and an external circuit pattern which is formed on an upper surface of the external insulating layer, wherein a lower surface of the electronic devices protrudes from the lower surface of the core substrate to a lower part. Accordingly, in the embedded printed circuit board in which the electronic devices are embedded, when the electronic devices are mounted, because the insulating layer is formed regardless of a thickness of the electronic devices, the printed circuit board having a desired thickness regardless of the thickness of the electronic devices can be formed.
    Type: Application
    Filed: February 25, 2013
    Publication date: March 5, 2015
    Inventors: Ji Su Kim, Ki Do Chun, Kyu Won Lee, Sang Myung Lee
  • Publication number: 20150062847
    Abstract: A component connection member, a mobile communication device comprising the same and a manufacturing method thereof include: a support structure, which is mounted on a substrate, formed to have at least one bent part; a first contact part connected to one end of the support structure and formed to come into contact with and be electrically connected to a first component disposed facing a first surface of the substrate; and a second contact part connected to the other end of the support structure and formed to come into contact with and be electrically connected to a second component disposed facing a second surface adjacent to the first surface of the substrate or a third surface opposite to the first surface of the substrate.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 5, 2015
    Inventor: Sung June Park
  • Patent number: 8964410
    Abstract: A transformer has two magnetic cores, at least one primary winding unit mounted in the magnetic cores, at least one secondary winding unit mounted in the magnetic cores and two rectifying circuit boards externally mounted beside the magnetic cores. An AC voltage output from the secondary winding unit is transmitted to and rectified by the rectifying circuit board. Therefore, the size of the transformer is compact, and heat energy generated by electronic elements mounted on the rectifying circuit board is effectively dissipated to maintain normal operation of the transformer. Further, since the transmission path from the secondary winding unit to the rectifying circuit board is short, energy loss is reasonably reduced when the transformer is operated under a high frequency situation or a larger current mode.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: February 24, 2015
    Assignee: Acbel Polytech Inc.
    Inventors: Shun-Te Chang, Chien-Hua Wu, Chia-An Yeh, Hsiang-Yu Hung
  • Patent number: 8964403
    Abstract: There is provided a wiring board including a multilayer substrate and a reinforcing member. The multilayer substrate has a first main substrate surface formed with a chip mounting area to which an electronic chip is mounted and a second main substrate surface opposed to the first main substrate surface. The reinforcing member is fixed to either an area of the first main substrate surface other than the chip mounting area or the second main substrate surface and has a body predominantly formed of ceramic material and incorporating therein at least one capacitor.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: February 24, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Seigo Ueno
  • Patent number: 8964395
    Abstract: Cooling airflow through an information handling system is redirected at positions of a motherboard having an unpopulated processing component towards positions of the motherboard having processing components. For example, a shroud shaped as a nozzle couples to a heat sink connector of the motherboard to cover an unpopulated CPU socket. The shroud has a nozzle-shaped channel with an inlet accepting cooling airflow and an outlet exhausting the cooling airflow towards a processing component. For instance, the inlet is proximate a cooling fan and the outlet directs the airflow from the cooling fan towards a heat sink associated with RAM populated on the motherboard.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: February 24, 2015
    Assignee: Dell Products L.P.
    Inventors: Darren B. Pav, David McKinney
  • Patent number: 8964402
    Abstract: An electronic device includes a wiring board including a first electrode and a second electrode, a semiconductor device mounted on the wiring board and including a first terminal and a second terminal, an interposer provided between the wiring board and the semiconductor device, the interposer including a conductive pad and a sheet supporting the conductive pad, the conductive pad having a first surface on a side of the wiring board and a second surface on a side of the semiconductor device, a first solder connecting the first electrode positioned outside of an area in which the interposer is disposed with the first terminal positioned outside of the area, a second solder connecting the second electrode positioned inside of the area with the first surface of the conductive pad, and a third solder connecting the second terminal positioned inside of the area with the second surface of the conductive pad.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro Yoneda
  • Patent number: 8964407
    Abstract: A substrate with built-in electronic component includes: a core layer that includes a core material and a cavity formed in the core material and containing an insulating material; an insulating layer that includes a ground wiring and a signal wiring and is formed on the core layer; and a plurality of electronic components that each include a first terminal and a second terminal and are stored in the cavity, the plurality of electronic components each having one end portion and the other end portion, the first terminal being formed at the one end portion and connected to the ground wiring, the second terminal being formed at the other end portion and connected to the signal wiring, the plurality of electronic components having at least one of arrangements in which the first terminals face each other and in which the second terminals face each other.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiyo Yuden Co., Ltd
    Inventors: Tatsuro Sawatari, Yuichi Sugiyama
  • Patent number: 8959759
    Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Gibbons, Tracy V. Reynolds, David J. Corisis
  • Patent number: 8958212
    Abstract: An electronic device includes a circuit board, a connector and an electronic module. The connector includes an insulating body and a first terminal set. The insulating body includes a concave. The first terminal set is fastened on the insulating body and is electrically connected to the circuit board. The electronic module is detachably disposed in the concave and includes a second terminal set. The second terminal set contacts the first terminal set to be electrically connected to the circuit board.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: February 17, 2015
    Assignee: ASUSTeK Computer Inc.
    Inventors: Pai-Ching Huang, Tsung-Fu Hung, Li-Chien Wu
  • Patent number: 8953334
    Abstract: An apparatus for performing communication control includes a control module implemented with at least one integrated circuit (IC) whose package includes a plurality of sets of terminals, each set of the plurality of sets of terminals corresponding to one of a plurality of sub-modules of the control module, and within the sets of terminals, a set of terminals corresponding to a specific sub-module of the sub-modules include a power-input terminal arranged to input power from outside the control module. For example, on a printed circuit board (PCB) of the apparatus, arrangement of some modules is similar to that of some contact pads associated to the sets of terminals. In another example, the control module includes a power distribution system including at least one power distribution wire. In another example, a PCB within the apparatus includes at least one signal transmission wire and at least one set of co-plane ground wires.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: February 10, 2015
    Assignee: Mediatek Inc.
    Inventors: Yu-Te Lin, Hsiao-Tung Lin
  • Patent number: 8953330
    Abstract: A security protection device includes a cover circuit board comprising at least one inner wiring layer and a base circuit board comprising at least one inner wiring layer. The device further includes a security frame between the base circuit board and the cover circuit board, at least one electrically conductive wire being wound and included within the security frame to form at least one winding protection layer around sides of the security frame. The cover circuit board, the security frame, and the base circuit board form an enclosure enclosing a security zone, and the at least one inner wiring layer within the cover circuit board, the at least one inner wiring layer within the base circuit board, and the at least one electrically conductive wire within the security frame are connectable to a security mechanism configured to detect an intrusion into the security zone.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: February 10, 2015
    Assignee: PAX Computer Technology Co., Ltd.
    Inventors: Shuxian Shi, Hongtao Sun
  • Publication number: 20150036304
    Abstract: An electronic device includes: a wiring substrate; a plurality of device chips that are flip-chip mounted on an upper surface of the wiring substrate through bumps, have gaps which expose the bumps between the device chips and the upper surface of the wiring substrate, and include at least one device chip that has a substrate having a thermal expansion coefficient more than a thermal expansion coefficient of the wiring substrate; a junction substrate that is joined to the plurality of device chips, and has a thermal expansion coefficient equal to or less than the thermal expansion coefficient of the substrate included in the at least one device chip; and a sealer that covers the junction substrate, and seals the plurality of device chips.
    Type: Application
    Filed: July 8, 2014
    Publication date: February 5, 2015
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Motoi YAMAUCHI, Osamu KAWACHI
  • Publication number: 20150036302
    Abstract: The present invention provides a micropackaged device comprising: a substrate for securing a device; a corrosion barrier affixed to said substrate; optionally at least one feedthrough disposed in said substrate to permit at least one input and or at least one output line into said micropackaged device; and an encapsulation material layer configured to encapsulate the micropackaged device.
    Type: Application
    Filed: December 27, 2013
    Publication date: February 5, 2015
    Applicant: California Institute of Technology
    Inventors: Yu-Chong Tai, Han-Chieh Chang
  • Patent number: 8946892
    Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghoon Kim, Jihyun Lee
  • Patent number: 8947884
    Abstract: A device includes a printed circuit assembly (PCA) including a printed circuit board and at least one electronic component integrated with the printed circuit board, and a support to which the PCA is securable. At least one of the PCA and the support includes engaging structure elements, and some engaging structure elements are configured to secure the PCA to the support while other engaging structure elements are configured to secure the support to a securing structure within a housing of an electronic device.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: February 3, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Matthew Don Grimm, Edward John Kliewer, Kwok Keung Lee, Sam David Blackwell
  • Patent number: 8947886
    Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Manfred Mengel, Khalil Hosseini, Klaus Schmidt, Franz-Peter Kalz
  • Patent number: 8947887
    Abstract: A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert Bauer, Thorsten Hauck
  • Patent number: 8946904
    Abstract: A substrate comprising a plurality of layers, a first side and a second side; and a via extending through the substrate from the first side to the second side. The via comprises:a first substrate via extending through a first layer of the plurality of layers, the first substrate via having a first cross-sectional area; a first capture pad disposed under the first substrate via, wherein the first capture pad physically contacts the first substrate via; a second substrate via extending through a second layer of the plurality of layers, the second substrate via physically contacting the first capture pad, the second substrate via having a second cross-sectional area that is greater than the first cross-sectional area; and a second thermal and electrical contact pad disposed under the second dielectric layer, wherein the second contact pad physically contacts the second substrate via.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: February 3, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Tarak A. Railkar, Ashish Alawani, Ray Parkhurst
  • Patent number: 8942006
    Abstract: A printed circuit board (PCB) stackup includes conductive layers and insulating layers interleaved among the conductive layers. The conductive layers include one or more power layers, one or more ground layers, one or more high-frequency layers, and one or more low-frequency layers. One or more first signals having one or more first frequencies greater than a first threshold are communicated over the high-frequency layers. One or more second signals having one or more second frequencies less than a second threshold are communicated over the low-frequency layers. Each second frequency is less than each first frequency. The insulating layers include one or more core layers and one or more prepreg layers arranged in alternating fashion. Each insulating layer adjacent to any high-frequency layer has a first material type. Each insulating layer not adjacent to any high-frequency layer has a second material type different than the first material type.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: January 27, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventor: Anthony E. Baker
  • Patent number: 8941247
    Abstract: In a packaging structure for a microelectromechanical-system (MEMS) resonator system, a resonator-control chip is mounted on a lead frame having a plurality of electrical leads, including electrically coupling a first contact on a first surface of the resonator-control chip to a mounting surface of a first electrical lead of the plurality of electrical leads through a first electrically conductive bump. A MEMS resonator chip is mounted to the first surface of the resonator-control chip, including electrically coupling a contact on a first surface of the MEMS resonator chip to a second contact on the first surface of the resonator-control chip through a second electrically conductive bump. The MEMS resonator chip, resonator-control chip and mounting surface of the first electrical lead are enclosed within a package enclosure that exposes a contact surface of the first electrical lead at an external surface of the packaging structure.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: January 27, 2015
    Assignee: SiTime Corporation
    Inventors: Pavan Gupta, Aaron Partridge, Markus Lutz
  • Publication number: 20150022989
    Abstract: A chip-on-glass device comprises a chip-on-glass substrate, a metal layer, and a plurality of chip-on-glass connection bumps. The metal layer comprises a plurality of passive jumper routing traces. The plurality of chip-on-glass connection humps is coupled with passive jumper routing traces of the plurality of passive jumper routing traces.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: Synaptics Incorporated
    Inventors: Jim DUNPHY, Joseph Kurth REYNOLDS
  • Patent number: 8937255
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 20, 2015
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Patent number: 8937392
    Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: January 20, 2015
    Assignee: PS4Luxco S.a.r.l.
    Inventors: Yukitoshi Hirose, Yushi Inoue, Shiro Harashima, Takuya Moriya, Chihoko Yokobe
  • Patent number: 8934161
    Abstract: A method of manufacturing an optical scanning apparatus which includes: a light source having a plurality of luminous points; a coupling lens converting a plurality of beams from the light source into luminous flux; a deflector deflecting the luminous flux in a main scanning direction; a scanning lens focusing the luminous flux from the deflector onto a scanned surface so as to form an image; and a frame supporting at least the light source and the coupling lens, the method includes: fixing a coupling lens to a frame; adjusting a position of the light source, relative to the coupling lens fixed to the frame, while the light source emits the light; adjusting a pitch between the plurality of beams the optical axis while the light source emits the light; and fixing the light source to the frame at the adjusted position and the adjusted pitch.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: January 13, 2015
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Shinya Kusuda
  • Patent number: 8934259
    Abstract: A method for fabricating a substrate having transferable chiplets includes forming a photo-sensitive adhesive layer on a process side of a source substrate including active components or on a patterned side of a transparent intermediate substrate. The intermediate substrate is brought into contact with the source substrate to adhere the active components on the process side to the patterned side of the intermediate substrate via the photo-sensitive adhesive layer therebetween. Portions of the source substrate opposite the process side thereof are removed to singulate the active components. Portions of the photo-sensitive adhesive layer are selectively exposed to electromagnetic radiation through the intermediate substrate to alter an adhesive strength thereof. Portions of the photo-sensitive adhesive layer having a weaker adhesive strength are selectively removed to define breakable tethers comprising portions of the adhesive layer having a stronger adhesive strength.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: January 13, 2015
    Assignee: Semprius, Inc.
    Inventors: Christopher Bower, Joseph Carr
  • Patent number: 8933344
    Abstract: The present invention provides a display substrate for reducing resistance deviation occurring in a fan out unit, and a display apparatus including the display substrate. According to the present invention, resistance units are disposed in lines having a relatively short length in an area where lengths of adjacent lines increase or decrease non-linearly, and the adjacent lines have substantially equal resistance or have linear resistance variation.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 13, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Mu-Kyung Jeon
  • Publication number: 20150009643
    Abstract: A device includes a substrate, a first antenna connection, and a first retention mechanism. The substrate has atop surface and a bottom surface. The first antenna connection is mounted directly to the top surface of the substrate, and is configured to connect with a first antenna. The first retention mechanism is connected at a first location of the bottom surface of the substrate to provide support for the substrate at the first antenna connection when the first antenna connection is connected to the first antenna. The first location of the first retention mechanism is selected to be directly below the first antenna connection.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventors: Andrew T. Sultenfuss, Thomas G. Noonan
  • Patent number: 8929062
    Abstract: A wireless terminal device includes: a conduction and connection module, and a first Printed Circuit Board, PCB, connected to the conduction and connection module, and the wireless terminal device further includes a first conductor, where one of the conduction and connection module and the first PCB is connected to one end of the first conductor through a first capacitance coupling module, and the other one of the conduction and connection module and the first PCB is connected to the other end of the first conductor. Through the foregoing processing, capacitance coupling and grounding between the conduction and connection module and the PCB can be implemented through the first capacitance coupling module.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Huawei Device Co., Ltd.
    Inventors: Yanping Xie, Qing Liu, Ping Lei, Yao Lan, Shuhui Sun
  • Patent number: 8929081
    Abstract: An electronic system includes a printed circuit board (PCB), and a heat dissipating element. The PCB includes one or more first electronic components mounted on a first side of the PCB, and one or more second electronic components mounted on a second side of the PCB. The first electronic components have a power consumption that is greater than a threshold and have a height over the first side of the PCB that is higher than any other electronic components mounted on the first side of the PCB. At least one of the second electronic components has a height over the second side of the PCB that is higher than the height of the first electronic components. The heat dissipating element is adjacent to the first electronic components so as to provide a thermal coupling for dissipating heat generated by the first electronic components.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: January 6, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Daniel Elkaslassy, Daniel Kalmanoviz
  • Patent number: 8929091
    Abstract: A method of manufacturing a printed circuit board (PCB) having an embedded bare chip includes attaching a tape to one side of an insulated substrate having a penetration hole formed therein, and attaching the bare chip onto the tape inside the penetration hole such that electrode pads of the bare chip face the tape; filling up the penetration hole with a filler, and removing the tape; laminating a metal layer onto a surface of the filler and the insulated substrate from which the tape is removed; and forming electrode bumps by removing portions of the metal layer. The forming of electrode bumps further includes simultaneously removing portions of the metal layer and forming an circuit pattern on one side of the insulated substrate. The circuit pattern is formed directly on the upper side of the insulated substrate and the electrode bumps are formed on the surface of the electrode pads.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 6, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyung-Jin Han, Hyung-Tae Kim, Moon-Il Kim, Jae-Kul Lee, Doo-Hwan Lee
  • Patent number: 8929087
    Abstract: An electromagnetic shield for a storage device comprising a printed circuit board (PCBA) defining a plated through hole defining a generally cylindrical plated surface. The electromagnetic shield may comprise a top surface and sides oriented generally perpendicular to the top surface. One or more of the sides comprise a press-fit connector configured for removable insertion in the plated through hole. The press-fit connector may comprise at least one resilient member defining a longitudinal axis and configured to resiliently bow out in a direction generally perpendicular to the longitudinal axis during insertion and press against the plated surface of the through hole to displace plating material formed thereon to form a gas-tight seal between the at least one resilient member and the plated surface.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 6, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventor: Bruce A. Cariker
  • Patent number: 8927875
    Abstract: A wiring board includes an interlayer insulation layer, conductive patterns formed on the interlayer insulation layer, and a solder-resist layer formed on the interlayer insulation layer and having an opening partially exposing the conductive patterns. The solder-resist layer has an edge portion bordering the opening and intersecting the conductive patterns, and the edge portion of the solder-resist layer has a concavo-convex shape having convex portions and concave portions such that the convex portions and the concave portions are alternately intersecting the conductive patterns.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 6, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Toru Furuta, Fumitaka Takagi
  • Patent number: 8929089
    Abstract: An electronic circuit module component includes an electronic component, a substrate, a first resin, a second resin, a metal layer, and an opening. The electronic component is mounted on the substrate. The first resin has pores and is in contact with at least a part of the electronic component. The second resin covers a surface of the first resin and has porosity which is lower than that of the first resin. The metal layer covers the first resin and the second resin and is electrically connected to a ground of the substrate. The opening is provided in the metal layer and allows a part of the first resin to be exposed to an outside at least of the metal layer.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 6, 2015
    Assignee: TDK Corporation
    Inventors: Shigeru Asami, Seiichi Tajima, Hiroki Hara, Shuichi Takizawa, Masumi Kameda, Kenichi Kawabata
  • Patent number: 8927334
    Abstract: Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Nathalie Normand, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 8922306
    Abstract: A system can include a first radio frequency (RF) port, a second RF port electrically coupled with the first RF port, a direct current (DC) port, and a bias tee incorporated into a substrate. The bias tee can include multiple capacitors that are each integrated as a catch pad with a layer of the substrate. The bias tee can also include an inductor at least partially integrated with a layer of the substrate.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Tektronix, Inc.
    Inventors: Charles F. Clark, Jr., James D. Pileggi
  • Patent number: 8921707
    Abstract: A suspension substrate according to the present invention includes an insulating layer and a metallic support layer provided on the actuator element's side of the insulating layer. On the other side of the insulating layer, a wiring layer is provided. This wiring layer includes a plurality of wirings and a wiring connection section that can be electrically connected with the actuator element via a conductive adhesive. The outer periphery of the metallic support layer in a connection structure region is positioned outside relative to the outer periphery of the insulating layer and the outer periphery of the wiring connection section of the wiring layer.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: December 30, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Masao Ohnuki
  • Patent number: 8923009
    Abstract: In a first conductive layer and a third conductive layer that are respectively closest to a core layer having a storage portion that penetrates therethrough, four first penetrating holes and four first penetrating holes are formed so as to overlap part of an opening edge of the storage portion that is projected onto the first conductive layer and the third conductive layer, respectively.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Tatsuro Sawatari, Yuichi Sugiyama, Hiroshi Nakamura, Masaki Naganuma, Tetsuo Saji
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Patent number: 8923006
    Abstract: An assembly includes an LED with two conductive leads, two conductive wires in which an insulator surrounds a conductor, and a housing. The two conductive wires are inserted into and held by a wire cavity of the housing. Each of the two conductive leads is inserted into a different LED lead hole of the housing. Electrical contact is made by each of the two conductive leads with the conductor of one of the two conductive wires and the LED is held by the housing. The conductive leads can have a sharp point that penetrates the insulator and the conductor when the LED is inserted into the housing. The LED can be seated in a LED cavity of the housing while insertion of the LED into the LED cavity creates an interference fit in which conductive portions of the wires opposite the exposed conductors are compressed against the housing.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: December 30, 2014
    Inventor: Carmen Rapisarda
  • Patent number: 8923005
    Abstract: An electrical component and a method for the manufacture thereof, comprising a connection arrangement between an active surface of an electrical component and a carrier, wherein electrical connecting elements are disposed in a connection zone on the active surface and/or on the carrier, and at least one spacer element is provided, which is disposed on the active surface and/or on the carrier. The at least one spacer element has a smaller height than the connecting elements before the connecting elements are reflowed to produce the electrically conductive connection, and is preferably disposed in an edge region of the connection zone.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: December 30, 2014
    Assignee: Micro Systems Engineering GmbH
    Inventors: Rainer Dohle, Florian Schuessler, Rolf Diehm, Oliver Kessling, Thomas Oppert
  • Patent number: 8923004
    Abstract: Several embodiments of stacked-die microelectronic packages with small footprints and associated methods of manufacturing are disclosed herein. In one embodiment, the package includes a substrate, a first die carried by the substrate, and a second die between the first die and the substrate. The first die has a first footprint, and the second die has a second footprint that is smaller than the first footprint of the first die. The package further includes an adhesive having a first portion adjacent to a second portion. The first portion is between the first die and the second die, and the second portion being between the first die and the substrate.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Peng Wang Low, Leng Cher Kuah, Hong Wan Ng, Seng Kim Ye, Chye Lin Toh
  • Publication number: 20140376200
    Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Charles G. Woychik, Michael Newman, Terrence Caskey
  • Patent number: 8913379
    Abstract: A telecommunications chassis includes an array of mezzanine card interfaces and a carrier module coupled to the mezzanine card interfaces to control and manage mezzanine cards connected to the mezzanine card interfaces.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Edoardo Campini, Steven Denies, Mark Summers, Lawson Guthrie