Addressing Patents (Class 365/230.01)
  • Patent number: 7839712
    Abstract: A semiconductor memory arrangement includes a substrate, a first control device disposed on the substrate and adapted to receive command and address signals, a second control device, and a plurality of memory units. The second control device is adapted to receive the command and address signals from the first control device and to transmit the command and address signals to the memory units of the plurality of memory units.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: November 23, 2010
    Assignee: Qimonda AG
    Inventor: Srdjan Djordjevic
  • Patent number: 7835207
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: November 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Patent number: 7830740
    Abstract: A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Susumu Takano
  • Patent number: 7830700
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: November 9, 2010
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li
  • Patent number: 7830730
    Abstract: A memory module fast in random accesses, large in capacity, and low in fabricating cost. And the memory module can assure high security. The memory module consists of a flash memory, a dynamic random access memory, and a control circuit. The control circuit enables data transfer between the flash memory and the dynamic random access memory only with a read operation for a specific address in the memory module. When reading data from the memory module, the control circuit refreshes the dynamic random access memory. Thus the present invention can realize a large capacity and low cost memory module capable of reading data fast reading and assuring high security.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: November 9, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Seiji Miura
  • Patent number: 7830742
    Abstract: A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number of times or more.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: November 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-Joo Han
  • Patent number: 7826302
    Abstract: A semiconductor memory device including an array of memory cells arranged in a plurality of rows and in a plurality of columns. The memory device further includes a plurality of word lines each associated with a respective row of the array and identified by a respective row address, and a row decoder configured to receive a current row address and select a word line according to said current row address. The row decoder includes a plurality of row selection units each associated with a respective word line and configured to receive the current row address; each row selection unit is configured to be enabled for biasing the respective word line to a selection voltage if the current row address identifies said word line. Each row selection unit includes a corresponding enabling device for enabling the row selection unit after a predetermined time from the reception of the current row address.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: November 2, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ruili Zhang
  • Patent number: 7826299
    Abstract: A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Artur Wroblewski
  • Publication number: 20100271891
    Abstract: Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters.
    Type: Application
    Filed: April 28, 2009
    Publication date: October 28, 2010
    Inventors: Richard Bruce Dell, Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
  • Patent number: 7821812
    Abstract: A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured to decode a part of most significant bits (MSB) of the column address to locally enable a part of one page area corresponding to the row address; and a column decoder configured to decode the column address.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: October 26, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong-Ki Kim
  • Patent number: 7821226
    Abstract: A method for placing addresses in the memory cells of a rechargeable energy storage device for use in a motor vehicle, each of which memory cells includes at least one sensor device and an individualizing device for storing an address. In order to optimize the placing of addresses in the memory cells of a rechargeable storage device, the functionality of the memory cells is checked using the sensor device in the vehicle, an individual address is assigned to each operable memory cell, and the individual address is used to individualize the sensor values made available from the sensor device.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 26, 2010
    Assignee: Bayerische Motoren Werke Aktiengesellschaft
    Inventor: Joachim Froeschl
  • Patent number: 7813215
    Abstract: The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency control multiplexer selects the output enable signal corresponding to column address strobe latency among the plurality of output enable signals, on the basis of the signal obtained by delaying the input signal by the phase difference between the clock and the delay locked loop clock, and outputs the selected signal as the data output control signal.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: October 12, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Uk Lee
  • Publication number: 20100246278
    Abstract: A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located closer to an input and output of said memory than it is to at least one array located further from an input and output of said memory.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: ARM Limited
    Inventor: Christophe Denis Lucien Frey
  • Publication number: 20100232202
    Abstract: A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 16, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Olga R. Lu, Lawrence F. Childs, Thomas W. Liston
  • Patent number: 7796461
    Abstract: A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section configured to make a drive-targeted memory chip selected or non-selected, based on an input signal. They also include an address signal input section configured to provide a signal to address the memory chip, based on an input signal. They further include a select address signal input section configured to make the plurality of memory chips selected or non-selected, based on an input signal, and configured divertible to the address signal input section.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: September 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Kawaguchi, Yutaka Shirai
  • Patent number: 7791961
    Abstract: A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: September 7, 2010
    Assignee: Spansion LLC
    Inventors: Kazuhiro Kitazaki, Kazuhide Kurosaki
  • Publication number: 20100220542
    Abstract: A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.
    Type: Application
    Filed: March 2, 2009
    Publication date: September 2, 2010
    Inventors: Gregory Kengho Chen, Dennis Michael Sylvester, David Theodore Blaauw
  • Patent number: 7788447
    Abstract: An electronic flash memory external storage method and device for data processing system, includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores date by flash memory and access control circuit 2 with the cooperation of the firmware, driver and operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in statistic state and is driven by software. It is plug-and-play and adapted to data processing system.
    Type: Grant
    Filed: July 24, 2004
    Date of Patent: August 31, 2010
    Assignee: Netac Technology Co., Ltd.
    Inventors: Guoshun Deng, Xiaohua Cheng
  • Publication number: 20100214827
    Abstract: A module comprises a bus invert encoder (24) for determining whether a set of data bits should be inverted prior to transmission over a communication bus. The bus invert encoder (24) produces a bus invert signal BI which controls a selective inversion means (28), for example a multiplexer. A partial fault detection encoder (32) determines one or more temporary check bits from the set of data bits, substantially in parallel with the bus invert encoder (24). Thus, the one or more temporary check bits are determined based on the assumption that the set of data bits are to be transmitted without inversion from the selective inversion means (28). A logic unit (34) is provided for correcting the one or more temporary check bits, if necessary, based on the bus invert signal produced by the bus invert encoder (24).
    Type: Application
    Filed: August 19, 2005
    Publication date: August 26, 2010
    Applicant: NXP B.V.
    Inventors: Martijn Henri Richard Lankhorst, Franciscus P. Widdershoven
  • Patent number: 7773447
    Abstract: A memory circuit of the invention comprises N look-up tables for implementing a desired logic function of L inputs/M outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting one of the N look-up tables by decoding a look-up table select signal and for selecting M memory cells to be accessed included in the selected look-up table by decoding an L-bit logic input signal of the logic function; and a select connect circuit for selectively connecting the input/output paths of the M memory cells to be accessed with an input/output bus for transmitting an M-bit logic output signal of the logic function in response to a decoded result of the decode circuit.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 10, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiko Kajigaya
  • Publication number: 20100195399
    Abstract: Methods for programming memory devices, a memory device, and memory systems are provided. According to at least one such method, bit lines a memory segment are read at substantially the same time by coupling a selected memory segment, and at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines. Other methods, devices, and systems are also provided.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 5, 2010
    Inventor: Tomoharu Tanaka
  • Patent number: 7764545
    Abstract: An address replacing circuit includes a sub-bank region selecting unit that allows a first sub-bank region or a second sub-bank region to be selectively activated, in response to a row address and first and second bits of a column address in accordance with operation modes a first column region activating unit that generates a first column region activating address and a second column region activating address from the first bit of the column address, a second column region activating unit that generates a third column region activating address and a fourth column region activating address from the second bit of the column address, and a column region selecting unit that allows at least one of first to fourth column regions of the first sub-bank region and first to fourth column regions of the second sub-bank region to be selectively activated, in response to the first to fourth column region activating addresses.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: July 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keun-Kook Kim
  • Patent number: 7760571
    Abstract: An image memory is composed of a memory cell array, first and second area selecting circuits, and a write circuit. The memory cell array includes memory elements arrayed in rows and columns, each of the memory elements being adapted to store pixel data. The first area selecting circuit is adapted to select a plurality of row addresses at the same time, and the second area selecting circuit is adapted to select a plurality of column addresses at the same time. The write circuit is adapted to write same pixel data into selected memory elements out of the memory elements, the selected memory elements being associated with the selected row addresses and column addresses.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: July 20, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hirobumi Furihata, Junyou Shioda
  • Patent number: 7760580
    Abstract: A flash memory device includes a plurality of block selection circuits and a plurality of memory blocks. The plurality of block selection circuits generate a block select signal in response to a plurality of decoded block address signals and a block control signal. The plurality of memory blocks are connected to global lines in response to the block select signal, and include a plurality of memory cell arrays performing an erase operation in response to a well bias. Each of the block selection circuits generates the block select signal in response to the block control signal regardless of the plurality of decoded block address signals, or selects the block select signal to select a corresponding memory block in response to the plurality of decoded block address signals.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: July 20, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Hyun Wang
  • Publication number: 20100177587
    Abstract: The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address.
    Type: Application
    Filed: April 2, 2009
    Publication date: July 15, 2010
    Applicant: NANYA TECHNOLOGY CORP.
    Inventor: Yu-Wen Huang
  • Publication number: 20100177547
    Abstract: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 15, 2010
    Inventor: Biao Shen
  • Patent number: 7752249
    Abstract: A memory-based Fast Fourier Transform device is provided, which adopts single-port random access memory (RAM), rather than dual-port RAM, as a storage, and the circuit area of the FFT device is therefore reduced. In order to enhance the access efficiency of the memory and the use efficiency of a processor, the transformer adopts a modified in-place conflict-free addressing to achieve similar performance of a traditional Fast Fourier Transform device.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: July 6, 2010
    Assignee: Industrial Technology Research Institute
    Inventor: Chi-Li Yu
  • Publication number: 20100165780
    Abstract: Methods and apparatus are disclosed for reducing write-to-read turnaround times using shadow writes in memory controllers and in DRAM. Embodiments of controllers including shadow write control logic may, in response to receiving a write request, issue an external write column address strobe (CAS) to DRAM to latch a valid write CAS address, and assert a set of write data values to be stored in a set of DRAM locations corresponding to the write CAS address. After asserting the write CAS and prior to asserting the complete set of write data values, such memory controllers may, in response to receiving a read request, issue an external read CAS to DRAM to indicate a valid read CAS address. A set of read data values from a second set of DRAM locations corresponding to the read CAS address, are received with reduced turnaround time after asserting the complete set of write data values.
    Type: Application
    Filed: December 27, 2008
    Publication date: July 1, 2010
    Inventors: KULJIT S. BAINS, Randy B. Osborne
  • Publication number: 20100165779
    Abstract: A semiconductor memory device including an array of memory cells arranged in a plurality of rows and in a plurality of columns. The memory device further includes a plurality of word lines each associated with a respective row of the array and identified by a respective row address, and a row decoder configured to receive a current row address and select a word line according to said current row address. The row decoder includes a plurality of row selection units each associated with a respective word line and configured to receive the current row address; each row selection unit is configured to be enabled for biasing the respective word line to a selection voltage if the current row address identifies said word line. Each row selection unit includes a corresponding enabling device for enabling the row selection unit after a predetermined time from the reception of the current row address.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Ruili Zhang
  • Publication number: 20100165765
    Abstract: A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory cells. The memory further includes a protection register comprising storage elements configured to store configuration data of the memory device. The storage elements of the protection register are redundant memory cells not being used to replace defective memory cells.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Applicant: STMicroelectronics S.r.I.
    Inventors: Chin-Tin Tina Yu, Rich E. Fackenthal, Duane Mills
  • Publication number: 20100165713
    Abstract: A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Inventors: Claudio Resta, Ferdinando Bedeschui
  • Publication number: 20100157693
    Abstract: A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit operative to change in the storage capacity of the memory cell array and change in the address space required for access to the memory cell based on a control signal.
    Type: Application
    Filed: November 6, 2009
    Publication date: June 24, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki Iwai, Takayuki Miyazaki, Mariko Iizuka
  • Publication number: 20100153676
    Abstract: A semiconductor device disclosed herein is provided with a plurality of function reconfigurable cells, each comprising a memory circuit and a control circuit, for realizing variable logical functions. A function reconfigurable cell autonomously controls a read address in the memory circuit storing true value data by itself. For example, the control circuit takes feedback input of information that has been read from the data field and control field of the memory circuit synchronously and uses feedback input information from the data field or another information as address information for next synchronous reading of the data field and control field, based on feedback input information from the control field. Because each function reconfigurable cell is capable of autonomous control of reading of the memory circuit storing true value data by itself, it is possible to handle the memory circuit for realizing variable logical functions as a circuit equivalent to a logic circuit.
    Type: Application
    Filed: May 21, 2008
    Publication date: June 17, 2010
    Inventor: Yoshifumi Kawamura
  • Publication number: 20100142250
    Abstract: A pair of access control circuits having bit line pairs wired corresponds to a same data terminal and is assigned different addresses. During a test mode, a data swap circuit prohibits swapping of connections between a pair of data terminals and a pair of data lines when one of the access control circuits is used, and swaps the connections between a pair of data terminals and a pair of data lines when the other one of the access control circuits is used. Accordingly, it is possible to give a data signal at the same logic level to bit lines with different logics from each other. Stress can be given between a contact arranged between a pair of the access control circuits and bit lines adjacent to both sides of the contact. Consequently, designing of a test pattern can be simplified, and test efficiency can be improved.
    Type: Application
    Filed: January 8, 2010
    Publication date: June 10, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroyuki KOBAYASHI, Daisuke KITAYAMA
  • Patent number: 7733738
    Abstract: Provided are a semiconductor memory device and a data write and read method thereof. The semiconductor memory device includes a write data controller, an address controller, and a read data controller. The write data controller writes data received with an address to a first memory cell corresponding to the address and simultaneously stores the data in a data register. The address controller decodes and stores the address in an address register. The read data controller outputs data from a second memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputs the data stored in the data register if the received address is equal to the address stored in the address register.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yoon-Hwan Yoon
  • Patent number: 7729200
    Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: June 1, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Patent number: 7729180
    Abstract: A semiconductor memory device operates using a first power supply and a second power supply. The device includes a static memory cell which receives the first power supply, a word line which is connected to the memory cell, and a decoder which controls selection/deselection of the word line on the basis of an address signal having a voltage of the second power supply. The decoder includes a level shifter which changes a voltage of the word line to a voltage of the first power supply, and a switching circuit which receives the first power supply and applies a voltage lower than the first power supply to the level shifter in selecting the word line.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Hirabayashi
  • Publication number: 20100128550
    Abstract: Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 27, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Simon J. Lovett
  • Publication number: 20100128541
    Abstract: An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Inventors: Andrew C. Russell, Shayan Zhang
  • Publication number: 20100110748
    Abstract: A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice.
    Type: Application
    Filed: April 17, 2008
    Publication date: May 6, 2010
    Inventor: Scott C. Best
  • Publication number: 20100110805
    Abstract: A semiconductor memory device includes a plurality of address pads, a plurality of data pads, a mode entry controlling unit configured to control the entry to a data masking mode in response to a write command signal and signals inputted through predetermined pads among the plurality of address pads, a signal classifying unit configured to classify signals inputted sequentially and in parallel through the plurality of address pads into column address signals and data masking signals in response to an output signal of the mode entry controlling unit and a write latency signal, and a pad masking signal generating unit configured to generate pad masking signals to control the masking of data inputted through the plurality of data pads, where the pad masking signals are generated by converting the data masking signals in response to the output signal of the mode entry controlling unit.
    Type: Application
    Filed: December 29, 2008
    Publication date: May 6, 2010
    Inventor: Sun-Suk YANG
  • Publication number: 20100110819
    Abstract: A memory is provided. The memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pass gate voltage provided to the gates of pass line transistor in a sector decoders and/or an array decoder for the memory cells being accessed. The boost converter circuitry includes at least two boost converters, and a switch. When one of the memory arrays is accessed, the switch either couples the boost converters together or does not couple the boost converters together based on the distance of the memory array being accessed from the boost converters.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Applicant: Spansion LLC
    Inventors: Chin-Ghee Chng, Teoh Boon-Weng
  • Publication number: 20100103747
    Abstract: A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 29, 2010
    Applicant: ARM LIMITED
    Inventors: Nicolaas Klarinus Johannes Van Winkelhoff, Christophe Denis Lucien Frey
  • Patent number: 7707384
    Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: April 27, 2010
    Assignees: The Massachusetts Institute of Technology University, The Board of Trustees of the Leland Stanford Junior University
    Inventors: William J. Dally, Scott W. Rixner
  • Publication number: 20100097853
    Abstract: A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect transistor (600) having a first conductivity type. A second junction field effect transistor (602) having a second conductivity type is coupled to the first junction field effect transistor. An access transistor (610) is coupled to the first and second junction field effect transistors.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Inventor: Robert N. Rountree
  • Patent number: 7701799
    Abstract: A semiconductor device may include a decoder for decoding a plurality of internal command signals and outputting a first Y-address enabling signal; a Y-address enabling signal generator for receiving the first Y-address enabling signal and outputting a second Y-address enabling signal having a predetermined enabled period; a multiplexer (MUX) for receiving the first Y-address enabling signal and the second Y-address enabling signal and selectively outputting any one thereof as a Y-address enabling signal; and a MUX controller for controlling the MUX such that the MUX selects any one of the first Y-address enabling signal or second Y-address enabling signal according to an operation mode of the semiconductor device.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: April 20, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Young You
  • Publication number: 20100091602
    Abstract: An address counting circuit includes a counter configured to sequentially count from an initial address in response to a clock signal in order to output counted addresses. The address counting circuit also includes a code conversion unit that is configured to output converted addresses such that only one address bit of the converted addresses with respect to the previous converted addresses are toggled to output the converted addresses. The converted addresses output form the code conversion unit do not overlap with one another.
    Type: Application
    Filed: December 29, 2008
    Publication date: April 15, 2010
    Inventors: Sang Hoon SHIN, Won Jun CHOI
  • Publication number: 20100091599
    Abstract: A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks, wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 15, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hyung Wook Moon, Jeong Woo Lee, Won Jun Choi
  • Patent number: 7697360
    Abstract: Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: April 13, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Chiaki Dono, Yasuji Koshikawa
  • Patent number: RE41379
    Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: June 15, 2010
    Assignee: Rising Silicon, Inc.
    Inventors: Tsugio Takahashi, Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura