Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: identifying a hardware failure of a failed component of a plurality of hardware components; determining a set of agent devices currently configured to utilize the failed component; reconfiguring an agent device to utilize a working component of the plurality of hardware components. Various exemplary embodiments additionally or alternatively relate to a method and related network node including one or more of the following: projecting a failure date for the hardware module; determining whether the projected failure date is acceptable based on a target replacement date for the hardware module; if the projected failure date is not acceptable: selecting a parameter adjustment for a hardware component, wherein the parameter adjustment is selected to move the projected failure date closer to the target replacement date, and applying the parameter adjustment to the hardware component.

Abstract: A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second data I/O block transmits the write internal signal to a second pad in response to a monitor enable signal. During a read operation, the first data I/O block supplies data from the first global I/O line to a first pad, and further generates a read internal signal. The second data I/O block transmits the read internal signal to the second pad in response to a monitor enable signal.

Abstract: A failure detection apparatus for a solid state driver tester is provided. The failure detection apparatus includes a host terminal for receiving a test condition for testing a storage from a user and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selects an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time.

Abstract: A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.

Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

Abstract: A semiconductor circuit comprises a digital circuit portion, which in turn comprises a combinatorial logic block. The semiconductor circuit comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion such as register addresses and/or memory addresses. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion through the scan chain involves writing bit values to inputs of the individually addressable scan control registers and reading bit values from at least one output of an individually addressable scan control register.

Abstract: An application server may provide an execution environment and a process execution engine that executes a process model within the execution environment. The process execution engine may include an operational component configured to perform an operation that is associated with the execution of the process model and based on a security policy, as well as a security provider configured to determine, based on the operation and on the security policy, at least one security service from among a plurality of security services executing within the process execution engine, and configured to provide the operational component with the at least one security service for use in securing the operation.

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract: Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.

Abstract: A radiation detector assembly (20) includes a detector array module (40) configured to convert radiation particles to electrical detection pulses, and an application specific integrated circuit (ASIC) (42) operatively connected with the detector array. The ASIC includes signal processing circuitry (60) configured to digitize an electrical detection pulse received from the detector array, and test circuitry (80) configured to inject a test electrical pulse into the signal processing circuitry. The test circuitry includes a current meter (84) configured to measure the test electrical pulse injected into the signal processing circuitry, and a charge pulse generator (82) configured to generate a test electrical pulse that is injected into the signal processing circuitry.

Abstract: The present patent document relates to a method and apparatus for optimizing access to control registers in an emulation chip. Control messages include in one half of the message a write-mask bits for the corresponding control bits in the other half of the word. A single message from the host workstation can be used to update several bits of the register using a single message, rather than reading, modifying, then writing back each bit individually. Only the bits desired to be updated are written, while the masked bits are not affected. Various configurations of the mask bits and control bits are possible, and block transfers can be used to update bits across a series of registers. The disclosed method and apparatus can reduce overhead and latency on communication channels to the host workstation by significantly reducing the number of individual transfer across the channel.

Abstract: An example of the present invention provides a method and system for automatically suppressing false alarms in an IT system, such as an IT application. The method includes consolidating abnormal metrics into a single anomaly. A size of the anomaly relative to the IT application is determined, as well as a distribution of the anomaly in the IT application. A false alarm is determined based on the size and the distribution of the anomaly.

Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Abstract: A test device and method using a separate control module for test are disclosed, where a main console is replaced with a control module of the test device, the control module may generate a control command after receiving the a command transmitted from the main console, and transmit the control command to at least one PLD corresponding thereto, the PLD may control the GIPO comprised thereby to test the unit under test according to the received control command, whereby reducing the test time and achieving in the effect where the main console may do the other work concurrently when engaging in the test for the unit under test.

Abstract: A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.

Abstract: A data processing device includes a memory, an arithmetic circuit that accesses the memory by outputting an access control signal CTRL that controls access to the memory, a first data storage unit that stores first data used when a self-diagnosis is performed, a read-modify-write circuit that generates second data by replacing a part of the first data stored in the first data storage unit with modify data outputted from the arithmetic circuit, and a determination unit that diagnoses a failure of the read-modify-write circuit by comparing the second data with an expected value.

Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Abstract: Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract: Roughly described, a method of controlling transportation of debug data on an integrated circuit chip. The chip has a shared hub and a number of peripheral circuits. Each peripheral circuit is connected to a respective debug unit, and between each debug unit and the shared hub there is an interface configured to transport data messages over each of a number of prioritized flows. In the method, still roughly described, control data for controlling the state of a debug unit is transported on a priority flow having a first priority, and debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit is transported on a flow having a second priority, the first priority being higher than the second priority.

Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.

Abstract: An interface node selects a logical block address that corresponds to a contiguous memory location located on a storage device that is accessible by multiple interface nodes. The interface node retrieves a logical block address status indicator from a shared memory area and determines, based upon the logical block status indicator, whether the logical block address is utilized by a different interface node. If the logical block address is not utilized by a different interface node, the interface node tests the corresponding contiguous memory location.

Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract: A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and a memory module slot including a plurality of second pins are disposed on the PCB. Each of the second pins is coupled to the corresponding first pin of the CPU socket via the corresponding trace. A CPU interposer board is inserted into the CPU socket, and a memory interposer board is inserted into the memory module slot. The traces form a test loop via the CPU interposer board and the memory interposer board. When an automatic test equipment (ATE) provides a test signal to the test loop via the test point, the ATE determines whether the test loop is normal according to a reflectometry result of the test signal.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: The generalized modular redundancy fault tolerance method for combinational circuits utilizes redundancy techniques to improve soft error reliability and is based on probability of occurrence for combinations at the outputs of circuits. The generalized modular redundancy method enhances the reliability of combinational circuits. Types of redundant modules, complexity of voters and single versus multiple outputs protection are explored.

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

Abstract: According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.

Abstract: A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.

Abstract: According to one general aspect, a method of testing an integrated circuit may include executing, on a system control processor of the integrated circuit, a Silicon Test Environment (STE). The STE may be configured to facilitate an interaction of a functional test program with a processor without aid of an operating system. The method may include executing, on a processor of the integrated circuit, one or more instances of the STE. The method may include establishing a plurality of functional test programs by instructing each of the one or more instances of the STE to each perform a respective functional test program targeting a respective hardware component of the integrated circuit. The method may include collecting data produced by the execution of the functional test programs.

Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.

Abstract: A collaborative language translation system, computer readable storage medium, and method is disclosed that allocates as between automated and manual language translation services, wherein a manual language translator creates a unique database including manual translator languages capability, accuracy skill level, scope of translation project desired, and translation turnaround time. Also a client creates a unique information set that includes original language, desired language, scope of translated material, client desired translation formats, client desired translation timing, and client desired translation accuracy. Also included in the system is an automated language translation database and instructions for allocating a flow of the unique information set as between the unique database and the automated language translation database based upon the client unique information set and instructions to perform the selected language translation for the client.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: Methods and apparatus relating to observing an internal link via an existing port for System On Chip (SOC) devices are described. In one embodiment, a logic within an SOC device may allow an external logic analyzer to observe communication between a first and second component of the SOC through an existing (e.g., shared and/or non-dedicated) interface. Other embodiments are also disclosed.

Abstract: In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.

Abstract: An example of the invention includes a process and apparatus combining test modalities that collates data, processes it into a standard format, evaluates trends and interrogates via an expert system can increase efficiency and yield greater confidence in testing of parts in a variety of supply chain segments. An exemplary process and test system can collect a variety of test data as pre-processed raw data from a plurality of modalities as an evaluation database. The evaluation database post-processes said raw data via data analysis output to an expert system and decision engine as exemplary rule sets. The decision engine generating a probability that a microelectronic device is unauthorized, does not meet specification(s), is defective or counterfeit.

Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Abstract: Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.

Abstract: A circuit having a component for signal recovery, such as an adaptive equalizer, may be tested in order to ensure that the component operates properly. Unfortunately, external test equipment may be expensive and prone to being damaged. According to an aspect of the disclosure, there is provided a circuit including BIST (Built-in Self-Test) circuitry for testing a component for signal recovery with a stress signal that simulates an imperfect signal received over a communication channel. The circuit also has a detector for determining whether the component is operating properly with the stress signal. Thus, no external test equipment is needed for testing the component. In some implementations, the BIST circuitry includes a low-pass filter for filtering a transmit signal into the stress signal. Thus, the amount of circuitry involved in generating the stress signal can be reduced.

Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.

Abstract: An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.

Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.

Abstract: Remote monitoring systems for remotely monitoring execution status of a PLC (Programmable Logic controller) program of a machine include a storage module, a parameter retrieval module and a monitoring module. The storage module stores ladder diagram information corresponding to a PLC source program, wherein the ladder diagram information includes PLC signal address relation information, a plurality of logic switches and a responsive collect command of each logic switch of a ladder diagram. The PLC signal address relation information indicates the relations of the logic switches on the ladder diagram. The parameter retrieval module respectively retrieves parameter data corresponding to the logic switches using the responsive collect commands.

Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event.