Abstract: A system on a chip (SoC) for smoke detection includes power regulator circuits coupled to respective pins and analog sensor amplifier circuits that are each coupled to a respective pin of the pins coupled to the power regulator circuits. A first analog sensor amplifier circuit of the analog sensor amplifier circuits has a photoelectric amplifier circuit, a first LED driver and a second LED driver. The SoC also has a digital core that includes a digital logic circuit, register bits, and an MCU communication circuit. The MCU communication circuit is coupled to a data pin, the register bits are coupled to control or modify operation of the power regulator circuits and the analog sensor amplifier circuits, and the register bits are operable to be written to by an MCU.

Abstract: Methods, systems, and devices for defect detection for a memory device are described. A segmented digital die defect detector may include multiple signal lines, each coupled with a test circuit, and a control circuit to form a path. At least part of the path may extend through an internal portion of the die. A test circuit may generate a digital feedback signal that indicates a condition of a respective signal line. The control circuit may generate a single output signal, indicative of the condition of the signal lines. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die defect detector may be reduced and a power consumption associated with the testing operation may be reduced.

Abstract: Various systems and methods for implementing secure system-on-chip (SoC) debugging are described herein. A method of providing secure system-on-a-chip (SoC) debugging, comprises: receiving, from a remote host at a debug companion circuit, a debug initiation request to initiate a debugging session with an SoC associated with the debug companion circuit; encrypting, at the debug companion circuit, a debug handshake command; transmitting the debug handshake command to the SoC from the debug companion circuit, wherein the SoC is configured to authenticate the debug companion circuit, and configure intellectual property (IP) blocks on the SoC to expose debug data to the debug companion circuit in response to authenticating the debug companion circuit; and managing a secure connection with the SoC to obtain debug data and report the debug data to the remote host.

Abstract: Described in detail herein are methods and systems dynamically generating maintenance data. The system includes a first computing system which can receive identification credentials associated with a user. The second computing system can receive the identification credentials associated with the user. The second computing system can authenticate the identification credentials associated with the user. The second computing system can determine whether the user is a first type or a second type in response to authenticating the identification credentials associated with the user. The second computing system can dynamically generate and display an editable form with empty fields, on the interactive display of the first computing system, in response to determining the user is of a first type. The second computing system can dynamically populate and display a read-only report on the interactive display of the first computing system, in response to determining the user is of a second type.

Abstract: An example test system includes a device interface board (DIB) having one or more signal transmission paths and an interface for connecting to one or more other components of the test system. Test circuitry is configured to inject test signals into the one or more signal transmission paths and to measure transmitted versions of the test signals at the interface to obtain measurement signals. One or more processing devices are configured to generate calibration factors based on differences between the injected test signals and the measurement signals, and to store the calibration factors in computer memory. The calibration factors are for correcting for effects on the test signals of the one or more signal transmission paths.

Abstract: A display apparatus includes: a plurality of pixel circuits at a display area, the display area having a non-quadrangular shape; a first signal line extending on the display area in a first direction, and electrically connected to a first pixel circuit from among the plurality of pixel circuits; a first voltage line extending on the display area in the first direction; a first load compensation capacitor adjacent to an end portion of the first signal line and an end portion of the first voltage line; a test circuit outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the first signal line, and an electrode of the first load compensation capacitor to each other.

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

Abstract: Disclosed herein are an apparatus and method for transmitting fuzzing data. The apparatus may include one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program may collect context information pertaining to a one-way fuzzing target device that uses a one-way protocol, may determine the execution state of the one-way fuzzing target device by analyzing the context information, and may transmit fuzzing data to the one-way fuzzing target device based on the result of determination of the execution state.

Abstract: Embodiments of the present disclosure relate to a method and device for facilitating a connectivity check between a terminal device and a media gateway. In example embodiments, the session controller receives, via a web gateway associated with said terminal device, a request for establishing a real-time communication call and an indication for indicating a capability of said terminal device for early reception of a connectivity parameter of said media gateway to be used in said connectivity check. The session controller obtains said connectivity parameter from said media gateway. Then, in response to said connectivity parameter being obtained, the session controller sends said connectivity parameter via said web gateway towards said terminal device within a time limit. In this way, said terminal device may initiate said connectivity check to said media gateway earlier, and thus a latency of call establishment may be reduced significantly.

Abstract: A waveform data acquisition module includes an A/D converter that converts an electrical signal relating to a DUT into a digital signal, and a first memory unit that stores waveform data configured as a digital signal sequence. A function test module includes a test unit and a second memory unit. A higher-level controller instructs the waveform data acquisition module to start data sampling, and holds the time point thereof. Furthermore, the higher-level controller instructs the function test module to start to execute a pattern program, and records the time point thereof. The first memory unit records the time point at which the data sampling is started. The higher-level controller records the time point at which the execution of the pattern program is started.

Abstract: An optic probe is used to measure signals from a device under test. The optic probe is positioned at a target probe location within a cell of the device under test, the cell including a target net to be measured and a plurality of non-target nets. A test pattern is applied to the cell with the optic probe a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: (i) simulating a combinational logic analysis (CLA) cross-talk waveform to model cross-talk from selected non-target nets by simulating an optical response of the cell to the test pattern with the target net masked; (ii) estimating a cross-talk weight; and (iii) determining a target net waveform by weighting the CLA cross-talk waveform according to the cross-talk weight and subtracting the weighted CLA cross-talk waveform from the LP waveform.

Abstract: A method is used to test a memory device including a package substrate, a controller die and a memory die. The package substrate includes an isolation pin, a test mode select pin, a test clock pin and a test data pin. The method includes setting the isolation pin to an isolation state to isolate the memory die from the controller die, and when the isolation pin is set to the isolation state, setting the memory die to receive control via the test mode select pin, the test clock pin and the test data pin.

Abstract: A method for operating a component of predetermined geometry ? that is cyclically loaded during operation, wherein a probability of failure P is determined for the component taking account of distributions of failure times, which are caused by deviations in material properties, the component is operated depending on the determined probability of failure P, wherein at least one maintenance time is set for the component, in particular depending on the determined probability of failure P.

Abstract: A prediction model creation apparatus includes a feature amount acquisition unit that acquires values of types of feature amounts that are calculated from operating state data indicating an operating state of a production facility that produces a product, for both a normal time at which the production facility produces the product normally and a defective time at which a defect occurs in the product that is produced, a feature amount selection unit that selects a feature amount effective in predicting the defect from among the acquired types of feature amounts, based on a predetermined algorithm that specifies a degree of association between the defect and the types of feature amounts, from the values of the types of feature amounts acquired at the normal time and the defective time, and a prediction model construction unit that constructs a prediction model for predicting occurrence of the defect, using the selected feature amount.

Abstract: The present disclosure discloses a method and device for pushing information to a target user. One example method includes identifying a plurality of users that meet a predetermined condition; selecting a target user from the identified users to be provided with information, where in the target user is selected based on a relationship strength and an influence of the identified users; and transmitting the information to the determined target user over a network, and relates to the field of information technologies.

Abstract: A modular multi-system gaming console can be configurable for use in conjunction with expansion consoles (also referred to as expansion modules, expansion units, and/or element modules herein) as a gaming console emulator and/or for use as an audio/video converter (e.g., an up-converter), data recorder, or streaming device. Further, the modular multi-system gaming console can evoke the original gaming experience of a game played on original hardware. A modular multi-system gaming console can provide a consistent platform for display, content management, statistical storage and analysis (e.g., high scores, fastest speed runs, etc.), and live streaming and other services (including core services described herein) across a multitude of gaming console platforms. A modular multi-system gaming console can also provide a more authentic game experience via active cartridge reading.

Abstract: A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

Abstract: In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.

Abstract: A system to collect and store in a special data structure arranged for rapid searching massive amounts of data. Performance metric data is one example. The performance metric data is recorded in time-series measurements, converted into Unicode, and arranged into a special data structure having one directory for every day which stores all the metric data collected that day. The data structure at the server where analysis is done has a subdirectory for every resource type. Each subdirectory contains text files of performance metric data values measured for attributes in a group of attributes to which said text file is dedicated. Each attribute has its own section and the performance metric data values are recorded in time series as Uinicode hex numbers as a comma delimited list. Analysis of the performance metric data is done using regular expressions.

Abstract: A computer system includes a circuit board, one or more electronic components and a board management controller (BMC). The electronic components are disposed on the circuit board. The BMC is disposed on the circuit board and electrically connected to the one or more electronic components. The BMC is configured to enable/initiate a boundary scan test for the one or more electronic component.

Abstract: One embodiment provides a system and method for automated design of a computational system. During operation, the system obtains a component library comprising a plurality of computational components, receives design requirements, and builds a plurality of universal component cells. A respective universal component cell is configurable, by a selection signal, to behave as one of the computational components. The system further constructs a candidate computational system using the universal component cells, constructs a miter based on the design requirements and the candidate computational system, and converts the miter into a quantified satisfiability (QS) formula. The system generates a set of inputs that are a subset of all possible inputs of the QS formula, solves the QS formula by performing partial input expansion on the generated set of inputs to obtain at least one design solution, and outputs the at least one design solution to facilitate construction of the computational system.

Abstract: A ring oscillator including a plurality of flip-flops is provided. The flip-flops are connected in a ring. The flip-flops are configured to start to oscillate according to a start signal to generate an output signal, and stop oscillating according to a stop signal to stop generating the output signal. When the stop signal changes from a first level to a second level, the output signal becomes floating. In addition, a time measuring circuit including the foregoing ring oscillator is also provided.

Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a host system comprising at least one processor, a management controller communicatively coupled to the at least one processor and configured to provide out-of-band management of the information handling system, a debugging circuit, and a logic device coupled to the host system and to the management controller. The logic device may be configured to determine that a trigger event has taken place, and in response to the trigger event, provide a serial data stream corresponding to the trigger event to the debugging circuit. The debugging circuit may be configured to provide access to the serial data stream to a debugging information handling system via a wireless interface.

Abstract: A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.

Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

Abstract: A semiconductor-product testing device that supplies a test pattern for testing a semiconductor product to the semiconductor product includes a pattern memory that stores a part of the test pattern. The pattern memory is rewritten during a time when the semiconductor product is tested by a part of the test pattern stored in the pattern memory included in the semiconductor-product testing device.

Abstract: A wafer burn-in test circuit may be provided. The wafer burn-in test circuit may include a timing correction unit configured to generate a plurality of timing-compensated input signals by synchronizing a plurality of pulse signals generated according to a plurality of input signals with an input signal among the plurality of input signals. The wafer burn-in test circuit may include a wafer burn-in signal decoding unit configured to generate a plurality of decoding signals by decoding the plurality of timing-compensated input signals and output the plurality of decoding signals as a plurality of wafer burn-in signals by latching the plurality of decoding signals.

Abstract: A method and a device for non-intrusively collecting function trace data of a software application running on a processor-core, comprising translating a source code of the software application which comprises traceable function source code into executable code. The steps to execute the executable code include allocating the executable code of the traceable function within at least one pre-defined code memory region, checking each function call or jump instruction for its target address, and if the target address is located within the pre-defined code memory region, logging the execution of the traceable function.

Abstract: Embodiments are directed to apparatuses and methods for providing a logic built-in self-test (LBIST) using an LBIST logic circuit and an auxiliary logic circuit. An example method includes using switch circuitry in an integrated circuit (IC) to change modes of operation associated with functional logic circuit, the modes of operation including an LBIST mode and an application mode, and to provide an internally generated digital clock signal to the functional logic circuitry and an LBIST logic circuit in response to the LBIST mode. The method further includes performing an LBIST using the internally generated digital clock signal, the LBIST logic circuit to test select nodes in the IC via control of the functional logic circuitry and via application of digital logic sequences provided as inputs to the I/O pad cells of the IC.

Abstract: A method and a device for generating boundary-scan interconnection lines are disclosed. In the method, the boundary scan test model is established according to boundary scan components and intermediate components on least one test card and a unit under test (UUT) board, and connection relationships therebetween; the boundary scan nets of the boundary scan test model are constructed; the boundary scan paths of each boundary scan net are generated, and a path establishment condition of each boundary scan path is obtained; and the boundary scan paths are filtered and integrated, and the filtered and integrated boundary scan paths are divided according to the path establishment conditions of filtered and integrated boundary scan paths, into subtests which each has at least one boundary-scan interconnection line. As a result, the accuracy and high coverage of a path search operation can be guaranteed.

Abstract: A method of testing a tester, comprising testing electronic units using a plurality of sites in order to obtain first bin assignment, instructing the tester to perform a tester quality test if conditions CiQA,1 and CiQA,2 are met, the tester quality test comprising performing a second plurality of tests on an electronic unit using a first site, thereby obtaining second bin assignment for the electronic unit, the second bin assignment being representative of passing or failing of the electronic unit of the second plurality of tests with respect to at least one second test criteria, wherein CiQA,1 is met if passing first bin assignment has been obtained for said electronic unit connected to the tester using the first site, and wherein CiQA,2 is met if data representative of passing first bin assignment obtained for electronic units which have been tested on the first site, meets a quality criteria.

Abstract: Disclosed is a measuring circuit for quantizing variations in the operating speed of a target circuit. The measuring circuit includes: a signal generator configured to generate a predetermined signal; an adjustable delay circuit configured to generate a first and second delay signals according to the predetermined signal respectively; a signal detector configured to detect the first and second delay signals respectively and thereby generate a first and second detection results respectively; and a calibrating circuit configured to enable a first and second numbers of delay units of the adjustable delay circuit according to the first and second detection results respectively so as to make each of the delays respectively caused by the first and second numbers of delay units be less than a delay threshold, in which the first and second numbers relate to the operating speed of the target circuit operating in the first and second conditions respectively.

Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.

Abstract: Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches. In an IC based on synchronous operation, the operation of the multiplicity of inputs, storage elements and observed outputs in said IC are synchronized to one or more clocks that determine the specific times at which inputs change, outputs are observed, and stored values are updated. Almost all ICs are based on synchronous operation. When input values to a logic circuit in an IC change, the effects of said changes propagate through paths in said logic circuit in a delayed manner such that each of said paths may have a different delay. Said different delays can cause a wire in a logic circuit to have transient values (termed “glitch”) before settling to a final value consistent with the input values being applied to said logic circuit.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

Abstract: The present application discloses a display device and a driving method thereof using the SSD method capable of charge with the data voltage in the pixel circuit and sufficient internal compensation even if the high resolution of a display image is improved. m demultiplexers corresponding to m sets of data signal line groups with k data signal lines being one set are provided. Each demultiplexer sets a prescribed period in a period after a time point when to start supplying a data signal output last in each of horizontal intervals among m data signals to a time point before a time point when to end supplying the data signal is set in advance as a delay period, and a scanning line drive circuit starts to select a scanning line corresponding to the pixel circuit to which the prescribed number of data signals are supplied, when the delay period of each of the horizontal intervals ends.

Abstract: The battery pack includes a base having a heat dissipation wall, a switching device for controlling current having a plurality of electrode terminals, being disposed so as to be capable of transferring released heat to the heat dissipation wall, and a bus bar having a connection terminal that is connected to the switching device or a unit cell so as to enable energization. The connection terminal is disposed so as to be positioned in an area corresponding to a width of the switching device in a direction in which the electrode terminals are arranged in line and in an area extending to a periphery of the switching device in a direction orthogonal to the direction in which the electrode terminals are arranged in line.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: A diagnostic having an analog-to-digital converter that is electrically coupled to an output port of a first analog multiplexer and an output port of a second analog multiplexer is provided. The analog-to-digital converter receives the high side voltage level signal and the low side current level signal at first and second times, respectively, and outputs a high side voltage value and a low side current value, respectively, based on the high side voltage level signal and the low side current level signal, respectively, that are received by a microcontroller. The microcontroller commands a high side driver circuit and a low side driver circuit to transition a contact of the contactor to an open operational position when the first analog multiplexer is malfunctioning based on the high side voltage value.

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: Embodiments provide multi-port communications switches with automated flip emulation for multi-orientation data connectors, for example, to test data connector system components. One embodiment includes multiple ports, each with pins adapted to electrically couple with corresponding structures of a data connector when the connector is physically coupled with the port in any of multiple connector orientations. A flip controller couples pins of first and second ports in accordance with a selected configuration, such that: in a first mode, the flip controller effectively emulates the coupled ports being in a same connector orientation; and in a second mode, the flip controller effectively emulates the coupled ports being in different orientations (e.g., as if one of the connectors is flipped over).

Abstract: What is disclosed are systems and methods of optical feedback for pixel identification, evaluation, and calibration for active matrix light emitting diode device (AMOLED) and other emissive displays. Optical feedback is utilized to calibrate pixel whose output luminance exceeds a threshold difference from a reference value, and may include the use of sparse pixel activation to ensure pixel identification and luminance measurement, as well as a coarse calibration procedure for programming the starting calibration data for a fine calibration stage.