Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.

Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

Abstract: Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Abstract: In accordance with an embodiment, a FinFET device includes: one or more fins, a dummy fin, a gate line, a gate contact landing pad, and a gate contact element. Each of the fins extends in a first direction above a substrate. The dummy fin extends in parallel with the fins in the first direction above the substrate. The gate line extends in a second direction above the substrate, and partially wraps around the fins. The gate contact landing pad is positioned adjacent to or above the dummy fin and electrically coupled to the gate line. The gate contact element is electrically coupled to the gate contact landing pad and is positioned to the top surface thereof.

Abstract: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n? type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.

Abstract: In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anisotropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions.

Abstract: Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium.

Abstract: A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

Abstract: A semiconductor device includes a main gate formed on a semiconductor substrate and a source region and a drain region formed in a surface of the semiconductor substrate on opposite sides of the main gate. An internal gate formed within a portion of the main gate that adjoins the source region.

Abstract: A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

Abstract: In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.

Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.

Abstract: An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region doped to the second conductivity type disposed in the first region. The diode can also comprise a cathode contact electrically contacting the cathode diffusion contact region, an anode disposed in the island, an anode contact electrically contacting the anode, and a first extension region doped to the first conductivity type disposed at a surface junction between the first region and the island.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device that may be capable of obtaining a stable device characteristic by securing an optimal CD of a gate. In embodiments, a method may include forming a gate oxide layer on a semiconductor substrate, forming a photoresist pattern at a first region of an upper portion of the gate oxide layer, forming an insulating layer on the substrate of a second region except for the photoresist pattern, removing the photoresist pattern after a formation of the insulating layer, forming a polysilicon on the substrate from which the photoresist pattern is removed, planarizing the polysilicon to expose the insulating layer in order to form a gate, forming sidewalls at both sides of the gate: and implanting ions in a resulting object using the sidewalls as a mask to form source/drain.

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line includes a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further include gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and the drain region; a first dielectric film formed on the channel region of the semiconductor substrate; a second dielectric film formed on the first dielectric film and having a higher permittivity than the first dielectric film; a third dielectric film formed on at least an end surface of the second dielectric film near the drain region out of end surfaces of the second dielectric film near the source and drain regions; and a gate electrode formed on the second dielectric film and the third dielectric film.

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract: A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.

Abstract: A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate formed over the semiconductor substrate, a source region formed in the semiconductor substrate at one side of the gate, a drain region formed in the semiconductor substrate at another side of the gate, and a channel region formed between the source region and the drain region, the channel region including a first channel region having a first threshold voltage and a second channel region having a second threshold voltage higher than the first threshold voltage. Accordingly, the semiconductor device has two channel regions having different threshold voltages.

Abstract: In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.

Abstract: A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate.

Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include a substrate and a laterally diffused metal oxide semiconductor (LDMOS) device. A semiconductor device may include a second conductive type well formed on and/or over a substrate. An LDMOS device may include a drain disposed on and/or over a substrate. An LDMOS device may include a field oxide at one side of a drain, a first conductive type impurity layer on and/or over a substrate, under a field oxide, and/or a second conductive type impurity layer between a first conductive type impurity layer and a field oxide.

Abstract: A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent to the gate pattern, having a shallower depth than a plurality of device isolation layers.

Abstract: A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished.

Abstract: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

Abstract: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.

Abstract: A lateral diffused metal-oxide-semiconductor field-effect transistor structure including a P substrate, an N+ buried layer, an N epitaxial layer, a P well, an N well, a drain region, a source region, and a body region is disclosed. The N+ buried layer is located between the P substrate and the N epitaxial layer, the P well contacts the N+ buried layer, the source region and the body region are located in the P well, the N well is located in the N epitaxial layer, and the drain region is located in the N well. When a high voltage is applied to the drain and the P substrate is grounded, a breakdown voltage with the P substrate is raised because of the N+ buried layer isolating the P substrate from the N epitaxial layer, so as to be able to avoid PN junction breakdown.

Abstract: There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A laser annealing method for obtaining a crystalline semiconductor film having a large grain size, and a method of manufacturing a semiconductor device using the crystalline semiconductor film, are provided. Using a shape change (convex portion or concave portion) of an amorphous semiconductor film when crystallizing the amorphous semiconductor film using irradiation of laser light, it is possible to intentionally regulate the origin of crystal growth, and to make the grain size large. By then designing the arrangement of an active layer (island shape semiconductor film) so as to contain at least a channel forming region within one grain, it becomes possible to improve the electrical characteristics of a TFT.

Abstract: To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the device, and is formed substantially from the same metal as is the LC metal gate.

Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.

Abstract: A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method.

Abstract: A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of the NMOS and PMOS transistors are connected through hot terminals to a biasing circuit. The drain node of the NMOS transistor is biased positive with respect to the drain node of the PMOS transistor, to extract hot electrons and hot holes from the cold terminal. Biases on the drain nodes and gates of the NMOS and PMOS transistors may be adjusted to optimize the efficiency of the CMOS thermoelectric refrigerator or maximize the thermal power of the CMOS thermoelectric refrigerator. The cold terminal may be configured to cool a selected component in the IC, such as a transistor.

Abstract: A semiconductor device is provide with a semiconductor substrate, a groove formed in the semiconductor substrate, a gate insulting film formed on the inner wall of the groove, a gate electrode formed in the groove, and a source/drain region and an LDD region arranged in the direction that is substantially orthogonal to the substrate surface of the semiconductor substrate.

Abstract: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.

Abstract: Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.

Abstract: A semiconductor circuit is provided that includes a short channel device, and a long channel device that is electrically isolated from the short channel device. The long channel device comprises a plurality of first gate electrodes, a first source region adjacent one of the plurality of first gate electrodes, a first drain region adjacent another of the plurality of first gate electrodes, and a plurality of common source/drain regions positioned between adjacent ones of the plurality of first gate electrodes. The first gate electrodes each overlie portions of a layer of high-dielectric constant (k) gate insulator material. Each of the first gate electrodes are electrically coupled to at least one of the other first gate electrodes.

Abstract: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

Abstract: A semiconductor device includes an isolation region, a semiconductor element region defined by the isolation region, and having a channel forming portion and a recessed portion, the recessed portion being formed between the isolation region and the channel forming portion, and an epitaxial semiconductor portion formed in the recessed portion, wherein the semiconductor element region has a wall portion between the isolation region and the epitaxial semiconductor portion.