Abstract: A memory device according to embodiments includes a cell array region. The cell array region comprises a plurality of transistors sharing a word line, a plurality of memory elements, and a plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned in a pith. The memory device further comprises a second contact positioned in the pith, along an extension of a row of the plurality of first contacts, outside the cell array region, and configured to be in contact with the word line.

Abstract: A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively. The first etching stop feature has a depth D1 and the second etching stop feature has a depth D2. D1 is less than D2. The substrate in the first region and the second region are etched to form a first trench and a second trench respectively. The first trench and the second trench land on the first etching stop feature and the second etching stop feature, respectively.

Abstract: A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

Abstract: Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials. The method further includes filling the remaining portion of the key-hole shaped column with a second number of materials.

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

Abstract: A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model cards that are assigned to plurality of devices. The plurality of devices include a first device having at least one parasitic diode that is associated with at least one isolation well, the PDK file including information of the at least one parasitic diode. A design layout of the integrated circuit corresponding to a result of the pre-layout simulation is generated.

Abstract: A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide (a); and the content of the compound (b) is not less than 20 parts by weight per 100 parts by weight of the polyimide (a).

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: In the condition where a nozzle for applying a coating liquid is disposed on the lower side of a substrate and a substrate surface controlled in wettability is faced down, the nozzle and the substrate are moved relative to each other, whereby the coating liquid is applied to a desired region of the substrate, and then the coating liquid is dried, to obtain a pattern included a dried coating layer.

Abstract: The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Abstract: A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; where the second layer includes a through layer via with a diameter of less than 150 nm, and where at least one of the second transistors includes a back-bias structure.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: The present invention generally relates to a MEMS device in which silicon residues from the adhesion promoter material are reduced or even eliminated from the cavity floor. The adhesion promoter is typically used to adhere sacrificial material to material above the substrate. The adhesion promoter is the removed along with then sacrificial material. However, the adhesion promoter leaves silicon based residues within the cavity upon removal. The inventors have discovered that the adhesion promoter can be removed from the cavity area prior to depositing the sacrificial material. The adhesion promoter which remains over the remainder of the substrate is sufficient to adhere the sacrificial material to the substrate without fear of the sacrificial material delaminating. Because no adhesion promoter is used in the cavity area of the device, no silicon residues will be present within the cavity after the switching element of the MEMS device is freed.

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract: In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract: A semiconductor device, including: a first layer including first transistors; an interconnection layer overlying the first transistors, the interconnection layer providing interconnection for the first transistors; a bonding layer overlying the interconnection layer; a second layer overlying the bonding layer; and a carrier substrate for the transferring of the second layer, where the second layer includes at least one through second layer via, where the at least one through second layer via has a diameter of less than 100 nm, where the second layer includes a plurality of second transistors, and where the second layer is transferred from a donor wafer.

Abstract: A semiconductor device, in which an integrated circuit portion and an antenna are easily connected, can surely transmit and receive a signal to and from a communication device. The integrated circuit portion is formed of a thin film transistor over a surface of a substrate so that the area occupied by the integrated circuit portion is increased. The antenna is provided over the integrated circuit portion, and the thin film transistor and the antenna are connected. Further, the area over the substrate occupied by the integrated circuit portion is 0.5 to 1 times as large as the area of the surface of the substrate. Thus, the size of the integrated circuit portion can be close to the desired size of the antenna, so that the integrated circuit portion and the antenna are easily connected and the semiconductor device can surely transmit and receive a signal to and from the communication device.

Abstract: An optical module providing higher reliability during high-speed light modulation and a lower bit error rate when built into a transmitter (transceiver). An optical module contains a taper mirror for surface emission of output light, an optical modulator device, and an optical modulation drive circuit, and the optical modulator device and the optical modulation drive circuit are mounted at positions so as to enclose the taper mirror.

Abstract: A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.

Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

Abstract: The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base.

Abstract: A method of separating dies of a singulated wafer is disclosed. The method may include supporting the singulated wafer on a supporting portion of a sheet of dicing tape that has a first ring attached to a first annular portion of the sheet that encompasses the supporting portion. The method may further include radially expanding the supporting portion by relative axial displacement of the supporting portion with respect to the first ring. The method may also include further expanding the supporting portion by radially outward displacement of a support surface that supports at least an annular portion of the sheet. The method may also include attaching a second ring to a second annular portion of the sheet.

Abstract: A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.

Abstract: A semiconductor integrated circuit comprises: a transistor region having a center line; a first block arranged in one side of the center line of the transistor region, and comprising a plurality of first and second groups each having a plurality of first and second segment transistors constituting first and second transistors of a differential amplifier; and a second block arranged in the other side of the center line, and having an arrangement corresponding to the arrangement of the first and second groups of the first block.

Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.

Abstract: Devices and methods for pattern alignment are disclosed. The device includes an assembly isolation region, a seal ring region around the assembly isolation region, and a scribe line region around the seal ring region, and a plurality of die alignment marks disposed within the seal ring region that are alternately disposed adjacent the scribe line region and the assembly isolation region.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

Abstract: An interposer device The invention relates to an interposer device comprising a doped silicon substrate (1) having an epitaxial layer (24) on a first side and two through vias (11, 12) extending from the first side to a second side opposite to the first side of the doped silicon substrate. Each through via comprises a volume of doped silicon substrate delimited by a surrounding trench (7) extending from the first to the second side of the doped silicon substrate such that said surrounding trench is arranged so as to electrically isolate the doped silicon substrate surrounded by said trench. First and second conductive layers (121, 122) are laid respectively on first and second sides of the first through via so as to be electrically connected together and third and fourth conductive layers (112, 11) are laid respectively on surfaces of the second through via so as to be electrically connected together.

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Abstract: A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.

Abstract: A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a first fin cut process to remove a subset of the first spacer fins, depositing a second spacer layer over the un-removed first spacer fins, and removing portions of the second spacer layer to form second spacer fins. The method further includes forming fin structures, and performing a second fin cut process to remove a subset of the fin structures.

Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.

Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.