Abstract: A manufacturing method includes sequentially forming first and second material layers having different etch selectivities in a laminated fashion, patterning the second material layer, to form an etch mask, etching the first material layer using the etch mask, to form a via hole in the first material layer, forming a photo mask over the etch mask such that a region larger than the via hole is exposed through the photo mask, etching the etch mask using the photo mask, removing the photo mask, and forming a metal material over the first material layer, to fill the via hole. Accordingly, it is possible to prevent formation of a side wall undercut in a deep via etching process, and thus to ease subsequent processes for forming an oxide barrier film, a barrier metal film, and a metal layer.

Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Abstract: A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate (10) is provided in which the body comprises a doped semiconductor region (24) adjacent a dielectric region (26). The body may further comprise a doped conductive region separated from the semiconductor region by the dielectric region. The material characteristics of single-crystal strontium titanate when doped in various ways are exploited to provide the insulating, conducting and semiconducting components of a MOS stack. Advantageously, the use of a single body avoids the presence of interface layers between the stack components which improves the characteristics of MOS devices such as field effect transistors.

Abstract: An ESD protecting circuit and a manufacturing method thereof are provided. The ESD protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.

Abstract: A semiconductor device fabrication method is disclosed. A buffer layer is provided and a first semiconductor layer is formed on the buffer layer. Next, a first intermediate layer is formed on the first semiconductor layer by dopant with high concentration during an epitaxial process. A second semiconductor layer is overlaid on the first intermediate layer. A semiconductor light emitting device is grown on the second semiconductor layer. The formation of the intermediate layer and the second semiconductor layer is a set of steps.

Abstract: A method of forming a solar cell, the method comprising: providing a semiconducting wafer having a pre-doped region; performing a first ion implantation of a dopant into the semiconducting wafer to form a first doped region over the pre-doped region, wherein the first ion implantation has a concentration-versus-depth profile; and performing a second ion implantation of a dopant into the semiconducting wafer to form a second doped region over the pre-doped region, wherein the second ion implantation has a concentration-versus-depth profile different from that of the first ion implantation, wherein at least one of the first doped region and the second doped region is configured to generate electron-hole pairs upon receiving light, and wherein the first and second ion implantations are performed independently of one another.

Abstract: A solar cell device and method of making are provided. The device includes a silicon substrate including a preexisting dopant. A homogeneous lightly doped region is formed on a surface of the silicon substrate to form a junction between the preexisting dopant and the lightly doped region. A heavily doped region is selectively implanted on the surface of the silicon substrate. A seed layer is formed over the heavily doped region. A metal contact is formed over the seed layer. The device can include an anti-reflective coating. In one embodiment, the heavily doped region forms a parabolic shape. The heavily doped regions can each be a width on the silicon substrate a distance in the range 50 to 200 microns. Also, the heavily doped regions can be laterally spaced on the silicon substrate a distance in the range 1 to 3 mm from each other. The seed layer can be a silicide.

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.

Abstract: Self-supported film and silicon wafer obtained by sintering. A silicon wafer for a photovoltaic cell is produced by a debinding step of a self-supported film formed of at least one main thin layer comprising at least 50% volume of silicon particles, devoid of silicon oxide and encapsulated in a polymer matrix protecting them against oxidation, followed by a sintering step to form the silicon wafer.

Abstract: An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer.

Abstract: A thermal oxidation method capable of obtaining a high oxidation rate by generating a sufficient enhanced-rate oxidation phenomenon even in a low temperature region is provided. In addition, a thermal oxidation method capable of forming a silicon oxide film having a high reliability even when formed at a low temperature region. A basic concept herein is to form a silicon oxide film by thermal reaction by generating a large amount of oxygen radicals (O*) having a large reactivity without using plasma. More specifically, ozone (O3) and other active gas are reacted, so that ozone (O3) is decomposed highly efficiently even in a low temperature region, thereby generating a large amount of oxygen radicals (O*). For example, a compound gas containing a halogen element can be used as the active gas.

Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

Abstract: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.

Abstract: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide with a diffusing dopant. Diffusing dopant from the bond oxide into the backside surface of the device wafer. Depositing an oxide layer on the bond oxide and bonding the deposited oxide layer to the handle wafer of the integrated circuit.

Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.

Abstract: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped layer in a low oxygen environment with a laser beam, a part of the second area overlapping with the first area.

Abstract: A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.

Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.

Abstract: A method of manufacturing a semiconductor device, which has a gate electrode and a pair of diffusion layers formed in a semiconductor substrate on sides of the gate electrode, includes forming an insulating film and a gate electrode on a semiconductor substrate, obtaining a thickness of an affected layer formed in a surface of the semiconductor substrate, forming a pair of diffusion layers by injecting an impurity element into the semiconductor substrate in areas flanking the gate electrodes based on a predetermined injection parameter, performing activating heat treatment based on a predetermined heat treatment parameter, and a parameter deriving step provided between the obtaining step and the diffusion layer forming step, the parameter deriving step deriving the injection parameter or heat treatment parameter in response to the obtained thickness of the affected layer such that the diffusion layers are set to a predetermined sheet resistance.

Abstract: A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth.

Abstract: A method of tailoring the dopant profile of a substrate by utilizing two different dopants, each having a different diffusivity is disclosed. The substrate may be, for example, a solar cell. By introducing two different dopants, such as by ion implantation, furnace diffusion, or paste, it is possible to create the desired dopant profile. In addition, the dopants may be introduced simultaneously, partially simultaneously, or sequentially. Dopant pairs preferably consist of one lighter species and one heavier species, where the lighter species has a greater diffusivity. For example, dopant pairs such as boron and gallium, boron and indium, phosphorus and arsenic, and phosphorus and antimony, can be utilized.

Abstract: A type-II InAs/GaSb superlattice photodiode for optimizing quantum efficiency without reducing the differential resistance area product at zero bias. The photodiode features a GaSb: Be buffer, a In/GaSb: Be superlattice, a p-type doped ? region, a InAs: Si/GaSb doped region, and a InAs: Si doped contact layer. The In/GaSb: Be superlattice and InAs: Si/GaSb doped region each having a thickness about two times greater than the thickness of the GaSb: Be buffer. The photodiode in one embodiment featuring a composition of InAs and GaSb with InSb forced interfaces, the composition suitable for being grown on GaSb wafers with a molecular beam epitaxy reactor. A method of optimizing quantum efficiency in a type-II InAs/GaSb superlattice photodiode having a 100% cutoff wavelength around 12 ?m is further provided herewith.

Abstract: A patterned anti-reflective coating may be used as a selective implant-blocking layer during fabrication of an integrated circuit transistor. In particular, the anti-reflective coating may be used as a gate sidewall spacer to block at least some dopants from an integrated circuit substrate beneath the gate sidewall spacer. Moreover, a single mask may be used when fabricating source and drain extension regions and source and drain regions of an integrated circuit transistor.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.

Abstract: [PROBLEMS] To provide a semiconductor element manufacturing method by which a semiconductor element having high accuracy and high function can be manufactured by controlling diffusion depth and diffusion concentration in a pn junction region with high accuracy. [MEANS FOR SOLVING PROBLEMS] A diffusion control layer (2) composed of a thin film of a substance having a smaller diffusion coefficient than that of a diffusion source (3) is formed between a surface of a substrate (1) and the diffusion source (3), and an element of the diffusion source (3) is permitted to thermally diffuse through the diffusion control layer (2). Thus, the diffusion depth and the diffusion concentration in the semiconductor region, which is formed on the surface portion of the substrate and has a conductivity type different from that of the substrate, can be highly accurately controlled, and the semiconductor element having high accuracy and high function can be manufactured.

Abstract: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.

Abstract: An ion beam irradiating apparatus has a field emission electron source 10 which is disposed in a vicinity of a path of the ion beam 2, and which emits electrons 12. The field emission electron source 10 is placed in a direction along which an incident angle formed by the electrons 12 emitted from the electron source 10 and a direction parallel to the traveling direction of the ion beam 2 is in the range from ?15 deg. to +45 deg. (an inward direction of the ion beam 2 is +, and an outward direction is ?).

Abstract: The aim of the invention is to improve the energy yield efficiency of solar cells. According to the invention, the silicon material is doped with one or more different lanthanides such that said material penetrates into a layer approximately 60 nm deep. Photons, whose energy is at least double that of the 1.2 eV silicon material band gap, are thus converted into at least two photons having energy in the region of the silicon band gap, by excitation and recombination of the unpaired 4f electrons of the lanthanides. As a result, additional photons having advantageous energy close to the silicon band gap are provided for electron-hole pair formation.

Abstract: A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape.

Abstract: A semiconductor device fabrication apparatus includes a load lock chamber, a loading assembly in the load lock chamber, and an ion implantation target chamber that is hermetically connected to the load lock chamber. The load lock chamber is configured to store a plurality of wafer plates. Each wafer plate respectively includes at least one semiconductor wafer thereon. The ion implantation target chamber is configured to implant an ion species into a semiconductor wafer on a currently loaded wafer plate. The loading assembly is also configured to load a next one of the plurality of wafer plates from the load lock chamber into the ion implantation target chamber. The loading assembly may be configured to load the next wafer plate from the load lock chamber into the ion implantation target chamber while substantially maintaining a current temperature within the ion implantation target chamber and/or without depressurizing the ion implantation target chamber. Related methods and devices are also discussed.

Abstract: A semiconductor light emitting device includes an active region, an n-type region, and a p-type region comprising a portion that extends into the active region. The active region may include multiple quantum wells separated by barrier layers, and the p-type extension penetrates at least one of the quantum well layers. The extensions of the p-type region into the active region may provide uniform filling of carriers in the individual quantum wells of the active region by providing direct current paths into individual quantum wells. Such uniform filling may improve the operating efficiency at high current density by reducing the carrier density in the quantum wells closest to the bulk p-type region, thereby reducing the number of carriers lost to nonradiative recombination.

Abstract: A method of manufacturing a semiconductor device in which the formation of buried wiring is facilitated includes: forming columnar patterns, which are arranged in a two-dimensional array, and bridge patterns, which connect the columnar patterns in a column direction, on a main surface of a silicon substrate; injecting an impurity in a surface portion of each of the columnar patterns and bridge patterns and in surface portions of the silicon substrate, thereby forming impurity injection layers; forming a side wall on sides of the columnar patterns and bridge patterns; removing the impurity injection layer, which has been formed in the silicon substrate, with the exception of the impurity injection layer covered by the bottom portions of the side walls; removing the side walls by etch-back; and thermally oxidizing the surface portion of the bridge patterns and then etching away the same. Buried wiring extending in the column direction of the columnar patterns is formed within the silicon substrate.

Abstract: An object of the invention is to provide a plasma doping method and a plasma doping apparatus in which uniformity of concentration of impurities introduced into a sample surface are excellent. The plasma doping apparatus of the invention introduces a predetermined mass flow of gas from a gas supply device (2) into a vacuum chamber (1) while discharging the gas through an exhaust port (11) by a turbo-molecular pump (3), which is an exhaust device in order to maintain the vacuum chamber (1) under a predetermined pressure by a pressure adjusting valve (4). A high-frequency power source (5) supplies high-frequency power of 13.56 MHz to a coil (8) disposed in the vicinity of a dielectric window (7) opposite a sample electrode (6) in order to generate an inductively coupled plasma in the vacuum chamber (1). A high-frequency power source (10) for supplying high-frequency power to the sample electrode (6) is provided.

Abstract: Methods for fabricating semiconductor devices using thermal gradient-inducing films are provided. One method comprises providing a substrate having a first region and a second region and forming a film overlying the second region and exposing the first region. The substrate is subjected to a thermal process wherein the film induces a predetermined thermal gradient between the first region and the second region.

Abstract: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Abstract: A method of introducing an impurity and an apparatus for introducing the impurity forms an impurity layer easily in a shallower profile. Component devices manufactured taking advantage of these method or apparatus are also disclosed. When introducing a material to a solid substance which has an oxidized film or other film sticking at the surface, the present method and apparatus first removes the oxidized film and other film using at least one means selected from among the group consisting of a means for irradiating the surface of solid substance with plasma, a means for irradiating the surface of solid substance with gas and a means for dipping the surface of solid substance in a reductive liquid; and then, attaches or introduces a certain desired particle. The way of attaching, or introducing, a particle is bringing a particle-containing gas to make contact to the surface, which surface has been made to be free of the oxidized film and other film.

Abstract: A method for surface treatment of diamond comprising exposing the surface of diamond to UV light containing wavelengths of 172 nm to 184.9 nm and 253.7 nm at an integrated exposure of 10 to 5,000 J/cm2 in an environment of an atmosphere having an oxygen concentration of 20 to 100% and an ozone concentration of 10 to 500,000 ppm to adsorb oxygen on the surface of diamond.

Abstract: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or a TiO2 precursor, Further, a manufacturing method of a solar cell is provided in which the masking paste is pattern-formed on the semiconductor substrate and then the p-type dopant and the n-type dopant are diffused.

Abstract: A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an insulation material layer on the silicon semiconductor layer after the P-type impurity and the N-type impurity are implanted into the low concentration diffusion layer, the P-type high concentration diffusion layer, and the N-type high concentration diffusion layer; forming an opening portion in the insulation material layer in an area for forming the low concentration diffusion layer; and etching the silicon semiconductor layer in the area for forming the low concentration diffusion layer so that a thickness of the silicon semiconductor layer is reduced to a specific level.

Abstract: A method of fabricating a photo diode includes sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a semiconductor substrate; forming a doped oxide film, including impurities of the second conductivity type, on the second epitaxial layer; forming a silicon nitride film on the oxide film; and patterning the oxide film and the silicon nitride film to sequentially form an oxide film pattern of the second conductivity type and a silicon nitride film pattern, respectively. The second conductivity type impurities are diffused from the oxide film pattern into the second epitaxial layer using a heat diffusion process to form a doped shallow junction layer of the second conductivity type, which converts the oxide film pattern into a non-conductive oxide film pattern.

Abstract: A method for the structuring of multicrystalline silicon substrate surfaces and emitter diffusion into said surfaces comprises the following steps: providing a texturing solution which comprises at least a portion of phosphoric acid, providing a semiconductor substrate with a surface to be structured, coating the surface to be structured with the texturing solution, heating the texturing solution to a heating temperature TT, and heating the texturing solution to a diffusion temperature TD, wherein TD>TT.

Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase.

Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase.

Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase.

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract: It is an object of the present invention to provide a semiconductor device superior in the decrease in leak current due to a short-channel effect and a manufacturing method thereof. In a process of forming a field-effect transistor over a single-crystal semiconductor substrate, an impurity is introduced to form an extension region and a single crystal lattice is broken to make the extension region amorphous. Alternatively, the impurity and an element having large mass number are introduced to break the single crystal lattice and make the extension region amorphous. Then, a laser beam with a pulse width of 1 fs to 10 ps and a wavelength of 370 to 640 nm is delivered to selectively activate the amorphous portion, so that the extension region is formed with a thickness of 20 nm or less.