Diffusion Of Impurity Material, E.g., Doping Material, Electrode Material, Into Or Out Of A Semiconductor Body, Or Between Semiconductor Regions; Interactions Between Two Or More Impurities; Redistribution Of Impurities (epo) Patents (Class 257/E21.135)
  • Patent number: 8163587
    Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface, and depositing an ink on the front substrate surface in an ink pattern, the ink comprising a set of nanoparticles and a set of solvents. The method further includes heating the substrate in a baking ambient to a first temperature of between about 200° C. and about 800° C. and for a first time period of between about 3 minutes and about 20 minutes in order to create a densified film ink pattern. The method also includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl3, a carrier N2 gas, a main N2 gas, and a reactive O2 gas, wherein a ratio of the carrier N2 gas to the reactive O2 gas is between about 1:1 to about 1.5:1, at a second temperature of between about 700° C. and about 1000° C.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: April 24, 2012
    Assignee: Innovalight, Inc.
    Inventors: Giuseppe Scardera, Dmitry Poplavskyy, Michael Burrows, Sunil Shah
  • Publication number: 20120083104
    Abstract: A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns.
    Type: Application
    Filed: June 29, 2011
    Publication date: April 5, 2012
    Inventors: Malcolm Abbott, Maxim KELMAN, Eric ROSENFELD, Elena ROGOJINA, Giuseppe SCARDERA
  • Publication number: 20120083105
    Abstract: A process for P-type boron doping of silicon wafers placed on a support in the chamber of a furnace of whose one end includes a wall in which element for introducing reactive gases and a carrier gas carrying a boron precursor in gaseous form are located, whereby the process includes the following stages: a) reacting in the chamber, the reactive gases with boron trichloride BCl3 that is diluted in the carrier gas at a pressure of between 1 kPa and 30 kPa, and a temperature of between 800° C. and 1100° C., to form a boron oxide B2O3 glass layer; and b) carrying out the diffusion of atomic boron in silicon under an N2+O2 atmosphere at a pressure of between 1 kPa and 30 kPa. A furnace designed for implementing the doping process, and the manufacturing of large boron-doped silicon slices, in particular for photovoltaic applications are also claimed.
    Type: Application
    Filed: April 6, 2010
    Publication date: April 5, 2012
    Applicant: SEMCO ENGINEERING SA
    Inventor: Yvon Pellegrin
  • Publication number: 20120077304
    Abstract: A method for forming an impurity layer, includes forming a resist material 16 on a surface portion of a semiconductor substrate 15; exposing the resist material using a grating mask 10 comprising a light transmission region 11 including a plurality of unit light transmission regions 14 being arranged two-dimensionally, each being composed of a plurality of minute partial sections 13A to 13D having different transmittance; forming a resist layer 18 on the surface of the semiconductor substrate 15 by developing the exposed resist material, the resist layer including a thin film region 17 having a film thickness corresponding to the transmittance of the light transmission region; implanting ions to the semiconductor substrate 15 via the thin film region; and diffusing ion groups 21A?, 21B?, 21C?, and 21D? that are implanted at the same depth such that the ion groups are coupled in a lateral direction.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ken TOMITA, Yoshihiro Obara
  • Patent number: 8143693
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Duk Baek, Sun-Won Kang, Hyun-Soo Chung
  • Publication number: 20120058588
    Abstract: The invention relates to a device and a method for simultaneous microstructuring and doping of semiconductor substrates with boron, in which the semiconductor substrate is treated with a laser beam coupled into a liquid jet, the liquid jet comprising at least one boron compound. The method according to the invention is used in the field of solar cell technology and also in other fields of semiconductor technology in which a locally delimited boron doping is important.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 8, 2012
    Applicant: FRAUNHOFER-GESELLSCHAFT zur Forderung der angewandten Forschung e.V.
    Inventors: Kuno Mayer, Ingo Krossing, Carsten Knapp, Filip Granek, Matthias Mesec, Andreas Rodofili
  • Publication number: 20120052665
    Abstract: Disclosed are methods of forming multi-doped junctions, which utilize a nanoparticle ink to form an ink pattern on a surface of a substrate. From the ink pattern, a densified film ink pattern can be formed. The disclosed methods may allow in situ controlling of dopant diffusion profiles.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 1, 2012
    Inventors: Giuseppe Scardera, Dmitry Poplavskyy, Michael Burrows, Sunil Shah
  • Patent number: 8124511
    Abstract: One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is achieved by forming gate electrodes over a semiconductor substrate, amorphizing the semiconductor substrate that creates amorphous regions adjacent the gate electrodes to a depth in the semiconductor substrate. Source/drains are formed adjacent the gate electrodes by placing conductive dopants in the semiconductor substrate, wherein displaced substrate atoms and the conductive dopants are contained within the depth of the amorphous regions. The semiconductor substrate is annealed to re-crystallize the amorphous regions subsequent to forming the source/drains.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: February 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Amitabh Jain
  • Publication number: 20120045887
    Abstract: Semiconductor materials suitable for being used in radiation detectors are disclosed. A particular example of the semiconductor materials includes tellurium, cadmium, and zinc. Tellurium is in molar excess of cadmium and zinc. The example also includes aluminum having a concentration of about 10 to about 20,000 atomic parts per billion and erbium having a concentration of at least 10,000 atomic parts per billion.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Applicant: WASHINGTON STATE UNIVERSITY RESEARCH FOUNDATION
    Inventors: Kelvin Lynn, Kelly Jones, Guido Ciampi
  • Publication number: 20120043540
    Abstract: The present invention provides a semiconductor device capable of suppressing a contact failure due to an increase in contact resistance, a production method of the semiconductor device, and a display device.
    Type: Application
    Filed: October 30, 2009
    Publication date: February 23, 2012
    Inventor: Tomohiro Kimura
  • Publication number: 20120032310
    Abstract: A process for producing a semiconductor device comprises the following process steps: provision of a semiconductor substrate (1); formation of a functional layer (2) on a semiconductor surface (11) of the semiconductor substrate (1); and production of at least one doped section (3) on the semiconductor surface (11) by driving a dopant into the semiconductor substrate (1) from the functional layer (2). The functional layer (2) is formed in such a way that it passivates the semiconductor surface (11), acting as a passivation layer upon completion of the semiconductor device.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 9, 2012
    Applicant: Q-CELLS SE
    Inventors: Peter ENGELHART, Stefan BORDIHN, Maximilian SCHERFF, Bernhard KLÖTER
  • Publication number: 20120032305
    Abstract: A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 9, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shoji KITAMURA
  • Patent number: 8106429
    Abstract: Disclosed is an image sensor. The image sensor includes a semiconductor substrate including a lower interconnection, a plurality of upper interconnection sections protruding upward from the semiconductor substrate, a first trench disposed between the upper interconnection sections such that the upper interconnection sections are spaced apart from each other, a bottom electrode disposed on an outer peripheral surfaces of the upper interconnection sections, a first conductive layer disposed on an outer peripheral surface of the bottom electrode, an intrinsic layer disposed on the semiconductor substrate including the first conductive layer and the first trench, and having a second trench on the first trench, a second conductive layer disposed on the intrinsic layer and having a third trench on the second trench, a light blocking part disposed in the third trench, and a top electrode disposed on the light blocking part and the second conductive layer.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: January 31, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Tae Gyu Kim
  • Publication number: 20120018856
    Abstract: Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.
    Type: Application
    Filed: July 23, 2010
    Publication date: January 26, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Joachim Weyers, Armin Willmeroth, Anton Mauder, Franz Hirler
  • Publication number: 20120018702
    Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: The Regents of the University of California
    Inventors: Ali Javey, Alexandra C. Ford, Johnny C. Ho
  • Publication number: 20120021557
    Abstract: A method for manufacturing a solar cell comprises disposing a first doping layer on a substrate, forming a first doping layer pattern by patterning the first doping layer to expose a portion of the substrate, disposing a second doping layer on the first doping layer pattern to cover the exposed portion of the substrate, diffusing an impurity from the first doping layer pattern which forms a first doping region in a surface of the substrate, and diffusing an impurity from the second doping layer which forms a second doping region in the surface of the substrate, wherein the forming of the first doping layer pattern uses an etching paste.
    Type: Application
    Filed: November 4, 2010
    Publication date: January 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Su KIM, Sang Ho KIM
  • Patent number: 8102026
    Abstract: To provide a group-III nitride semiconductor freestanding substrate, with carrier concentration of a peripheral part of a n-type group-III nitride semiconductor freestanding substrate set to be lower than the carrier concentration inside of the peripheral part. In this freestanding substrate, preferably value ?? obtained by dividing a difference between a maximum value of the carrier concentration and a minimum value of the carrier concentration in a surface of the freestanding substrate by the maximum value of the carrier concentration is greater than 0.05, and the carrier concentration in any place in the surface of the freestanding substrate exceeds 5.0×1017 cm?3.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 24, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Eri, Takeshi Meguro
  • Publication number: 20120015508
    Abstract: Provided is a method of manufacturing a semiconductor device capable of preventing a relative displacement of the positions between a range where impurity ions are injected and a range where charged particles are injected. The method of manufacturing the semiconductor device includes: irradiating impurity ions in a state in which a mask is disposed between an impurity ion irradiation apparatus and a semiconductor substrate; and irradiating charged particles to form a short carrier lifetime region, in a state in which the mask is disposed between a charged particle irradiation apparatus and the semiconductor substrate. A relative positional relationship between the mask and the semiconductor substrate is not changed from a beginning of one of the irradiating the impurity ions and the irradiating the charged particles to a completion of both of the irradiating the impurity ions and the irradiating the charged particles.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya IWASAKI, Akira KAMEI
  • Publication number: 20120009749
    Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Dexter TAN, Kin Leong PEY, Sai Hooi YEONG, Yoke King CHIN, Kuang Kian ONG, Chee Mang NG
  • Publication number: 20120003826
    Abstract: Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred.
    Type: Application
    Filed: March 8, 2011
    Publication date: January 5, 2012
    Inventors: Kimberly Dona Pollard, Allison C. Rector
  • Publication number: 20110309412
    Abstract: Superjunction collectors for transistors are discussed in this application. According to one embodiment, a bipolar transistor having a superjunction collector structure can comprise a collector electrode, a base electrode, an emitter electrode, a collector-base space charge region, and a superjunction collector. The collector-base space charge region can be disposed in electrical communication between the collector electrode and the base electrode. The superjunction collector region can be disposed in the collector-base space charge region. The superjunction collector region can comprise a plurality of alternating horizontally disposed P-type and N-type layers. The layers can be horizontally disposed layers that are layered on top of each other. The P-type and N-type layers can be doped with different types of doping levels. Other aspects, embodiments, and features are also discussed and claimed.
    Type: Application
    Filed: April 8, 2010
    Publication date: December 22, 2011
    Applicant: Georgia Tech Research Corporation
    Inventors: Jiahui Yuan, John D. Cressler
  • Publication number: 20110303265
    Abstract: A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).
    Type: Application
    Filed: June 9, 2010
    Publication date: December 15, 2011
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: Hao-Chih Yuan, Howard M. Branz, Matthew R. Page
  • Publication number: 20110306160
    Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The bands or chains are driven synchronously at ultra-low tension by a pin drive roller or sprocket at either the inlet or outlet end of the furnace, with appropriate tensioning systems disposed in the return path. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces.
    Type: Application
    Filed: August 19, 2011
    Publication date: December 15, 2011
    Applicant: TP SOLAR, INC.
    Inventors: Richard W. Parks, Luis Alejandro Rey Garcia, Peter G. Ragay
  • Publication number: 20110300697
    Abstract: Disclosed is a method of fabricating a semiconductor device, including the steps of forming a diffusion preventing mask on a surface of a semiconductor substrate, applying a dopant diffusing agent containing a dopant of a first conductivity type or a second conductivity type onto the surface of the semiconductor substrate at a spacing from the diffusion preventing mask, and forming a dopant diffusion layer by diffusing the dopant from the dopant diffusing agent into the semiconductor substrate.
    Type: Application
    Filed: February 24, 2010
    Publication date: December 8, 2011
    Inventors: Masatsugu Kohira, Yasushi Funakoshi
  • Publication number: 20110298092
    Abstract: An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.
    Type: Application
    Filed: April 27, 2011
    Publication date: December 8, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ming-Yeh Chuang
  • Publication number: 20110298104
    Abstract: A semiconductor body comprises a protective structure. The protective structure (10) comprises a first and a second region (11, 12) which have a first conductivity type and a third region (13) that has a second conductivity type. The second conductivity type is opposite the first conductivity type. The first and the second region (11, 12) are arranged spaced apart in the third region (13), so that a current flow from the first region (11) to the second region (12) is made possible for the limiting of a voltage difference between the first and the second region (11, 12). The protective structure comprises an insulator (14) that is arranged on the semiconductor body (9) and an electrode (16) that is constructed with floating potential and is arranged on the insulator (14).
    Type: Application
    Filed: September 16, 2009
    Publication date: December 8, 2011
    Applicant: Austriamicrosystems AG
    Inventor: Hubert Enichlmair
  • Publication number: 20110298056
    Abstract: A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 8, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tak Hung Ning, Zhen Zhang
  • Publication number: 20110298100
    Abstract: Disclosed are a semiconductor device producing method and a semiconductor device. The semiconductor device producing method is comprised of a step of forming a diffusion suppressing mask composed of at least two of a thick film portion, an opening portion, and a thin film portion, on a surface of a semiconductor substrate; a step of applying dopant diffusing agents containing dopants to the entirety of a surface of the diffusion suppression mask; and a step of diffusing the dopants obtained from the dopant diffusing agents onto the surface of the semiconductor substrate. In the semiconductor device, a high concentration first conductive dopant diffusion layer, a high concentration second conductive dopant diffusion layer, a low concentration first conductive dopant diffusion layer, and a low concentration second conducive dopant diffusion layer are provided on one of the surfaces of the semiconductor substrate.
    Type: Application
    Filed: January 25, 2010
    Publication date: December 8, 2011
    Inventor: Kyotaro Nakamura
  • Patent number: 8072043
    Abstract: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: December 6, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Peter Flohrs, Alfred Goerlach, Peter Urbach, Wolfgang Feiler, Ning Qu, Klaus Heyers
  • Patent number: 8071444
    Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Wakako Takeuchi
  • Publication number: 20110287616
    Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.
    Type: Application
    Filed: June 30, 2011
    Publication date: November 24, 2011
    Inventor: François Hébert
  • Publication number: 20110287618
    Abstract: Disclosed is a method of manufacturing a silicon carbide semiconductor apparatus which provides a smooth silicon carbide surface while maintaining a high impurity activation ratio. The method of manufacturing a silicon carbide semiconductor apparatus which forms an impurity region in the surface layer of a silicon carbide substrate includes the steps of implanting an impurity into the surface layer of the silicon carbide substrate, forming a carbon film on the surface of the silicon carbide substrate, preliminarily heating the silicon carbide substrate with the carbon film as a protective film, and thermally activating the silicon carbide substrate with the carbon film as a protective film.
    Type: Application
    Filed: November 9, 2009
    Publication date: November 24, 2011
    Applicant: SHOWA DENKO K.K.
    Inventor: Kenji Suzuki
  • Publication number: 20110284905
    Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 24, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiya YOKOGAWA, Mitsuaki OYA, Atsushi YAMADA, Ryou KATO
  • Patent number: 8063486
    Abstract: A circuit board 1 having a base material 10 and an electrode 11 formed on at least one main surface of the base material 10 includes an easy peeling portion 12 formed in at least one of an inner portion and a side portion of the electrode 11, with the adhesive strength between the electrode 11 and the easy peeling portion 12 being less than the adhesive strength between the electrode 11 and the base material 10. A circuit board that has high connection reliability and enables narrow pitch mounting thereby can be provided.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Tsukasa Shiraishi, Seiichi Nakatani, Tatsuo Ogawa
  • Publication number: 20110278694
    Abstract: A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 ?m and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 ?m.
    Type: Application
    Filed: June 15, 2011
    Publication date: November 17, 2011
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Ulrich Schlapbach, Arnost Kopta
  • Patent number: 8053344
    Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ka-Hing Fung, Wei-Yuan Lu, Han-Ting Tsai
  • Patent number: 8053340
    Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 8, 2011
    Assignees: National University of Singapore, Globalfoundries Singapore Pte. Ltd.
    Inventors: Benjamin Colombeau, Sai Hooi Yeong, Francis Benistant, Bangun Indajang, Lap Chan
  • Publication number: 20110269263
    Abstract: In a method for implanting impurities into a substrate and a method for manufacturing a solar cell using the method, a substrate is dipped into a first solution including a first impurity, and a laser is irradiated to a first region of the substrate dipped into the first solution is irradiated with laser to implant a first dopant generated from the first impurity into the first region. Accordingly, the first dopant generated from the first impurity is implanted into the substrate at room temperature to improve reliability for implanting the first dopant.
    Type: Application
    Filed: December 3, 2010
    Publication date: November 3, 2011
    Inventor: Yoon-Mook KANG
  • Publication number: 20110263110
    Abstract: A film-forming composition for use in a coating diffusion method, capable of diffusing a dopant at a higher concentration, and further capable of concomitantly forming a silica-based coating film is provided. A film-forming composition for constituting a diffusion film provided for diffusing a dopant element into a silicon wafer, the film-forming composition including: (A) a polymeric silicon compound; (B) an oxide of the dopant element, or a salt including the dopant element; and (C) porogene.
    Type: Application
    Filed: July 1, 2011
    Publication date: October 27, 2011
    Applicant: TOKYO OHKA KOGYO CO., LTD.
    Inventor: Toshiro Morita
  • Publication number: 20110263111
    Abstract: Group III-nitride N-type doping techniques are described.
    Type: Application
    Filed: March 24, 2011
    Publication date: October 27, 2011
    Inventors: Yuriy Melnik, Olga Kryliouk, Lu Chen, Hidehiro Kojiri, Tetsuya Ishikawa
  • Patent number: 8043943
    Abstract: A method for forming polycrystalline semiconductor film from amorphous semiconductor film at reduced temperatures and/or accelerated rates. The inclusion of a small percentage of semiconductor material, such as 2% within the metal layer, reduces the temperatures required for crystallization of the amorphous semiconductor by at least 50° C. in comparison to the use of the metal layer without the small percentage of semiconductor material. During a low temperature isothermal annealing process adjacent Al-2% Si and a-Si films undergo a layer exchange resulting in formation of a continuous polycrystalline silicon film having good physical and electrical properties. Formation of polycrystalline-semiconductor in this manner is suitable for use with low temperature substrates (e.g., glass, plastic) as well as with numerous integrated circuit and MEMs fabrication devices and practices.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: October 25, 2011
    Assignee: The Regents of the University of California
    Inventors: Roya Maboudian, Frank W. DelRio, Joanna Lai, Tsu-Jae King Liu
  • Publication number: 20110254118
    Abstract: A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 20, 2011
    Inventors: Zia Alan Shafi, Jeffrey A. Babcock
  • Patent number: 8039937
    Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, Seung-Kwan Ryu, Ju-Il Choi, Dong-Ho Lee, Seong-Deok Hwang
  • Patent number: 8039289
    Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The bands or chains are driven synchronously at ultra-low tension by a pin drive roller or sprocket at either the inlet or outlet end of the furnace, with appropriate tensioning systems disposed in the return path. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: October 18, 2011
    Assignee: TP Solar, Inc.
    Inventors: Richard W. Parks, Luis Alejandro Rey Garcia, Peter G. Ragay
  • Publication number: 20110248267
    Abstract: In connection with various example embodiments, an organic electronic device is provided with an organic material that is susceptible to decreased mobility due to the trapping of electron charge carriers in response to exposure to air. The organic material is doped with an n-type dopant that, when combined with the organic material, effects air stability for the doped organic material (e.g., exhibits a mobility that facilitates stable operation in air, such as may be similar to operation in inert environments). Other embodiments are directed to organic electronic devices n-doped and exhibiting such air stability.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 13, 2011
    Inventors: Peng Wei, Zhenan Bao, Joon Hak Oh
  • Patent number: 8034700
    Abstract: A method of fabricating a diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 11, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Reiner Barthelmess
  • Publication number: 20110241182
    Abstract: An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track.
    Type: Application
    Filed: November 10, 2009
    Publication date: October 6, 2011
    Applicant: CAMBRIDGE SILICON RADIO LTD.
    Inventors: Rainer Herberholz, Howard Godfrey
  • Publication number: 20110244627
    Abstract: In a method of manufacturing a photoelectric conversion device having a pixel region and a peripheral circuit region, a semiconductor compound layer is formed by causing a surface of a diffusion layer or gate electrode of a MOS transistor in the peripheral circuit region to react with a high melting point metal, then an insulating layer is formed in the pixel region and the peripheral circuit region after the step of forming a semiconductor compound layer. A contact hole is formed in the insulating layer to expose a diffusion layer in the pixel region, and a contact hole is formed in the insulating layer to expose the semiconductor compound layer formed in the peripheral circuit region. These holes are formed at different timings. Prior to forming the hole which is formed later, a contact plug is formed in the contact hole which is formed earlier.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 6, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takehito Okabe, Hiroaki Naruse, Ryuichi Mishima, Kouhei Hashimoto
  • Patent number: 8030188
    Abstract: Provided is a method of forming a compound semiconductor device. In the method, a dopant element layer is formed on an undoped compound semiconductor layer. An annealing process is performed to diffuse dopants in the dopant element layer into the undoped compound semiconductor layer, thereby forming a dopant diffusion region. A rapid cooling process is performed using liquid nitrogen with respect to the substrate having the dopant diffusion region.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi-Ran Park, Jae-Sik Sim, Yong-Hwan Kwon, Bongki Mheen, Dae Kon Oh
  • Publication number: 20110227071
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 22, 2011
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu