Assembling Semiconductor Devices, E.g., Packaging , Including Mounting, Encapsulating, Or Treatment Of Packaged Semiconductor (epo) Patents (Class 257/E21.499)

  • Patent number: 9040352
    Abstract: A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shun Meen Kuo, Li Li
  • Patent number: 9041189
    Abstract: A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: May 26, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Meng-Tsung Lee, Chiang-Cheng Chang, Shih-Kuang Chiu
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Patent number: 9040355
    Abstract: A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Philip H. Bowles, Paige M. Holm, Stephen R. Hooper, Raymond M. Roop
  • Patent number: 9041179
    Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: May 26, 2015
    Assignee: SONY CORPORATION
    Inventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
  • Patent number: 9040347
    Abstract: A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 26, 2015
    Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
    Inventors: Yujuan Tao, Lei Shi
  • Patent number: 9034751
    Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: May 19, 2015
    Assignee: Infineon Technologies AG
    Inventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
  • Patent number: 9035466
    Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface contains a black pigment.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 19, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Takeshi Matsumura, Goji Shiga
  • Patent number: 9036678
    Abstract: A fiber coupled semiconductor device and a method of manufacturing of such a device are disclosed. The method provides an improved stability of optical coupling during assembly of the device, whereby a higher optical power levels and higher overall efficiency of the fiber coupled device can be achieved. The improvement is achieved by attaching the optical fiber to a vertical mounting surface of a fiber mount. The platform holding the semiconductor chip and the optical fiber can be mounted onto a spacer mounted on a base. The spacer has an area smaller than the area of the platform, for mechanical decoupling of thermally induced deformation of the base from a deformation of the platform of the semiconductor device. Optionally, attaching the fiber mount to a submount of the semiconductor chip further improves thermal stability of the packaged device.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: May 19, 2015
    Assignee: JDS Uniphase Corporation
    Inventors: Reddy Raju, Richard L. Duesterberg, Jay A. Skidmore, Prasad Yalamanchili, Xiangdong Qiu
  • Patent number: 9029983
    Abstract: In one embodiment, a chip comprises a capacitor and a resistor. The capacitor comprises a first capacitor terminal, a second capacitor terminal, and a dielectric layer between the first and second capacitor terminals. The second capacitor terminal and the resistor are both fabricated from a resistor metal layer.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: May 12, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Haining Yang
  • Patent number: 9029991
    Abstract: An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 12, 2015
    Assignee: Conexant Systems, Inc.
    Inventors: Robert W. Warren, Hyun Jung Lee, Nic Rossi
  • Patent number: 9029989
    Abstract: A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Soojeoung Park
  • Patent number: 9018039
    Abstract: A circuit module includes a circuit substrate, at least one mount component, sealing bodies, and a shield. The circuit substrate includes a mount surface. The mount component is mounted on the mount surface. The sealing body is formed on the mount surface, covers the mount component and has a first sealing body section having a first thickness and a second sealing body section having a second thickness larger than the first thickness. The shield covers the sealing body and has a first shield section formed on the first sealing body section and having a third thickness and a second shield section formed on the second sealing body section and having a fourth thickness smaller than the third thickness. The sum of the fourth thickness and the second thickness equals to the sum of the first thickness and the third thickness.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 28, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Eiji Mugiya, Takehiko Kai, Masaya Shimamura, Tetsuo Saji, Hiroshi Nakamura
  • Patent number: 9013017
    Abstract: A method of making image sensor devices may include forming a sensor layer including image sensor ICs in an encapsulation material, bonding a spacer layer to the sensor layer, the spacer layer having openings therein and aligned with the image sensor ICs, and bonding a lens layer to the spacer layer, the lens layer including lens in an encapsulation material and aligned with the openings and the image sensor ICs. The method may also include dicing the bonded-together sensor, spacer and lens layers to provide the image sensor devices. Helpfully, the method may use WLP to enhance production.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Yonggang Jin, Laurent Herard, WeeChinJudy Lim
  • Patent number: 9006007
    Abstract: A method for producing an optoelectronic assembly (12) is provided, in which an optoelectronic component (16) is arranged on a carrier (14). Electrical terminals of the optoelectronic component (16) are electrically coupled to electrical contacts of the carrier (14) corresponding thereto. A dummy body (20) is arranged on a first side of the optoelectronic component (16) facing away from the carrier (14). A potting material (22) is arranged on the carrier (14), which potting material at least partially encloses the optoelectronic component (16) and at least partially encloses the dummy body (20). The dummy body (20) is removed, after the potting material (22) is dimensionally stable, whereby a recess (23) results, which is at least partially enclosed by the dimensionally stable potting material (22). An optically functional material (24) is decanted into the recess (23).
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 14, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Markus Schneider
  • Patent number: 9006840
    Abstract: A semiconductor device includes a plurality of semiconductor chips in a stack structure and a through-silicon via suitable for passing through the chips and transfer a signal from or to one or more of the chips. Each of the chips includes a buffering block disposed in path of the through-silicon via, and suitable for buffering the signal, an internal circuit, and a delay compensation block suitable for applying delay corresponding to the buffering blocks of the chips to the signal, wherein the delay compensation blocks of the chips compensates for delay difference of the signal transferred to and from the internal circuit of the chip, due to operations of the buffering block, based on stack information for distinguishing the chips.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sang-Hoon Shin, Young-Ju Kim
  • Patent number: 8999770
    Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 7, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Tien-Ming Lin, Chih-Hsuan Sun, Wei-Yu Yeh
  • Patent number: 8994188
    Abstract: A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Shin-Puu Jeng, Tsang-Jiuh Wu
  • Patent number: 8993377
    Abstract: A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Jun Mo Koo, Pandi C. Marimuthu, Seung Wook Yoon, Il Kwon Shim
  • Patent number: 8993378
    Abstract: A method for assembling a flip chip ball grid array package includes mounting solder spheres to a ball grid array substrate, applying flux to a plurality of flip chip solder bumps provided on a diced wafer, aligning the ball grid array substrate over a chip on the diced wafer, picking and separating the chip from the diced wafer by urging the chip upwards towards the ball grid array substrate until the flip chip solder bumps on the chip come in contact with the ball grid array substrate, whereby the chip attaches to the ball grid array substrate in an upside-down orientation, and subjecting the chip and the ball grid array substrate to a thermal process whereby the solder spheres reflow and form solder balls and the flip chip solder bumps reflow and form solder joints between the chip and the ball grid array.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chih Liu, Jing Ruei Lu, Wei-Ting Lin, Sao-Ling Chiu, Hsin-Yu Pan
  • Patent number: 8993376
    Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Emmanuel A. Espiritu, Henry D. Bathan, Dioscoro A. Merilo
  • Patent number: 8988299
    Abstract: A chip package includes a plurality of layers including conductive planes connected by vias. The layers include a first portion having an antenna formed therein and a parallel-plate mode suppression mechanism to suppress parallel-plate mode excitation of the antenna. The parallel-plate mode suppression mechanism includes a reflector offset from an antenna ground plane and first grounded vias. A second portion has an interface for connecting to an integrated circuit device wherein the first portion and the second portion are separated by the parallel-plate mode suppression mechanism.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dong G. Kam, Duixian Liu, Scott K. Reynolds
  • Patent number: 8987050
    Abstract: Methods and systems for backside dielectric patterning for wafer warpage and stress control are disclosed and may include thinning a semiconductor wafer comprising one or more through silicon vias (TSVs) and one or more die to expose the TSVs on a first surface of the wafer. The wafer may be passivated by depositing dielectric layers. The passivated wafer may be planarized and portions dielectric layers may be selectively removed to reduce a strain on the wafer. Metal contacts may be placed on the exposed TSVs prior to or after the selectively removal. The die may comprise functional electronic die or interposer die. Portions of the dielectric layers may be selectively removed in a radial pattern and may comprise a nitride and/or silicon dioxide layer. The wafer may be thinned to below a top surface of the TSVs. The dielectric layers may be selectively removed utilizing a dry etch process.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: March 24, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: David Jon Hiner, Ronald Patrick Huemoeller, Michael G. Kelly
  • Patent number: 8987922
    Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Wen-Hsiung Lu, Hung-Jen Lin
  • Patent number: 8987889
    Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 24, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Patrick Lawrence Welch, Yifan Guo
  • Patent number: 8980687
    Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Stefan Landau, Joachim Mahler, Alexander Heinrich, Ralf Wombacher
  • Patent number: 8981514
    Abstract: A semiconductor package includes a light transmissive cover having a conductive pattern, a substrate having a cavity, a semiconductor chip in the cavity of the substrate and electrically connected to the conductive pattern arranged on the light transmissive cover, and a blocking pattern between the light transmissive cover and the substrate.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Sung Ryu, Byoung-Rim Seo, In-Won O
  • Patent number: 8980689
    Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
  • Patent number: 8975105
    Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 10, 2015
    Assignee: Raytheon Company
    Inventor: Cody B. Moody
  • Patent number: 8975734
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8975090
    Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 10, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Toma Fujita
  • Patent number: 8975092
    Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Chihiro Uchibori, Michael G. Lee
  • Patent number: 8969134
    Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
  • Patent number: 8969135
    Abstract: A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the down bond area from die attach material, which may occur during a die attach process.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peng Liu, Qingchun He, Zhaobin Qi, Liqiang Xu, Tong Zhao
  • Patent number: 8969143
    Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
  • Patent number: 8969102
    Abstract: A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Peter S. Schultz
  • Patent number: 8962485
    Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohamed Salama, Tuhin Guha Neogi, Scott Beasor
  • Patent number: 8963317
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 8963197
    Abstract: An LED package includes a package body having a well formed in its upper surface, where the well is configured to receive a light emitting chip. An optical lens is disposed above the package body and includes a hollow dome structure located above and encompassing the lateral extent of the light emitting chip within the well of the package body. In one implementation, the package body and the optical lens collectively include at least one protrusion and concave, where the protrusion is aligned with the concave so that the optical lens mates with the package body, thereby causing the optical lens to self align with the package body. In another implementation, a protruding inner portion of the upper surface of the package body mates with the hollow dome structure, achieving a similar purpose. Consequently, generation of an eccentric fault between the optical lens and the package body is prevented.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Myung Soo Han, Seung Ho Jang, Won Seok Choi
  • Patent number: 8957513
    Abstract: A semiconductor device comprising: a lower semiconductor package that comprises a first set of one or more semiconductor dies, an upper semiconductor package that is stacked on the lower semiconductor package, the upper semiconductor package comprises a second set of one or more semiconductor dies, and a first interconnect pad that is embedded in a top side of the lower semiconductor package to couple the upper semiconductor package to the lower semiconductor package.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 17, 2015
    Assignee: Intel Corporation
    Inventors: Ke Xiao, Henry K. Hong, Gunaranjan Viswanathan
  • Patent number: 8957457
    Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 17, 2015
    Assignee: STMicroelectronics SA
    Inventors: Richard Fournel, Pierre Dautriche
  • Patent number: 8956904
    Abstract: A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Analog Devices, Inc.
    Inventors: John R. Martin, Timothy J. Frey, Christine H. Tsau, Michael W. Judy
  • Patent number: 8952404
    Abstract: A light-emitting device package having improved connection reliability of a bonding wire, heat dissipation properties, and light quality due to post-molding and a method of manufacturing the light-emitting device package. The light-emitting device package includes, for example, a wiring substrate having an opening; a light-emitting device that is disposed on the wiring substrate and covers the opening; a bonding wire electrically connecting a bottom surface of the wiring substrate to a bottom surface of the light-emitting device via the opening; a molding member that surrounds a side surface of the light-emitting device and not a top surface of the light-emitting device, which is an emission surface, is formed on a portion of a top surface of the wiring substrate, and is formed in the opening of the wiring substrate to cover the bonding wire; and a solder resist and a bump formed on the bottom surface of the wiring substrate.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-jun Yoo, Young-hee Song
  • Patent number: 8952479
    Abstract: A method of forming a focal plane array by: preparing a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer; preparing a second wafer including read-out integrated circuit and a contact pad, which is covered by another sacrificial layer into which are formed support legs in contact with the contact pad, the support legs being covered with a further sacrificial layer; bonding the sacrificial layers of the first and second wafers together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; defining a pixel in the sensing material and forming a conductive via through the pixel for providing a connection between an uppermost surface of the pixel and the supporting legs; and removing the sacrificial layers to release the pixel, with the supporting legs underneath it.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 10, 2015
    Assignee: SensoNor AS
    Inventors: Adriana Lapadatu, Gjermund Kittilsland
  • Patent number: 8952452
    Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
  • Patent number: 8952528
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi Che Lai
  • Patent number: 8952529
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JaeHyun Lee, SunJae Kim, JoongGi Kim
  • Patent number: 8951833
    Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: February 10, 2015
    Assignee: WaferTech, LLC
    Inventor: Kun-Yi Liu
  • Patent number: 8952519
    Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: February 10, 2015
    Inventors: Chia-Sheng Lin, Po-Han Lee
  • Patent number: 8952512
    Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 10, 2015
    Assignee: China Wafer Level CSP Ltd.
    Inventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang