Abstract: A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film.

Abstract: Integrated circuits and methods for fabricating an integrated circuit are provided. A conductive feature is formed in a semiconductor substrate. A layer of ULK or LK dielectric material is formed overlying the conductive feature. An opening having a sidewall surface is etched through the layer of ULK or LK dielectric material. Damage on the sidewall surface resulting from the etching is removed. An ULK or LK dielectric liner is formed overlying the sidewall surface. The ULK or LK dielectric liner along the bottom of the opening is removed to expose the conductive feature. The opening is filled with a metal fill material contacting the conductive feature.

Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Abstract: Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a substrate on which MEMS components are fabricated and coupling predetermined ones of the MEMS components via the redistribution traces.

Abstract: A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.

Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Abstract: A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with a second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: The present invention provides a strip plate structure and a method for manufacturing the same. The strip plate structure comprises a strip plate array, which comprises a plurality of strip plates arranged with spacing in a predetermined direction on a same plane, wherein each of the strip plates has a first surface and a second surface opposite to the first surface and the strip plate array is arranged on a plane parallel to the first surface of the strip plates; a plurality of strip sheets which connect neighboring ones of the strip plates; flexible material layers, which are located on at least a portion of the surfaces of the strip sheets and/or on at least a portion of the surfaces of the strip plates.

Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion.

Abstract: To provide a display device which can be manufactured with higher efficiency in the use of material through a simplified manufacturing process, and a method for manufacturing the display device. Another object is to provide a technique by which patterns of a wiring the like which constitutes the display device can be formed to a desired shape with good control. In a method for forming a pattern according to the present invention, a mask is formed over a light-transmitting substrate; a first region including a photocatalyst is formed over the substrate and the mask; the photocatalyst is irradiated with light through the substrate to modify a part of the first region; a second region is formed; and a composition containing a pattern forming material is discharged to the second region, thus, a pattern is formed. The mask does not transmit light.

Abstract: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate.

Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.

Abstract: An IPD semiconductor device has a capacitor formed over and electrically connected to a semiconductor die. An encapsulant is deposited over the capacitor and around the semiconductor die. A first interconnect structure is formed over a first surface of the encapsulant by forming a first conductive layer, forming a first insulating layer over the first conductive layer, and forming a second conductive layer over the first insulating layer. The second conductive layer has a portion formed over the encapsulant at least 50 micrometer away from a footprint of the semiconductor die and wound to operate as an inductor. The portion of the second conductive layer is electrically connected to the capacitor by the first conductive layer. A second interconnect structure is formed over a second surface of the encapsulant. A conductive pillar is formed within the encapsulant between the first and second interconnect structures.

Abstract: The image sensor includes a substrate; a wiring structure formed on a front side of the substrate and including a plurality of wiring layers and a plurality of insulating films; a first well formed within the substrate and having a first conductivity type; and a first metal wiring layer directly contacting a backside of the substrate and configured to apply a first well bias to the first well.

Abstract: A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.

Abstract: A semiconductor integrated circuit device can be mounted on a circuit board through capacitive coupling even when being miniaturized. A passivation film disposed on a principal surface of a semiconductor substrate provided with a plurality of wirings laminated sequentially with insulating films therebetween has an opening at which at least a portion of the uppermost layer wiring is exposed. An electrode is arranged to cover the uppermost layer wiring exposed at the opening of the passivation film and the periphery of the opening of the passivation film. A dielectric layer is arranged to cover the electrode. An extension portion of the electrode on the surface of the passivation film and an electrode of a circuit board are capacitively coupled with a dielectric layer therebetween.

Abstract: A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides, and laying out a second power-supply wiring pattern further in at least a portion of a pattern-layout allowable area remaining in the vacant areas.

Abstract: A multi-level integrated circuit comprising a superposition of a first stack and a second stack of layers, and including: a first row of electronic devices produced in the first stack, extending parallel to a first direction and fitting into a first volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H1; a second row of electronic devices produced in the second stack, extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H2<H1; a plurality of electrical connection elements passing through the second stack of layers, each connection element fitting into a third volume arranged on the first volume and next to the second volume.

Abstract: A submount for an electronic device includes a substrate formed of a bulk material including first and second major surfaces on opposite sides of the substrate, a surface insulating layer on the first major surface of the substrate, and a die attach pad on the surface insulating layer. The die attach pad may be electrically insulated from the substrate by the surface insulating layer. The submount further includes a heatsink contact pad on the second major surface of the substrate, and a thermal conduction member extending from the second major surface of the conductive semiconductor substrate through the substrate toward the first major surface of the substrate. The thermal conduction member has a higher thermal conductivity than a thermal conductivity of the bulk material of the substrate.

Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Abstract: Device for connecting nano-objects to external electrical systems, and method for producing the device. According to the invention, which applies in particular to molecular characterization, a device including the following is produced: an upper layer (16) equipped with upper contact pads (8) to be connected to a nano-object (2); a lower layer (18), equipped with lower contact pads (12) to be connected to an external electrical system (4); above the lower layer, a bonding layer (20) including electrical through-vias (22) in contact with the lower pads; and, between the bonding layer and the upper layer, at least two layers (22, 24) equipped with conductive lines (25) and electrical vias (26), for connecting the upper pads to the lower pads.

Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.

Abstract: A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.

Abstract: A layer of a porous insulating film precursor is formed on or over a substrate, a layer of a specific silicon compound is then formed, this silicon compound layer is pre-cured as necessary, and the porous insulating film precursor is exposed to UV through the silicon compound layer or pre-cured layer.

Abstract: A method for fabricating through-silicon via structure includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.

Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract: An integrated circuit includes a conductive pad and a substrate. The conductive pad is used to transfer a first signal. The substrate blocks a second signal from a first region of the substrate to the conductive pad. A second region of the substrate insulates a third region of the substrate from the first region. The first and third regions include a first type of semiconductor and the second region includes a second type of semiconductor. In addition, a first shadow obtained by perpendicularly projecting the third region onto a surface of the substrate overlaps with a second shadow obtained by perpendicularly projecting the conductive pad onto the surface.

Abstract: A semiconductor device includes contact structures and conductive wires formed over the contact structures and coupled to the respective contact structures. Part of each of the conductive wires crosses the contact structure.

Abstract: A manufacturing method of a semiconductor substrate includes the following steps: forming a first wiring layer on a substrate; forming an interlayer insulating film having a via hole on the wiring layer; forming carbon nanotubes in the via hole; performing a fluorination treatment entirely to the substrate; forming an embedded film in the via hole having the carbon nanotubes therein; and polishing the substrate to entirely flatten the substrate.

Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.

Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.

Abstract: A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure includes an n-contact region and a p-contact region. A cross section of the n-contact region comprises a plurality of first regions wherein portions of the light emitting layer and p-type region are removed to expose the n-type region. The plurality of first regions are separated by a plurality of second regions wherein the light emitting layer and p-type region remain in the device. The device further includes a first metal contact formed over the semiconductor structure in the p-contact region and a second metal contact formed over the semiconductor structure in the n-contact region. The second metal contact is in electrical contact with at least one of the second regions in the n-contact region.

Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.

Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.

Abstract: Methods for the fabrication of nanostructures, including nanostructures comprised of carbon nanotubes, and the nanostructures, devices, and assemblies prepared by these methods, are described.

Abstract: A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.

Abstract: An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 ?m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 ?m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 ?m or finer is formed therefrom.

Abstract: Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature.

Abstract: An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: An encapsulated die (100, 401) comprises a substrate (110, 510) having a first surface (111), an opposing second surface (112), and intervening side surfaces (113), with active devices located at the first surface of the substrate. The active devices are connected by a plurality of electrically conductive layers (120, 520) that are separated from each other by a plurality of electrically insulating layers (125, 525). A protective cap (130, 530) is located over the first surface of the substrate contains an interconnect structure (140) exposed at a surface (131) thereof. In another embodiment, a microelectronic package (200) comprises a package substrate (250) with an encapsulated die (100) such as was described above embedded therein.

Abstract: A method of forming a vertical interconnect for a memory device. The method includes providing a substrate having a surface region and defining a cell region, a first peripheral region, and a second peripheral region. A first thickness of dielectric material is formed overlying the surface region. A first bottom wiring structure spatially configured to extend in a first direction is formed overlying the first dielectric material for a first array of devices. A second thickness of a dielectric material is formed overlying the first wiring structure. The method includes forming an opening region in the first peripheral region. The opening region is configured to extend in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate.

Abstract: Systems and methods of nanomaterial transfer are described. A method of nanomaterial transfer involving fabricating a template and synthesizing nanomaterials on the template. Subsequently, the nanomaterials are transferred to a substrate by pressing the template onto the substrate. In some embodiments, the step of transferring the nanomaterials involves pressing the template onto the substrate such that the nanomaterials are embedded below a surface layer of the substrate. In some embodiments, the temperature of the plurality of nanomaterials is raised to assist the transfer of the nanomaterials to the substrate.

Abstract: An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.

Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.