Fault Detecting In Electric Circuits And Of Electric Components Patents (Class 324/500)
  • Patent number: 6807505
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: October 19, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Franciscus G. M. De Jong, Mathias N. M. Muris, Robertus M. W. Raaijmakers, Guillaume E. A. Lousberg
  • Publication number: 20040201287
    Abstract: A safety device is provided that can be connected with a technical device and an associated emergency activation apparatus. The safety device includes a rail. The rail and emergency activation apparatus are fashioned such that the emergency activation apparatus can be attached to the rail and be shifted thereon. A test signal can be output by the rail that can be received by an emergency activation apparatus attached thereto independent of its shift position. A response signal can be output by the emergency activation apparatus that can be received by the rail independent of the shift position emergency activation apparatus. The safety device is fashioned such that a signal can be emitted to the technical device dependent on the receipt of the response signal. Via the signal, an emergency measure can be triggered, for example an emergency disconnection of the technical device such as an E-stop or, respectively, dead-man's function.
    Type: Application
    Filed: March 12, 2004
    Publication date: October 14, 2004
    Inventors: Robert Kagermeier, Reiner Staab
  • Publication number: 20040189315
    Abstract: An evaluator (210) having an input (207) for receiving a signal indicative of a channel current sensed via a sensor in a mutlichannel current sharing system, and circuitry (313, 319) coupled to the input (207) and responsive to the signal for indicating an unreliable sensing for the sensor when a low current condition occurs for a time period exceeding the switching time period of the channel current. Further, the apparatus can include an additional input (207) and circuitry (313, 319) for evaluating an additional sensor sensing an additional channel current. The low current condition is characterized by thresholds corresponding to the peak level and a valley level of the channel current over a switching time period.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Vladimir Alexader Muratov, Stefan Wlodzimierz Wiktor
  • Publication number: 20040183542
    Abstract: A high-precision, multi-port compatible, relative correction method and apparatus for correcting measurement errors covering an increase in the number of ports of a non-coaxial electronic component, in which a relative correction adapter 31 is provided that is formed of a two-port network connected to each port of a production test fixture 5B adjacent to a measurement apparatus. The relative correction adapter has a characteristic that modifies the electrical characteristics generated by the production test fixture 5B having an electronic component under test mounted thereon into electrical characteristics generated by a standard test fixture 5A having the electronic component under test mounted thereon. An error factor of the relative correction adapter 31 is identified from a standard test fixture measurement value and a production test fixture measurement value of a correction data acquisition specimen 11B.
    Type: Application
    Filed: December 19, 2003
    Publication date: September 23, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Gaku Kamitani
  • Publication number: 20040174172
    Abstract: A high-precision, multi-port compatible, relative correction method and apparatus for correcting measurement errors covering an increase in the number of ports of a non-coaxial electronic component, in which a relative correction adapter 31 is provided that is formed of a two-port network connected to each port of a production test fixture 5B adjacent to a measurement apparatus. The relative correction adapter has a characteristic that modifies the electrical characteristics generated by the production test fixture 5B having an electronic component under test mounted thereon into electrical characteristics generated by a standard test fixture 5A having the electronic component under test mounted thereon. An error factor of the relative correction adapter 31 is identified from a standard test fixture measurement value and a production test fixture measurement value of a correction data acquisition specimen 11B.
    Type: Application
    Filed: May 15, 2003
    Publication date: September 9, 2004
    Inventor: Gaku Kamitani
  • Patent number: 6787801
    Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: September 7, 2004
    Assignee: Infienon Technologies AG
    Inventors: Helmut Fischer, Alan Morgan
  • Patent number: 6788403
    Abstract: A checking machine for being used in a fabricating process of a display module and checking a position of a tape automated bonding (TAB) region is provided. The checking machine includes a main holder having an inclined panel positioned at an inclination &bgr; relative to the horizontal, wherein the range of the inclination &bgr; is 0°<&bgr;≦90°, a test plate having a first hollow portion for suiting a size of the display module and a circuit plate disposed around the first hollow portion for suiting the position of the tape automated bonding region, and a fixing device for fixing the test plate to the inclined panel, thereby the tape automated bonding region is electrically connected with the circuit plate.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: September 7, 2004
    Assignee: Hannstar Display Corp.
    Inventor: Chun-Hung Lien
  • Patent number: 6785617
    Abstract: The present invention discloses method and apparatus for wafer analysis. First, a plurality of specific distribution maps, which respectively refer to a defect pattern distribution in a pattern group, is defined. Next, a plurality of distribution features is defined so that each specific distribution map correlates to one of the distribution features. Then, each pattern group on the wafer is compared to each specific distribution map in order to relate each pattern group to at least one of the specific distribution maps, and relate each pattern group on the wafer indirectly to at least one of the distribution features while allocating each distribution feature indirectly related to each pattern group with a respective relative value. Finally, the relative values of each distribution feature are totaled on the wafer respectively to obtain total values of the distribution features.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: August 31, 2004
    Assignee: ProMOS Technologies Inc.
    Inventor: Hung-Jen Weng
  • Publication number: 20040150407
    Abstract: A system and method of monitoring LCD production yields, predicting the effects of different testing methodologies on LCD production yields, and optimizing production yields is provided that compares the effect of different testing methodologies on the yields at various stages in the LCD testing and assembly process. The present invention can also be used to predict the effect of different testing methodologies on user-defined parameters, such as profit.
    Type: Application
    Filed: May 28, 2003
    Publication date: August 5, 2004
    Applicant: YieldBoost Tech, Inc.
    Inventor: Kyo Young Chung
  • Patent number: 6768313
    Abstract: The present invention relates to method for a detecting tracking short. In some embodiments, the method may include detecting current flowing on an electric circuit. In other embodiments, the method may include calculating the frequency distribution of the variation of the current detected in a predetermined period. In an embodiment, the method may include outputting a detecting signal in case the frequency of variations included in the predetermined range satisfies a judgement reference.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: July 27, 2004
    Assignee: Tempearl Industrial Co., Ltd.
    Inventors: Yasunori Hamai, Takeshi Kamada, Hideki Miyamoto
  • Publication number: 20040130454
    Abstract: Thermostatic Controller and Circuit Tester is a new trouble shooting device, designed to improve the air conditioning technicians fault diagnostic capabilities. The device comes equipped with two independent circuits and its own built in flashlight. The first circuit is the controller, which is outfitted with test leads with alligator clips controlled by four push on-push off switches. When attached to the thermostat wires or the air handlers connector block, it allows the air conditioning system to be manually overridden, so as to determine and locate defects in the system. The next circuit, with detachable test leads and probes, performs line voltage and continuity tests.
    Type: Application
    Filed: January 7, 2003
    Publication date: July 8, 2004
    Inventor: Errol Wendell Barton
  • Publication number: 20040119477
    Abstract: A limiting amplifier (LIA), used for example in high speed optical communication systems, includes a loss of signal (LOS) feature that may provide improved optical receiver performance and includes wide range user-programmable thresholds for generating analog loss of signal (LOS) alarms. In particular, multiple sampling points within the limiting amplifier may be used. These samples may be differentially amplified with weighted gains and then combined and compared to a threshold value to generate an LOS alarm signal.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventor: Mehdi Kazemi-Nia
  • Patent number: 6754606
    Abstract: A method of protecting a circuit arrangement for processing data, particularly a microprocessor, preferably a smart card controller, in which circuit arrangement, during and/or at the end of manufacturing this circuit arrangement and for the purpose of manufacturing control scan tests, a shift register chain is formed by combining memory cells of the circuit arrangement, preferably memory cells formed as flip-flops, in a predetermined configuration from these memory cells, by means of this shift register chain and/or another shift register chain formed in the circuit arrangement, arbitrary states are generated in the memory cells of the circuit arrangement and evaluated in a predetermined way for testing the functional capability of the memory cells of the circuit arrangement loaded with these states, after ending the manufacturing control scan test, the shift register chain is made unusable.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: June 22, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Detlef Mueller
  • Publication number: 20040106025
    Abstract: According to one aspect of the invention, a diagnostic apparatus for a fuel cell installed in a moving object as a power source is characterized by comprising an operation control portion that is connected to a control system installed in the moving object to perform operation control of the fuel cell and that performs operation control of the fuel cell by issuing an operational instruction to the control system, a diagnostic portion that diagnoses a state of the fuel cell on the basis of operation of the fuel cell controlled by the operation control portion, and a power adjustment portion that adjusts power obtained from the fuel cell operated by the operation control portion during a diagnosis made by the diagnostic portion.
    Type: Application
    Filed: November 19, 2003
    Publication date: June 3, 2004
    Inventors: Norihiko Saito, Masaaki Kondo
  • Publication number: 20040106022
    Abstract: According to an aspect of the invention, a diagnostic apparatus which diagnoses a state of the fuel cell includes an operation device which is used for operating the fuel cell; an operational state detecting portion which detects a change in an operational state of the fuel cell; a device control portion which controls the operation device such that the fuel cell is operated according to at least one predetermined operation pattern; and a diagnostic portion which diagnoses the state of the fuel cell based on the change in the operational state of the fuel cell that is detected by the change in the operational state detecting portion when the fuel cell is operated by the device control portion according to the at least one predetermined operation pattern, and the at least one predetermined operation pattern.
    Type: Application
    Filed: November 19, 2003
    Publication date: June 3, 2004
    Inventors: Norihiko Saito, Masaaki Kondo
  • Publication number: 20040085215
    Abstract: An improved pump, reservoir and reservoir piston are provided for controlled delivery of fluids. A motor is operably coupled to a drive member, such as a drive screw, which is adapted to advance a plunger slide in response to operation of the motor. The plunger slide is removably coupled to the piston. A method, system, and an article of manufacture for automatically detecting a force sensor failure in a medication infusion pump is provided. The electrical current to an infusion pump is measured. Based on the current measurements, the infusion pump detects when the plunger slide is seated in the reservoir, and detects a problem with the force sensor when the force sensor independently fails to register a value indicating that the plunger slide is seated in the reservoir.
    Type: Application
    Filed: October 22, 2003
    Publication date: May 6, 2004
    Applicant: MEDTRONIC MINIMED, INC.
    Inventors: Sheldon B. Moberg, Ian B. Hanson
  • Publication number: 20040070401
    Abstract: An Addressable Electronic Switch (AES) is disclosed together with unique S/W (software) procedures for a system control to detect, locate, and isolate shorts, overloads, and other troubles, such as temporary breaks or disconnects, on a Vplex or similar 2-wire polling loop. The addressable electronic switches are placed at strategic locations throughout the polling loop, and are individually commanded by the system control to either connect or disconnect its respective branch from the rest of the polling loop, to locate and isolate a troubled area from the rest of the polling loop.
    Type: Application
    Filed: October 11, 2002
    Publication date: April 15, 2004
    Applicant: Honeywell International, Inc.
    Inventors: Francis C. Marino, Jon C. Bruns, Jean U. Millien, John J. Ryan
  • Patent number: 6720774
    Abstract: A control board controls operation of a plurality of ventilation fans and generates a fault signal upon occurrence of a predetermined fault condition. The control board includes a control circuit in a circuit board, an interface connector connected to the control circuit and mounted to the circuit board, and control connectors connected to the circuit and mounted to the circuit board. The control connectors are configured to connect the control circuit to ventilation fans or other components to be controlled. The control connectors are connected to a fault detection device of the control circuit operable to generate a fault signal upon occurrence of a predetermined fault condition at the control connectors.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: April 13, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Carl L. Meert, Thomas E. Stewart, Timothy W. Olesiewicz
  • Patent number: 6720872
    Abstract: An arc fault/ground fault circuit interrupter for a power circuit includes a line terminal; a load terminal; and separable contacts electrically connected between the line and load terminals. An operating mechanism opens the separable contacts and has a closed position for closing the separable contacts. A trip mechanism cooperates with the operating mechanism to trip open the separable contacts. A ground fault protection circuit is operatively associated with the power circuit. An arc fault protection circuit is also operatively associated with the power circuit. A circuit tests the ground fault protection circuit, tests the arc fault protection circuit, and restores the operating mechanism to the closed position responsive to sequential activation of test and reset buttons.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: April 13, 2004
    Assignee: Eaton Corporation
    Inventors: Joseph C. Engel, Robert T. Elms, John C. Schlotterer
  • Publication number: 20040066199
    Abstract: A method of using experimental data determines the structure and voltage dependence of transition rates for states in models of ion channels.
    Type: Application
    Filed: June 6, 2003
    Publication date: April 8, 2004
    Inventor: Paul A. Rhodes
  • Patent number: 6718284
    Abstract: A smart module is disclosed for use in testing equipment such as cables and wire harnesses. The smart module may be incorporated within an adapter that interfaces with a test device and a wiring analyzer. The smart module includes a processor and a memory wherein data relating to the adapter may be stored. The smart module further includes first and second inputs that enable synchronous, bi-directional communication with the wiring analyzer. The smart module receives power, clock, communication data, and a reference input from the wiring analyzer and transmits data stored in the memory. The smart module may further include one or more visual indicators, such as LEDs, for displaying conditions of an interface between the adapter and a test device.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: April 6, 2004
    Assignee: Cirris Systems Corporation
    Inventors: Paul S. Smith, Jon Alan Bertrand
  • Patent number: 6708139
    Abstract: A method and apparatus are provided for determining quality metrics associated with a test pattern used to test an integrated circuit (IC). The delays associated with (1) a longest sensitizable path through the IC that includes the delay fault and (2) an actual path exercised by the test pattern through the IC that includes the delay fault are determined. A difference between the delays is then obtained. The difference is then combined with a difference between a speed at which the test is performed and a design specification operating speed of the IC for the actual path. The sum represents the first quality metric associated with the test pattern for a given fault site. The ratio of the delays of the actual path to the longest sensitizable path represents the second quality metric associated with the test pattern for a given fault site.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: March 16, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Jeff Rearick, Manish Sharma
  • Patent number: 6701270
    Abstract: The present invention provides a method for reliability testing leakage characteristics in an electronic circuit, and a testing device for accomplishing the same. In an advantageous embodiment, the method includes dividing conductors of an electronic circuit into at least first and second noninterleaved regions having at least two conductors each. The method further includes forming conductor nets by electrically connecting ones of the at least two conductors of the first region to ones of the at least two conductors of the second region then testing for electrical leakage in the conductor nets.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 2, 2004
    Assignee: LSI Logic Corporation
    Inventors: Leah M. Miller, Anand Govind
  • Publication number: 20040021578
    Abstract: This invention relates to a limited range low voltage testing, regulating, and indicating device comprising a detector and low voltage measurer of magnitude in a switch-regulated power supply circuit wherein indicator LEDs are operated directly from a power supply wherein continually increasing current draw provided by shunt switching operates to cause the first display LEDs to “fade” in an overlapping pattern of activation, in and out with slight voltage changes. Increased voltage causes a second LED to turn on. Further increased voltage causes the second LED to turn off and a third LED to turn on. Shunt and series connected voltage regulators selectively exert control over the LEDs.
    Type: Application
    Filed: July 30, 2002
    Publication date: February 5, 2004
    Inventors: James Hudson, Thomas J. Mayer
  • Publication number: 20040021449
    Abstract: The present invention discloses a method and apparatus (4) for condition diagnosing of a tap changer (1) immersed in a cooling fluid (3), controlling and regulating an inductive power device (5), such as a transformer or reactor. The diagnosing method basically compares and evaluates expected heat exchanges between the tap changer (1) and ambient air and the inductive power device (5), an expected amount of heat generated by the tap changer (1) during operation, together with an actual temperature of the fluid (3). From the actual temperature, expected heat exchanges and expected generated heat, the heat balance in the system may be obtained and is used for disgnosing the operation conditions of the tap changer (1). The results from the condition diagnosing may be used as indicators (70) that can alarm operators or may be sent as a data signal (78) to remote and/or portable display means (79), such as a computer.
    Type: Application
    Filed: June 16, 2003
    Publication date: February 5, 2004
    Inventors: Bengt-Olof Stenestam, Gunnar Andersson
  • Patent number: 6687627
    Abstract: Power quality detection, monitoring, reporting, recording and communication in a revenue accuracy electrical power meter is disclosed. All recorded and computed data is moved to non-volatile storage via direct memory access transfer in the event that a power quality event jeopardizes the operating power of the meter. The meter provides a power supply utilizing high and low capacitive storage banks to supply sufficient energy to survive short duration power quality events which jeopardize the meter's operating power. The power supply also enables the meter to initiate and complete a shut-down routine allowing the storage of he recorded and computed data. Further, a separate power supply utilizing a capacitive storage bank is utilized to operate a communications device when the operating power is lost.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 3, 2004
    Assignee: Power Measurement Ltd.
    Inventors: Colin N. Gunn, Hal E. Etheridge, Martin A. Hancock, Simon H. Lightbody, Dan N. Loewen
  • Patent number: 6686747
    Abstract: A programmable voltage divider has normal and test modes of operation. The divider includes first and second supply nodes, a divider node that provides a data value, and a first divider element that is coupled between the first supply node and the divider node. The divider also includes a controlled node, a second divider element that has a selectable resistivity and that is coupled between the divider node and the controlled node, and a test circuit that is coupled between the controlled node and the second supply node. During the normal mode of operation, the first and second divider elements generate the data value having a first logic level when the second divider element has a first resistivity, and generate the data value having a second logic level when the second divider element has a second resistivity. The test circuit generates a first voltage at the controlled node during the normal mode of operation, and generates a second voltage at the controlled node during the test mode of operation.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: February 3, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Donald M. Morgan
  • Publication number: 20040015338
    Abstract: The present invention is directed to a method and apparatus for simulating digital electronic systems. The signal integrity of a digital electronic system is assessed by analyzing traces (e.g. wires between components) for cross coupling. Problem areas are identified by monitoring storage components or output ports of the electronic system. Wires (traces), which carry signal transitions to the storage component or output ports are analyzed and quantified based on timing windows associated with the wires (traces). The clock transitions into a storage device are analyzed and vulnerability windows are identified for the storage device. The vulnerability windows are time periods when cross coupling may occur on a storage device. If a timing window overlaps a vulnerability window the timing window is considered a critical timing window. Devices driving the transition on wires with critical timing windows are then analyzed.
    Type: Application
    Filed: July 19, 2002
    Publication date: January 22, 2004
    Inventors: William Richard Lawrence, Francisco A. Ostojic, Michael Rogers Lambert, Robert J. Martin, Edward V. Weber
  • Patent number: 6675108
    Abstract: In a line protection unit for monitoring fault conditions of an electrical power line and actuating breakers to disconnect the line from a power supply bus, the supply bus is in the ring bus arrangement including a first bus and an auxiliary bus so that each power line includes first and second breakers. The three phase current in the line is monitored at both the breakers and summed in the unit to allow calculation of the fault conditions based upon the total current in the line. In the event of a fault condition, both breakers are tripped. In the event of breaker failure so that current continues to flow, this is detected in the unit and all the first breakers tripped to prevent the faulty breaker from allowing current to flow to the faulty line.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: January 6, 2004
    Assignee: NXT Phase Corporation
    Inventors: David James Fedirchuk, James Wood
  • Patent number: 6670201
    Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: December 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masaki Kouno, Masato Hamamoto, Atsushi Wakahara, Hideyuki Takahashi, Keiichi Higeta, Mitsugu Kusunoki, Kazutaka Mori
  • Publication number: 20030234651
    Abstract: The present invention is a system for automatically testing and providing notification of an efficacy failure of an electrostatic discharge (ESD) device or devices. The system includes testing circuitry for testing the efficacy of one or more ESD devices, a memory for storing ESD device testing protocol, ESD device test results, employee identification information, e-mail messaging software, and interface connection software, an internet interface, and a processor for controlling the testing circuitry in accordance with the executed process steps of the ESD device testing protocol and for controlling the storing of the ESD device test results in memory, wherein the processor automatically provides email notification of efficacy failure of an ESD device by collecting and formatting an ESD device test result into an e-mail message using the stored e-mail messaging software and forwarding the e-mail through the internet interface using the internet connection software.
    Type: Application
    Filed: June 20, 2002
    Publication date: December 25, 2003
    Applicant: Semtronics
    Inventor: Hoa Nguyen
  • Patent number: 6665591
    Abstract: A protection device includes a measurement device and a downstream evaluation device. The evaluation device is a unit for early short-circuit identification which actuates a semiconductor switch, which is preferably produced based on silicon carbide. The unit for early short-circuit identification preferably operates with switching thresholds which can be predetermined for the product of the current and the current rate of change, or on the basis of tolerant locus curves. In the latter case, different power factors (0.1<cos100 <0.9) are used in the locus curves in a locus curve representation of the current and current rate of change. The semiconductor switch preferably contains two back-to-back series-connected switching elements based on silicon carbide.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: December 16, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Gerd Griepentrog, Reinhard Maier, Heinz Mitlehner, Erich Zerbian
  • Patent number: 6654219
    Abstract: A protection device for an electrical circuit having a load includes a sensor operatively associated with the electrical circuit to sense current changes and voltage fluctuations in the electrical circuit. A detector receives input from the sensor and compares the input to known arc fault signatures and arc fault mimicking signatures to determine what category of arc fault or mimicked arc fault occurs. The detector then produces an encoded output signal indicative of the category of arc fault or mimicked arc fault. Categories of arc faults include upstream or downstream series, downstream parallel, downstream line to line, and downstream line to ground.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: November 25, 2003
    Assignee: Pass & Seymour, Inc.
    Inventors: James P. Romano, Jeffrey C. Richards
  • Publication number: 20030214305
    Abstract: A system and a method are distinguished by the fact that, if it is determined that the system is not operating properly, a control device is stopped and it is ensured that the control device, when operation is continued, begins with the execution of the operation whose faulty execution may be the cause for the fault registered, or which was being executed when the fault was registered. This makes it possible, with little effort and without noticeable disruption to the operation of the system, to determine whether improper operation of the system is of only a temporary nature or of a permanent nature, and for the system or parts of the same to be deactivated or reset only when the fault that has occurred is not a temporary fault.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 20, 2003
    Inventor: Wihard Christophorus Von Wendorff
  • Patent number: 6650956
    Abstract: A checking method is described for a wiring harness having first sub-harnesses and second sub-harnesses in which the first sub-harness has a first press-fit terminal joined to each end of a first electrical cable, and the first sub-harness has a first isolator holding the first press-fit terminal and the second sub-harness has a second press-fit terminal, a crimp terminal, a connector housing for accommodating the crimp terminal, a second isolator supporting the second press-fit terminal and wherein a second electrical cable connects the second press fit terminal and the crimp terminal at opposite ends. The checking method, which is effective upon layering of the first and second isolators includes the conduct of decision steps for determining acceptance or rejection of the individual sub-harnesses after assembly thereof and a final decision step for determining acceptance or rejection of the completed wiring harness layering following of the isolators of the first and second sub-harness.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: November 18, 2003
    Assignee: Yazaki Corporation
    Inventors: Kazuhiko Takada, Yutaka Matsuoka, Katsuhiro Suzuki, Hidehiko Yabuuchi, Toshiyuki Ueki, Wataru Tanizawa
  • Patent number: 6636035
    Abstract: In an electronic caliper, a detecting circuit 112 detects displacement of a grid with respect to a scale, on the basis of a signal from a transducer 110. A CPU 114 displays the detected position on a display device 124. The CPU 114 performs error detection on the transducer, only when the relative speed of the grid with respect the scale is zero, or becomes equal to or smaller than a predetermined value. Since error detection is performed only at a predetermined timing, power consumption can be reduced.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: October 21, 2003
    Assignee: Mitutoyo Corporation
    Inventors: Tetsuro Kiriyama, Toshiharu Miyata, Nobuyuki Hayashi, Kouji Sasaki, Yoshiaki Shiraishi
  • Publication number: 20030193010
    Abstract: A method and apparatus for detecting material accretion and peeling in a system such as a plasma process chamber, including multiple optical sensors which are provided in the chamber above a gas distribution plate or other surface inside the chamber. The optical sensors are connected to a central process controller that is capable of terminating operation of the chamber and may be equipped with an alarm. In the event that the optical sensors detect asymmetries in brightness or light reflection among various portions or regions of the gas distribution plate or other surface, which asymmetries may indicate the formation of a material coating on the plate or dislodging of contaminant particles from the plate, a signal is sent to the process controller, which may be adapted to terminate the plasma process, alert operating personnel, or both.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 16, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jenq-Yann Tsay, Jeng-Chiang Chuang, Chih-Pen Yen, Yung-Mao Hsu
  • Patent number: 6624638
    Abstract: LED lamp circuitry that emulates an incandescent lamp's behavior upon remote verification of the LED lamp. The invention presents a fuse blow-out circuit and a cold filament detection circuit permitting the use of LED lamps in applications, such as railway signal light applications, where there is a need for remote monitoring of the lamps, while keeping the advantageous features of lower power consumption and longer life. The invention also provides a control circuit for enabling/disabling the power supply to LED lamps in relation to the level of the line voltage. The advantage of this embodiment is to avoid unwanted functioning of the LED lamp caused by interference from surrounding electrical cables.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: September 23, 2003
    Assignee: Gelcore, LLC
    Inventor: Nicolas St-Germain
  • Patent number: 6622108
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 16, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Franciscus G. M. De Jong, Mathias N. M. Muris, Robertus M. W. Raaijmakers, Guillaume E. A. Lousberg
  • Patent number: 6618842
    Abstract: A prototype development apparatus includes a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of the IC sites, and a plurality of logic board connector sites (LBCSs) configured to provide access to a number of the logic traces and each adapted to receive a connector. Additionally, a mezzanine board (MB) has a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and configured to provide access to a number of mezzanine traces interconnecting the LBCSs. The MB board is coupled to the LB and a portion of the logic traces are coupled to a portion of the mezzanine traces. In another embodiment the MB does not have any active components. This is because in this embodiment, the MB is configured to connect the pins of the connector sites according to a predetermined program.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: September 9, 2003
    Assignee: NVIDIA Corporation
    Inventors: Ernest P. Vogel, Sam J. Nicolino, Jr., Robert J. Hasslen, III, Fernando G. Martinez
  • Patent number: 6608485
    Abstract: LED lamp circuitry that emulates an incandescent lamp's behavior upon remote verification of the LED lamp. The invention presents a fuse blow-out circuit and a cold filament detection circuit permitting the use of LED lamps in applications, such as railway signal light applications, where there is a need for remote monitoring of the lamps, while keeping the advantageous features of lower power consumption and longer life. The invention also provides a control circuit for enabling/disabling the power supply to LED lamps in relation to the level of the line voltage. The advantage of this embodiment is to avoid unwanted functioning of the LED lamp caused by interference from surrounding electrical cables.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: August 19, 2003
    Assignee: Gelcore, LLC
    Inventor: Nicolas St-Germain
  • Patent number: 6605948
    Abstract: A test system for testing the wiring configuration of a programming plug 10 for a gas turbine engine control unit 16 includes an array of multiplexers 28. The multiplexers concurrently acquiring one data bit from a prescribed data pin in each of several groups of data pins projecting from the plug. A computer operating under the authority of an executable computer program produces an incrementable selection signal to successively prescribe the individual data pins from which data is to be acquired. The system also includes standards against which the condition or validity of the wiring configuration is assessed. A display system, such as a video monitor reports the condition of the programming plug.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: August 12, 2003
    Assignee: United Technologies Corporation
    Inventor: Paul D. Russell
  • Patent number: 6600324
    Abstract: LED lamp circuitry that emulates an incandescent lamp's behaviour upon remote verification of the LED lamp. The invention presents a fuse blow-out circuit and a cold filament detection circuit permitting the use of LED lamps in applications, such as railway signal light applications, where there is a need for remote monitoring of the lamps, while keeping the advantageous features of lower power consumption and longer life. The invention also provides a control circuit for enabling/disabling the power supply to LED lamps in relation to the level of the line voltage. The advantage of this embodiment is to avoid unwanted functioning of the LED lamp caused by interference from surrounding electrical cables.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: July 29, 2003
    Assignee: Gelcore, LLC
    Inventor: Nicolas St-Germain
  • Patent number: 6597179
    Abstract: LED lamp circuitry that emulates an incandescent lamp's behaviour upon remote verification of the LED lamp. The invention presents a fuse blow-out circuit and a cold filament detection circuit permitting the use of LED lamps in applications, such as railway signal light applications, where there is a need for remote monitoring of the lamps, while keeping the advantageous features of lower power consumption and longer life. The invention also provides a control circuit for enabling/disabling the power supply to LED lamps in relation to the level of the line voltage. The advantage of this embodiment is to avoid unwanted functioning of the LED lamp caused by interference from surrounding electrical cables.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: July 22, 2003
    Assignee: Gelcore, LLC
    Inventor: Nicolas St-Germain
  • Patent number: 6593714
    Abstract: In an inverter which implements drive control on a three-phase AC motor by detecting a first-phase current value and a second-phase current value among three-phase alternating current values with two current sensors, one of the current sensors is determined to be abnormal if one of the absolute value of the deviation of the first-phase current detection value relative to a first current command value and the absolute value of the deviation of the second-phase current detection value relative to a second-phase current command value exceeds a first judgement reference value while the three-phase AC motor is being driven.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: July 15, 2003
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Kazutoshi Nagayama
  • Patent number: 6587544
    Abstract: Method for measuring a load impedance (ZL) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal device, having the following steps: specifically a digital toll signal (x1) is generated by means of a Codec circuit (13) connected to the SLIC circuit (6), said toll signal (x1) being converted into an analog toll signal; the analog toll signal is output by the SLIC circuit (6) to the load circuit; an analog voltage which is brought about at the terminal connection (4,5) of the terminal device of the SLIC circuit (6) via the analog toll signal is sensed; the digital toll signal (x1) is filtered by means of an adaptive filter (39) which is provided in the Codec circuit (13) and has adjustable filter coefficients (g1, g2) for generating a filtered digital comparison signal (yv) which is converted into an analog comparison voltage (Uv); the filter coefficients (g1, g2) of the adaptive filter (39) are adjusted until the analog comparison voltage (Uv) and the analog
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: July 1, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Nössing, David Schwingshackl, Herbert Zojer
  • Patent number: 6586943
    Abstract: A sensor signal processing apparatus includes a sensor section, power supply section, switching section, and CPU. The characteristics of the sensor section change in accordance with a change in physical quantity to be measured. The power supply section supplies powers of two systems having different polarities to the sensor section. The switching section is connected between the power supply section and the sensor section to switch combinations of powers of the two systems from the power supply section while preventing mixing of powers of the two systems. The CPU obtains the ratio between the differences between a plurality of signals output from the sensor section for every switching operation of the switching section.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: July 1, 2003
    Assignee: Yamatake Corporation
    Inventors: Takashi Masuda, Yasuhide Yoshikawa
  • Patent number: 6586945
    Abstract: Apparatus (1) for testing the integrity of a toner cartridge (3), the apparatus (1) including a drive means (8,11) adapted to rotate gear (12) for rotating the drum (4) in the cartridge (3), an electrical means powered and adapted to provide electrical static charges via the electrodes (14) in the contact arm (13) to enable the cartridge (3) to imitate the normal electrical operation of the cartridge (3), and to an operator to control testing conditions of the cartridge (3) being tested. The invention further includes methods of testing the integrity the cartridge (3) using the apparatus (1).
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: July 1, 2003
    Assignee: Printer Ribbon Inkers Limited
    Inventor: David Stanley Hendrick Geurts
  • Patent number: 6586944
    Abstract: Apparatus and methods for creating a fault such as a varying resistance fault causing static are disclosed. Devices according to the invention include a housing having an entrance face and defining an interior region, a quantity of granular electrically conductive material contained within the interior region, and a pair of electrical conductors extending through the entrance face of the housing, each conductor having a first portion that extends into the interior region of the device. Each of the first portions includes a distal portion that is in electrical contact with the granular conductive material, and the quantity of granular material is such that the granular material provides an intermittent electrical connection between the distal portions.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: July 1, 2003
    Assignee: BellSouth Intellectual Property Corporation
    Inventor: Kenneth F. Bugg
  • Patent number: 6577137
    Abstract: Methods and apparatus are provided for motor testing wherein performance characteristics are determined for motors exhibiting linear operating characteristic curves without making contact with shafts of the motors during testing. More particularly, a motor to be tested is operated in one direction to a no-load speed and then reversed with current and speed measurements being made during this testing period. A full load or stall point or points and a no-load point or points are determined from the measurements so that linear speed versus torque and/or current versus torque motor characteristic curves can be generated for the motor. Multiple voltages can be applied to determine a family of characteristic curves for the motor.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: June 10, 2003
    Inventor: James Allan Fisher