Abstract: A semiconductor structure may implement a metal-oxide-metal capacitor. When layer design rules change from one layer to the next, the structure may change the direction of the interleaved plates of the capacitor. For example, when the metallization width or spacing design rules change from layer M3 to layer M4, the structure may run the capacitor traces in different directions (e.g., orthogonal to one another) on M3 as compared to M4. Among the layers that adhere to the same design rules, for example layers M1, M2, and M3, the structure may run the capacitor traces in the same direction in each of the layers M1, M2, and M3. In this way, the capacitor traces overlap to large extent without misalignment on layers that have the same design rules, and the structure avoids misalignment of the capacitor traces when the design rules change.

Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.

Abstract: A film capacitor element including a base dielectric film layer 12, a vapor-deposition metal film layer 14 formed on the base dielectric film layer 12 and consisting of a first film portion 20 and a second film portion 22 that are spaced apart from each other by a margin portion 18, and a dielectric covering film layer 16 which is formed integrally on the second film portion 22 by vapor-deposition polymerization or coating and which has a covering portion 30 which fills the margin portion 18 and covers an entire area of an end face of the second film portion 22 on the side of the margin portion 18. The first film portion 20 including a non-covered portion 34 which is not covered by the dielectric covering film layer 16.

Abstract: Capacitive circuits are implemented with desirable quality factors in various implementations. According to an example embodiment, a fringe capacitor includes two capacitive circuits (e.g., plates), respectively having a plurality of capacitive fingers extending from an end structure, and respectively having a connecting pin that is adjacent the connecting pin of the other capacitive circuit, on a common side fringe capacitor. The capacitive fingers are arranged in stacked layers, with vias connecting the fingers in different layers back to the connecting pins.

Abstract: A capacitor structure including a dielectric material layer and at least two metal layers is provided. The metal layers are disposed at intervals in the dielectric material layer. Each of the metal layers includes a zigzaging electrode, a first finger-shaped electrode and a second finger-shaped electrode. The zigzaging electrode forms a plurality of first concave parts disposed at one side of the zigzaging electrode and a plurality of second concave parts disposed at the other side of the zigzaging electrode. The first finger-shaped electrode includes a plurality of first extension parts. The first extension parts are respectively disposed in the first concave parts. The second finger-shaped electrode includes a plurality of second extension parts. The second extension parts are respectively disposed in the second concave parts. The zigzaging electrode in each of the metal layers is electrically coupled to the first and second finger-shaped electrodes of adjacent metal layers.

Abstract: Provided is an electrochemical device compatible with high-temperature reflow soldering using a lead-free solder. An electrical double layer capacitor 10-1 includes a package 14 that is constructed with a film or films and has sealed parts 14a1 to 14a3 formed by sealing parts, in which films are superimposed on each other, by, for example, heat sealing. The entireties of the sealed parts 14a1 to 14a3 of the package 14 are covered in a close-contact state with a support 16 that has higher rigidity than the film(s) constructing the package 14.

Abstract: An on-chip capacitor includes a first layer first polarity conducting strip and a first layer second polarity conducting strip, wherein the first layer second polarity conducting strip is arranged adjacent to and spaced apart from the first layer first polarity conducting strip, a second layer first polarity conducting strip and a second layer second polarity conducting strip, wherein the second layer second polarity conducting strip is arranged adjacent to and spaced apart from the second layer first polarity conducting strip, wherein the second layer second polarity conducting strip is arranged overlying the first layer second polarity conducting strip, wherein the second layer first polarity conducting strip is arranged overlying the first layer first polarity conducting strip; wherein the first layer first-polarity conducting strip electrically couples with the second layer first polarity conducting strip; and wherein the first-layer second polarity conducting strip electrically couples with the second la

Abstract: An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: An electronic component includes a laminate including a plurality of insulating layers that are laminated on each other. A capacitor conductor is embedded in the laminate and includes an exposed portion exposed between the insulating layers at a predetermined surface of the laminate. An external electrode is provided on the predetermined surface by direct plating so as to cover the exposed portion. An outer edge of the external electrode is spaced away from the exposed portion by about 0.8 ?m or more.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: A liquid composition is provided for forming a thin film in the form of a mixed composite metal oxide in which a composite oxide B containing copper (Cu) and a composite oxide C containing manganese (Mn) are mixed into a composite metal oxide A represented with the general formula: Ba1-xSrxTiyO3, wherein the molar ratio B/A of the composite oxide B to the composite metal oxide A is within the range of 0.002<B/A<0.05, and the molar ratio C/A of the composite oxide C to the composite metal oxide A is within the range of 0.002<C/A<0.03.

Abstract: In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

Abstract: The present disclosure is directed to a device and a method for achieving a precise capacitance of a capacitor. The method includes trimming a first capacitance of the capacitor to a second capacitance, the capacitor having a first conductive layer separated from a second conductive layer by a dielectric layer. Changing a first dielectric constant of the dielectric layer to a second dielectric constant, where the first dielectric constant corresponding to the first capacitance and the second dielectric constant corresponding to the second dielectric constant includes heating the dielectric layer above a threshold temperature for a time period. The heat is provided by either one of the plates of the capacitor or from a separate heater.

Abstract: A hard start capacitor replacement unit has a plurality of capacitors in a container sized to fit in existing hard start capacitor space. The capacitors are 4 metallized film capacitors wound in a single cylindrical capacitive element. The container has a common terminal and capacitors value terminals for the plurality of capacitors, which may be connected singly or in combination to provide a selected capacitance. An electronic or other relay connects the selected capacitance in parallel with a motor run capacitor. The hard start capacitor replacement unit is thereby adapted to replace a wide variety of hard start capacitors.

Abstract: A capacitive element that can efficiently reduce high-frequency noise generated in a circuit is provided. A capacitive element 1 includes a capacitive formation portion 100, which is formed in the shape of a loop to separate the inside from the outside. The capacitive formation portion 100 includes an electrode 110, an opposite electrode 111, and a dielectric layer 120. One or more outgoing terminals (one or more outer circumference outgoing terminals 140, and one or more internal circumference outgoing terminals 130) are provided at the outer and inner circumferences of the electrode 110, respectively. A printed wiring board is made by mounting the capacitive element inside the board or on the surface of the board. A semiconductor package is made by putting the capacitive element 1 on a target semiconductor circuit portion. Moreover, a semiconductor circuit is made by placing the capacitive element on a target functional circuit portion 301.

Abstract: A capacitor system and a method for producing a capacitor system. The capacitor system may be used in a power semiconductor module. In one embodiment, the capacitor system comprises a metal shaped body having a depression; a capacitor arranged at least partly in the depression; a spacer composed of electrically insulating material, the spacer being arranged at least partly between the capacitor and the metal shaped body in the depression; and an electrically insulating potting material provided in the depression, wherein the potting material fixes the capacitor in the depression so that the capacitor does not touch the metal shaped body.

Abstract: A power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.

Abstract: A capacitor-embedded substrate includes a base material having a desired thickness, and a pair of conductors (feedthrough electrodes) each formed in a desired pattern to penetrate through the base material in the thickness direction thereof, and oppositely disposed with an insulating layer interposed therebetween. The pair of electrodes are formed in comb-shaped patterns, and are oppositely disposed in such a manner that respective comb-tooth portions are meshed with each other.

Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.

Abstract: A system and method for sealing a capacitor bottom in a filtered feedthrough. The feedthrough comprises a ferrule, a capacitor, at least one terminal pin and a support structure. The support structure includes at least one projection that extends into an aperture of the capacitor. The projection includes an opening through which the at least one terminal pin extends such that, in an assembled state, the terminal pin extends through the opening of the projection and the aperture of the capacitor.

Abstract: A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.

Abstract: A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.

Abstract: A method of forming a vinylidene fluoride (VDF) oligomer or co-oligomer film on a substrate is disclosed. The method comprises forming a VDF oligomer or co-oligomer precursor solution; depositing the VDF oligomer or co-oligomer precursor solution onto the substrate to form a preliminary VDF oligomer or co-oligomer film on the substrate; and applying uniaxial pressure on the preliminary VDF oligomer or co-oligomer film and the substrate at an elevated temperature to form the VDF oligomer or co-oligomer film on the substrate. The substrate may comprise a metal surface which may be used as a bottom electrode and a top electrode may be deposited on the VDF oligomer or co- oligomer film The VDF oligomer or co-oligomer film, the bottom electrode on the substrate and the top electrode on the VDF oligomer or co-oligomer film form an electrical device.

Abstract: An electrostatic capacitor device is disclosed including first and second spaced apart electrode structures separated by a dielectric structure in which the first and second electrode structures are each formed from a composite material which includes electrically conductive fibres in a binder matrix.

Abstract: An electronic component mounting structure which can reduce the ESL while saving the space when mounting electronic components is provided. A first electronic component 7 is electrically connected to surface-mounted electrode parts 11A, 12A at metal terminals 26, 27 such that a first capacitor 24 having a greater capacitance and a mounting surface 4a of a multilayer substrate 4 are separated from each other. A second electronic component 8 is arranged between the first capacitor 24 and the mounting surface 4a and electrically connected to surface-mounted electrode parts 12B, 11B at second terminal electrodes 32, 33. The second electronic component 8 overlaps the first capacitor 24 when seen in the laminating direction. The first electronic component 7 is mounted to the multilayer substrate 4 such that first terminal electrodes 22, 23 oppose each other in a predetermined direction D1.

Abstract: A ceramic electronic component includes a ceramic body and a plurality of external electrodes disposed at a surface of the ceramic body. The external electrodes include a plating layer containing glass particles each coated with a metal film. The plating layer is formed by co-deposition of a plating metal and the metal-coated glass particles.

Abstract: Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.

Abstract: An apparatus includes a charge storage device. The charge storage device includes a first plate, a second plate, and a dielectric. The dielectric separates the first and the second plate. The first plate is configured to hold a first charge, and the second plate is configured to hold a second, opposite, charge. The charge storage device is housed in a product receptacle that is configured to charge the first plate and the second plate such that the charge storage device is able to generate an electrical current.

Abstract: The aim of the present invention is to harvest the improvised impact of the hydrometeors into a practical mechanical energy with the use of mechanical capacitor. Consequently, the mechanical energy is converted into electricity via the principal of electromagnetic induction.

Abstract: Particles of active electrode material are made by blending or mixing a mixture of activated carbon, optional conductive carbon, and binder. In selected implementations, the activated carbon particles have between about 70 and 98 percent microporous activated carbon particles and between about 2 and 30 percent mesaporous activated carbon particles by weight. Optionally, a small amount of conductive particles, such as conductive carbon particles may be used. In one implementation, the binder is inert. The electrode material may be attached to a current collector to obtain an electrode for use in various energy storage devices, including a double layer capacitor.

Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.

Abstract: A thin film capacitor includes: two electrode layers; a dielectric film interposed between the two electrode layers; an opening that pierces through, together with the dielectric film, in the thickness direction, any one of the two electrode layers or a conductive layer in the same level adjacent to one of the two electrode layers; and a reinforcing member that couples, in the opening, a side surface of the dielectric film to a side surface of the one electrode layer or the conductive layer.

Abstract: An electronic component that is prevented from being inclined with respect to a circuit board during and after mounting includes a laminated body that is preferably configured by stacking a plurality of insulator layers, and includes a lower surface with depressions provided thereon. The lower surface includes a series of outer edges of the insulator layers. Capacitor electrodes are defined by internal conductors incorporated in the laminated body, which respectively have exposed sections that are exposed from between the insulator layers in the depressions on the lower surface. External electrodes, which are preferably formed directly by plating, are provided in the depressions to cover the exposed sections.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: A capacitor provides a plurality of selectable capacitance values, by selective connection of six concentrically wound capacitor sections of a capacitive element each having a capacitance value. The capacitor sections each have a respective section element terminal at a first end of the capacitive element and the capacitor sections have a common element terminal at a second end of the capacitive element. A pressure interrupter cover assembly is sealingly secured to the open end a case for the element and has a deformable cover with a centrally mounted common cover terminal and a plurality of section cover terminals mounted at spaced apart locations. A conductor frangibly connects the common element terminal of the capacitive element to the common cover terminal and conductors respectively frangibly connect the capacitor section terminals to the section cover terminals.

Abstract: Parallel plate bus structures are commonly used for high-current applications where low inductance is a requirement. Such bus structures are very well suited for inverter topologies used to convert from DC to AC power and a capacitor is needed to minimize ripple on the DC bus. The present invention provides a method of integrating an annular form factor wound film capacitor into a parallel bus structure to provide a compact geometry with minimal inductance. Furthermore, the capacitor acts as the dielectric spacer between the bus plates, which eliminates the need for separate capacitor terminals and provides the lowest possible profile.

Abstract: A sensor includes a first printed wiring board having a first electrode made of a metal film, a second printed wiring board facing the first printed wiring board and having a second electrode made of a metal film, the second electrode being positioned on the second printed wiring board such that the second electrode faces the first electrode of the first printed wiring board, and a dielectric body spacing the first electrode and the second electrode apart such that the first electrode, the second electrode and the dielectric body form a capacitor.

Abstract: A multi-layer capacitor includes a first capacitor layer and a second capacitor layer adjacent and substantially parallel to the first capacitor layer. The second capacitor layer has a surface area that is less than the surface area of the first capacitor layer.

Abstract: The present invention provides a raw coke having such a structure that the graphitized product resulting from graphitization of the raw coke at a temperature of 2800° C. under an inactive gas atmosphere will have ratios of the crystallite size to the lattice constant of 360 or less in the (002) plane and 1500 or less in the (110) plane, as a raw coke providing active carbon produced by alkali-activating the raw coke, which is reduced in remaining alkali content and can simplify washing operation because washing liquid can easily pass through the activated carbon, or as a raw coke for the production of needle coke.

Abstract: The present invention provides a raw coke having such a structure that the graphitized product resulting from graphitization of the raw coke at a temperature of 2800° C. under an inactive gas atmosphere will have ratios of the crystallite size to the lattice constant of 360 or less in the (002) plane and 1500 or less in the (110) plane, as a raw coke providing active carbon produced by alkali-activating the raw coke, which is reduced in remaining alkali content and can simplify washing operation because washing liquid can easily pass through the activated carbon, or as a raw coke for the production of needle coke.

Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Abstract: A trench capacitor structure is provided. The trench capacitor structure includes a substrate, a trench formed in the substrate, a plurality of scallops formed in the sidewalls of the trench, and at least one capacitor formed within at least one of the scallops. The disclosure also provides a method of manufacturing the trench capacitor structure.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: A magnetic capacitor includes two electrode layers, an insulator layer, and one or more magnetized layers. The insulator layer is located between the first electrode layer and the second electrode layer. The one or more magnetized layers include one or more ferro-magnetic elements that are magnetized. The one or more magnetized layers are located so that the one or more ferro-magnetic elements apply a magnetic field to the insulator layer to improve an electrical property of the insulator layer. Magnetic fields applied perpendicular to the electrode layers increase the capacitance and electrical energy storage of the insulator layer. Magnetic fields applied parallel to the electrode layers decrease the leakage current and increase the breakdown voltage of the insulator layer. The one or more ferro-magnetic elements used can include ferro-magnetic plates or magnetic nanodots. The one or more magnetized layers can be located between or outside of the electrode layers.

Abstract: A system for providing selective capacitance with a bundled capacitor is described herein. The bundled capacitor can include a housing a cap, a central common terminal, a plurality of auxiliary terminals, an interrupter, an insulating spider, a plurality of individual rolled sandwich like connected capacitors, a thermal fuse, a frangible electrical connection, an insulating layer, a resin, and an expansion chamber. A single phase motor can be connected to the bundled capacitor.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: A capacitor includes a substrate made of an organic film, a first conductive layer provided on an upper surface of the substrate, a first dielectric layer provided on an upper surface of the first conductive layer, a second dielectric layer provided on an upper surface of the first dielectric layer, and a second conductive layer provided on an upper surface of the second dielectric layer. The first dielectric layer is made of plural metal oxide chips spread over on the upper surface of the first conductive layer. The second dielectric layer is made of plural metal oxide chips spread over on a lower surface of the second conductive layer. This capacitor can have a large capacitance.

Abstract: A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.

Abstract: The capacitor module includes a capacitor, in which a screw hole is arranged on an outer bottom wall surface of a capacitor case housing a capacitor element, and a heat dissipater, on which a plurality of capacitor cases are fixated by screwing fixation screws in the screw holes of the capacitors. As a result, for example, the capacitor can be fixated with reliability and durability secured even under a condition where very strong vibration is continuously applied, for example, when the capacitor module is mounted on construction machinery. Further, because, an adherence of the outer bottom wall surface of the capacitor case on a fixation surface of the heat dissipater is strengthened by screwing the fixation screw in the screw hole, the capacitor can be cooled down by transferring heat produced by the capacitor to the heat dissipater as needed.