Abstract: A fabric connector for sensing object proximity is provided. The fabric connector comprises a sensing layer (23), an insulating layer (22) and a yarn (26). The sensing layer has at least one connection region (233a, 233b, 233c, 233d) and a disconnection region. The at least one connection region (233a, 233b, 233c, 233d) has a capacitance value and is formed with conductive fabric. The insulation layer (22) which is formed with insulating fabric is disposed below the sensing layer (23). The yarn (26) is formed with conductive material and is configured to electrically connect to the at least one connection region (233a, 233b, 233c, 233d) of the sensing layer (23) and a sensor (25). The sensor (25) senses a variation in the capacitance value of the at least one connection region (233a, 233b, 233c, 233d) in accordance with object proximity.

Abstract: The present invention is directed to an encapsulated ?? particle emitter that comprises a sol-gel derived core that comprises a ??-emitting radioisotope and an encapsulant enclosing the core through which at least some of the ?? emissions from the ??-emitting radioisotope pass, wherein the encapsulant comprises a substrate and a cover and at least a portion of the encapsulant is electrically conductive, and a method for making the same. Additionally, the present invention is directed to a capacitor comprising such an encapsulated ?? particle emitter and a method of performing work with such a capacitor.

Abstract: A method of forming a capacitor includes forming a cylindrical lower electrode structure having an internal support structure on a substrate, forming a dielectric layer on the cylindrical lower electrode structure and the support structure, and forming an upper electrode on the dielectric layer.

Abstract: A capacitor is provided having a capacitor element, with first and second metalized thermoplastic sheets, which are offset and wound together to create common edges at opposite ends, a zinc or zinc-rich conductive coating thermally sprayed on each of the common edges of the capacitor element, and aluminum or aluminum-rich terminals welded to each of the conductive coatings to form a metallurgical bond, having a pull strength of at least 5 pounds, without damaging the capacitor element.

Abstract: Disclosed is a metalized film capacitor having excellent safety preservation ability and an excellent withstand voltage at high temperatures.

Abstract: Electrostatic capacitors with high capacitance density and high-energy storage are implemented over conventional electrolytic capacitor anode substrates using highly conformal contact layers deposited by atomic layer deposition. Capacitor films that are suitable for energy storage, electrical and electronics circuits, and for integration onto PC boards endure long lifetime and high-temperature operation range.

Abstract: The present invention provides a capacitor for an inverter of a vehicle comprising a case; a plurality of capacitor unit modules; positive and negative bus plates that are disposed in the case to be connected to the capacitor unit modules; and a power module corresponding to the unit modules, wherein that the unit modules are insulated from each other through an insulating material, and wherein the bus plates each comprise a bus bar that overlaps with the other bus bar and is electrically connected to the power module.

Abstract: A capacitor is provided having a tough surface portion which prevents cracking that tends to occur when the capacitor is built-in or surface-mounted on a wiring board. A ceramic sintered body of the capacitor includes a capacitor forming layer portion, a cover layer portion and an interlayer portion. The capacitor forming layer portion has a laminated structure wherein ceramic dielectric layers and inner electrodes connected to a peripheral portion of capacitor via conductors, are alternately laminated. The cover layer portion is exposed at a surface portion of the ceramic body and has a laminated structure wherein ceramic dielectric layers and dummy electrodes not connected to the capacitor via conductors, are alternately laminated.

Abstract: A laminate includes insulating layers laminated to each other. Capacitor conductors are embedded in the laminate and have exposed portions exposed between the insulating layers at respective surfaces of the laminate. The capacitor conductors define a capacitor. External electrodes are provided by plating on the respective surfaces of the laminate so as to directly cover the respective exposed portions. When the laminate is viewed in plan in a y axis direction, the length of each of the exposed portions is approximately 35% to approximately 45% of the length of an outer periphery of the insulating layer.

Abstract: The present invention provides a raw coke having such a structure that the graphitized product resulting from graphitization of the raw coke at a temperature of 2800° C. under an inactive gas atmosphere will have ratios of the crystallite size to the lattice constant of 360 or less in the (002) plane and 1500 or less in the (110) plane, as a raw coke providing active carbon produced by alkali-activating the raw coke, which is reduced in remaining alkali content and can simplify washing operation because washing liquid can easily pass through the activated carbon, or as a raw coke for the production of needle coke.

Abstract: Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures.

Abstract: It is provided a ceramic multilayer substrate obtained by co-sintering a low dielectric constant layer made of an insulating material of a low dielectric constant and a high dielectric constant layer of a dielectric material of a high dielectric constant. The low dielectric constant layer includes a ceramic component of xBaO-yTiO2-zZnO (“x”, “y” and “z” represent molar ratios, respectively, and satisfy the relationship: x+y+z=1; 0.09?x?0.20; 0.49?y?0.61; 0.19?z?0.42) and 1.0 to 5.0 weight parts of a glass component comprising boron oxide with respect to 100 weight parts of the ceramic component. The high dielectric layer is made of a barium titanate based dielectric material with CuO and Bi2O3 added thereto.

Abstract: A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material.

Abstract: A high power, low passive inter-modulation capacitor is presented, which is formed using metal clad substrates, which are broad-side coupled through a thin air gap. Each substrate may include metal layers affixed on both sides which are electrical coupled together to form a single capacitor plate, or each substrate may have only a single metal layer on the surface adjacent to the air gap. The capacitor has particular application in low cost RF and microwave filters, which may be used in communication equipment and communication test equipment such a diplexers, for low PIM applications.

Abstract: An electronic component includes a laminate including a plurality of insulating layers that are laminated on each other. A capacitor conductor is embedded in the laminate and includes an exposed portion exposed between the insulating layers at a predetermined surface of the laminate. An external electrode is provided on the predetermined surface by direct plating so as to cover the exposed portion. An outer edge of the external electrode is spaced away from the exposed portion by about 0.8 ?m or more.

Abstract: (1) A niobium monoxide powder for a capacitor represented by formula: NbOx (x=0.8 to 1.2) and optionally containing other elements in an amount of 50 to 200,000 ppm, having a tapping density of 0.5 to 2.5 g/ml, an average particle size of 10 to 1000 ?m, angle of repose from 10° to 60°, the BET specific surface area from 0.5 to 40 m2/g and a plurality of pore diameter peak tops in the pore distribution, and a producing method thereof; (2) a niobium monoxide sintered body, which is obtained by sintering the above niobium monoxide powder and, having a plurality of pore diameter peak tops in a range of 0.01 ?m to 500 ?m, preferably, the peak tops of two peaks among the plurality of pore diameter peak tops having a highest relative intensity are present in the range of 0.2 to 0.7 ?m and in the range of 0.7 to 3 ?m, respectively, and a producing method thereof; (3) a capacitor using the above sintered body and a producing method thereof; and (4) an electronic circuit and electronic device using the above capacitor.

Abstract: An anchor group anchors organic dielectric compounds used in the production of organically based capacitors. The capacitors referred to are those that can be produced in a parallel process on a prepeg or other common printed circuit board substrate without additional metallisation on copper. The pre-fabricated capacitor layer can then be built into the printed circuit board, thereby gaining on space and cost for the surface of the printed circuit board.

Abstract: A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: The present invention relates to one or more electrode plates, which are installed with collecting current terminals at two or more sides thereof, clipping with an auxiliary conductor made of the material with conductivity better than that of the electrode plates; in which collecting current terminals are installed at two or more sides of the auxiliary conductor, for linking with the collecting current terminals installed at two or more sides of the electrode plates, and at least one of which are used to be the general collecting current terminal to output current to the external part or to receive the input current from the external part; and there are insulators installed between the auxiliary conductor and the electrode plates to constitute an electrode unit.

Abstract: In one embodiment, an apparatus includes a first reference voltage coupled to a first metal layer and a second reference voltage coupled to a second metal layer. A first finger type in the plurality of fingers is coupled to the first metal layer at a first area and coupled to the first metal layer and the second metal layer at a second area. A second finger type in the plurality of fingers is coupled to the second metal layer at the first area and coupled to the first metal layer and the second metal layer at the second area. Also, the first finger type and the second finger type alternately positioned next to each other.

Abstract: An interposer including: a substrate including a first layer and second layer, wherein the first layer and second layer are positioned parallel to each other; electrodes each having a concave-convex structure formed on each facing surface of the first layer and second layer of the substrate; a dielectric layer sandwiched between the electrodes which are formed on each facing surface of the first layer and second layer of the substrate; a first conductive part which vertically passes through the first layer of the substrate from a first outer surface of the substrate and is electrically connected to an electrode formed on a surface of the second layer of the substrate that faces the first layer of the substrate; and a second conductive part which vertically passes through the second layer of the substrate from a second outer surface of the substrate and is electrically connected to an electrode formed on a surface of the first layer of the substrate that faces the second layer of the substrate.

Abstract: A capacitor with a combined with a resistor and/or fuse is described. This safe capacitor can rapidly discharge through the resistor when shorted. The presence of a fuse in series with the capacitor and results in a resistive failure when this opens during and overcurrent condition. Furthermore, the presence of a resistor in parallel to the capacitor allows the energy to be rapidly dissipated when a failure occurs.

Abstract: There is provided a variable device circuit according to the present invention, including: a substrate; at least one movable switch device formed on a first principal surface of the substrate; at least one fixed capacitor device formed on the first principal surface of the substrate; at least one variable capacitor device formed on the first principal surface of the substrate; at least one variable inductor device formed on the first principal surface of the substrate; and wiring lines for electrically connecting the devices to one another, the wiring lines being formed on the first principal surface of the substrate; wherein electrical connections among the devices can be selected by operation of the movable switch device, whereby achieving stable, low-loss circuit characteristics with lower manufacturing cost.

Abstract: According to the preferred embodiment, an integrated capacitor having a fence-shaped structure is provided. The integrated capacitor comprises a fence-shaped, outer metal pattern and a dielectric layer. The fence-shaped, outer metal pattern encompasses an inner metal pattern, and the dielectric layer is situated between the outer metal pattern and the inner metal pattern.

Abstract: A capacitor provides a plurality of selectable capacitance values, by selective connection of six concentrically wound capacitor sections of a capacitive element each having a capacitance value. The capacitor sections each have a respective section element terminal at a first end of the capacitive element and the capacitor sections have a common element terminal at a second end of the capacitive element. A pressure interrupter cover assembly is sealingly secured to the open end a case for the element and has a deformable cover with a centrally mounted common cover terminal and a plurality of section cover terminals mounted at spaced apart locations. A conductor frangibly connects the common element terminal of the capacitive element to the common cover terminal and conductors respectively frangibly connect the capacitor section terminals to the section cover terminals.

Abstract: The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a high-density capacitor system comprising a substrate and a porous conductive layer formed on the substrate, wherein the porous conductive layer is formed in accordance with a predetermined pattern. Furthermore, the high-density capacitor system includes a dielectric material formed on the porous conductive layer and a second conductive layer formed on the dielectric material. Additionally, the high-density capacitor system includes a plurality of conductive pads configured in communication with the second conductive layer.

Abstract: Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.

Abstract: Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A second sacrificial material may be formed over the first capacitor storage node and over the first sacrificial material, and a retaining structure may be formed over the second sacrificial material. A second opening may be formed through the retaining structure and the second sacrificial material, and a second capacitor storage node may be formed within the second opening and against the first storage node. The first and second sacrificial materials may be removed, and then capacitor dielectric material may be formed along the first and second storage nodes. Capacitor electrode material may then be formed along the capacitor dielectric material. Some embodiments include methods of forming DRAM unit cells, and some embodiments include DRAM unit cell constructions.

Abstract: An electrical circuit arrangement provides a substrate and at least two conductive surfaces. The substrate comprises at least one layer disposed between the conductive surfaces. The conductive surfaces form a capacitor and overlap in part and form an overlapping area. In the event of a displacement of the conductive surfaces relative to one another, the resulting overlapping area is largely constant up to a threshold value of the displacement.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: Devices for storing energy at a high density are described. The devices include carbon-containing extensions which increase the surface area between a dielectric material and one or both of the electrodes. The dielectric material may have a high dielectric constant (high permittivity) and a high breakdown voltage, allowing a high voltage difference between paired electrodes to effect a high stored energy density.

Abstract: An improved method for forming a capacitor. The method includes: providing a carrier with a channel therein; providing a metal foil with a valve metal with a first dielectric on a first face of the metal foil; securing the metal foil into the channel with the first dielectric away from a channel floor; inserting an insulative material between the metal foil and each side wall of the channel; forming a cathode layer on the first dielectric between the insulative material; forming a conductive layer on the cathode layer and in electrical contact with the carrier; lap cutting the carrier parallel to the metal foil such that the valve metal is exposed; and dice cutting to form singulated capacitors.

Abstract: A capacitor and method of fabricating a capacitor. A method of fabricating a capacitor may include forming a device isolation film on and/or over a semiconductor substrate, forming a polysilicon pattern on and/or over a device isolation film, forming a silicide on and/or over an upper portion of a polysilicon pattern, forming a capacitor insulating film covering a silicide, forming a pre-metal-dielectric (PMD) on and/or over a semiconductor substrate having a capacitor insulating film, and/or forming an upper metal electrode on and/or over a hole on and/or over a PMD, which may expose an insulating film opposite a region of a silicide.

Abstract: (1) A niobium monoxide powder for a capacitor represented by formula: NbOx (x=0.8 to 1.2) and optionally containing other elements in an amount of 50 to 200,000 ppm, having a tapping density of 0.5 to 2.5 g/ml, an average particle size of 10 to 1000 ?m, angle of repose from 10° to 60°, the BET specific surface area from 0.5 to 40 m2/g and a plurality of pore diameter peak tops in the pore distribution, and a producing method thereof; (2) a niobium monoxide sintered body, which is obtained by sintering the above niobium monoxide powder and, having a plurality of pore diameter peak tops in a range of 0.01 ?m to 500 ?m, preferably, the peak tops of two peaks among the plurality of pore diameter peak tops having a highest relative intensity are present in the range of 0.2 to 0.7 ?m and in the range of 0.7 to 3 ?m, respectively, and a producing method thereof; (3) a capacitor using the above sintered body and a producing method thereof; and (4) an electronic circuit and electronic device using the above capacitor.

Abstract: Disclosed herein is a method of: placing between a cooling element and an opposing surface a slurry of: a dielectric powder containing barium titanate, a dispersant, a binder, and water; maintaining the cooling element at a temperature below the opposing surface to cause the formation of ice platelets perpendicular to the surface of the cooling element and having the powder between the platelets; subliming the ice platelets to create voids; sintering the powder to form the dielectric material; and filling the voids with the polymeric material. The process can produce a composite having: a sintered dielectric material of barium titanate and platelets of a polymeric material embedded in the dielectric material. Each of the platelets is perpendicular to a surface of the composite.

Abstract: A capacitor and capacitor-like device or any other device showing capacitive effects, including FETs, transmission lines, piezoelectric and ferroelectric devices, etc., with at least two electrodes, of which at least one electrode consists of or comprises a material or is generated as electron system, whose absolute value of the electronic charging energy as defined by the charging-induced change of Ekin+Eexc+Ecorr exceeds 10% of the charging-induced change of the Coulomb field energy of the capacitor according to E=Ecoul+Ekin+Eexc+Ecorr. Therein, E is the energy of a capacitor and Ecoul=Q2/2 Ccoul=Q2d/(2 ?0 ?x A), A is the area of the capacitor electrodes, d is the distance and ?0?x the dielectric constant between them. Ecorr describes the correlation energy, Ekin the electronic kinetic energy and Eexc the exchange energy of the electrode material.

Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad.

Abstract: A 3-D structure formed in a recess of a substrate delimited by walls, including a large number of rectangle parallelepipedic blades extending from the bottom of the recess to the substrate surface while being oriented perpendicularly to one another and formed in a pattern covering the whole surface of the recess, some blades being non-secant to one of the walls, each non-secant blade being connected to one of the walls by at least another perpendicular blade.

Abstract: There is herein disclosed an interdigital capacitor, an inductor, and an LH transmission line and a coupler using the interdigital capacitor and the inductor. The interdigital capacitor comprises two finger sets which are substantially disposed in parallel with each other. Fingers of each finger set are overlapped at outer edges thereof with each other to thereby generate capacitance. The inductor is formed substantially spirally inside the transmission line, so that it can have a large inductance in a compact shape and can be used in a broad frequency band. The LH transmission line has a broad frequency band in a compact shape, which includes interdigital capacitors connected in series with each other and inductors connected in parallel with each other. In addition, the coupler employing the LH transmission line has an excellent couplability.

Abstract: The present invention relates to systems, materials and methods for the formation of conducting, semiconducting, and dielectric layers, structures and devices from suspensions of nanoparticles. Drop-on-demand systems are used in some embodiments to fabricate various electronic structures including conductors, capacitors, FETs. Selective laser ablation is used in some embodiments to pattern more precisely the circuit elements and to form small channel devices.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Abstract: A chip component having external electrodes that allow both connection by an interlayer connection conductor and connection by soldering and a component built-in module containing the chip component therein are produced and provided. A metal of electrode parts on at least one principal surface of the external electrodes at the ends of the chip component is different from a metal of electrode parts at the remaining portion of the external electrodes. With such a structure, both a metal suitable for connection to an interlayer connection conductor, such as a via hole conductor or a through hole conductor of the component built-in module and, a metal suitable for soldering can be used for the external electrodes. Thus, the component built-in module can be reduced in the height and size.

Abstract: A ceramic electronic component includes a ceramic body and a plurality of external electrodes disposed at a surface of the ceramic body. The external electrodes include a plating layer containing glass particles each coated with a metal film. The plating layer is formed by co-deposition of a plating metal and the metal-coated glass particles.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: The present invention provides a metal-insulator-metal capacitor, which comprises a semiconductor substrate; an interlayer dielectric layer disposed on the semiconductor substrate; and an insulation trench and two metal trenches all running through the interlayer dielectric layer and allowing the semiconductor substrate to be exposed; wherein the metal trenches being located on each side of the insulation trench and sharing a trench wall with the insulation trench respectively, the insulation trench being filled with insulation material as an insulation structure, the metal trenches being filled with metal material as electrodes of the capacitor.

Abstract: An apparatus for storing electrical energy includes a first magnetic layer, a second magnetic layer, and a dielectric layer. The first magnetic layer includes a first magnetic section and a second magnetic section. The first magnetic section has magnetic dipoles with horizontal directions. The second magnetic section has magnetic dipoles with vertical directions. The second magnetic layer includes a third magnetic section and a fourth magnetic section. The third magnetic section has magnetic dipoles with horizontal directions. The fourth magnetic section has magnetic dipoles with vertical directions. The dielectric layer is configured between the first magnetic layer and the second magnetic layer. The dielectric layer is arranged to store electrical energy. The first magnetic layer and the second magnetic layer are arranged to prevent electrical energy leakage.

Abstract: Capacitive deionization (CDI) is a non-membrane and chemical-free technique for water purification, used-water recycling, and seawater desalination. Ionic contaminants in the waters are retained by a static electric field built within the critical component of CDI, which is known as flow through capacitor (FTC). Apparently, parameters enhancing the field strength of FTC and electrode efficiency are the keys to the performance of CDI. The FTC of the present invention is formed by a plurality of monopolar and a plurality of bipolar electrodes, and a plural number of perforated holes are disposed on the FTC electrodes in a pattern that allows certain water flow rate and residence time to yield the highest efficiency of electrode utilization.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.