Abstract: According to one embodiment, a capacitor arrangement support system includes a resonance analysis module configured to perform a resonance analysis based on data of a component producing electromagnetic radiation, a resonance point extraction module configured to extract a resonance point from an analysis result of the resonance analysis module, an electromagnetically radiated energy analysis module configured to analyze the ease of collection of electromagnetically radiated energy with respect to a resonance point extracted by the resonance point extraction module, a determination module configured to determine whether or not an absolute value of a value showing the ease of collection of electromagnetically radiated energy is larger than a preset absolute value, and a capacitor arrangement module configured to arrange a capacitor for suppressing electromagnetic radiation at a resonance point where the determination module determines that data of the component is larger the preset absolute value.

Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.

Abstract: In a method for forming a photoresist pattern, a method for forming a capacitor, and a capacitor manufactured using the same, a light is selectively irradiated onto a selected portion of a photoresist film formed on a substrate. An interfered light generated from the irradiated light is transmitted through other portions of the photoresist film except a ring-shaped portion of the photoresist film having a predetermined width along a boundary of the selected portion. The photoresist film is exposed using the interfered light and the light irradiated onto the selected portion. A cylindrical photoresist pattern having a minute width may be formed through developing the photoresist film. With the cylindrical pattern, the capacitor can be easily formed.

Abstract: A parallel plate magnetic capacitor (Mcap) includes two first pillar electrodes, two second pillar electrodes and a dielectric layer. The two first pillar electrodes electro-connect with each other and are located at right corner of a first plane and left corner of a second plane respectively. The two second pillar electrodes electro-connect with each other and are located at left corner of the first plane and right corner of the second plane respectively. The dielectric layer is located between the first pillar electrodes and the second pillar electrodes, such that the first pillar electrodes and the second pillar electrodes form capacitances therebetween.

Abstract: A first electrode pattern comprises a first lead-out electrode portion extending continuously along the longitudinal direction of a first dielectric film, a plurality of first capacitor electrode portions each extending from the first lead-out electrode portion almost perpendicularly to the first lead-out electrode portion, and second capacitor electrode portions which are disposed between the first capacitor electrode portions and connected thereto. The second capacitor electrode portions each has have a plurality of first sections. Each first section is connected to one end surface and the other end surface extending along the width direction of the first dielectric film of the first capacitor electrode portions through a narrow first fuse portion.

Abstract: Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: A placement configuration of MIM type capacitance elements comprises a group of first capacitance elements in which the first capacitance elements as the MIM type capacitance elements are placed in tandem and a group of second capacitance elements in which the second capacitance elements as the MIM type capacitance elements are placed in tandem, wherein the group of first capacitance elements and the group of second capacitance elements are alternately placed in parallel with each other with an equal interval therebetween.

Abstract: A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.

Abstract: There is provided a variable device circuit according to the present invention, including: a substrate; at least one movable switch device formed on a first principal surface of the substrate; at least one fixed capacitor device formed on the first principal surface of the substrate; at least one variable capacitor device formed on the first principal surface of the substrate; at least one variable inductor device formed on the first principal surface of the substrate; and wiring lines for electrically connecting the devices to one another, the wiring lines being formed on the first principal surface of the substrate; wherein electrical connections among the devices can be selected by operation of the movable switch device, whereby achieving stable, low-loss circuit characteristics with lower manufacturing cost.

Abstract: A capacitor provides a plurality of selectable capacitance values, by selective connection of six capacitor sections of a capacitive element each having a capacitance value. The capacitor sections are provided in a plurality of wound cylindrical capacitive elements. Two vertically stacked wound cylindrical capacitance elements may each provide three capacitor sections. There may be six separately wound cylindrical capacitive elements each providing a capacitor section. The capacitor sections have a common element terminal. A pressure interrupter cover assembly is sealingly secured to the open end of case for the elements and has a deformable cover with a centrally mounted common cover terminal and a plurality of section cover terminals mounted at spaced apart locations. A conductor frangibly connects the common element terminal of the capacitor section to the common cover terminal and conductors respectively frangibly connect the capacitor section terminals to the section cover terminals.

Abstract: There are provided a capacitor and a thin film capacitor-embedded multi-layer wiring board. The capacitor includes: first and second electrodes connected to first and second polarities; a dielectric layer formed therebetween; and at least one floating electrode disposed inside the dielectric layer and having overlaps with the first and second electrodes. The wiring board includes: an insulating body having a plurality of insulating layers thereon; a plurality of conductive patterns and conductive vias formed on the insulating layers, respectively, to constitute an interlayer circuit; and a thin film capacitor embedded in the insulating body, wherein the thin film capacitor includes a first electrode layer, a first dielectric layer, at least one floating electrode layer, a second dielectric layer and a second electrode layer sequentially formed, and wherein the first and second electrode layers are connected to the interlayer circuit and the floating electrode layer is not directly connected thereto.

Abstract: A method of manufacturing a circuit board embedding a thin film capacitor, the method including: forming a sacrificial layer on a first substrate; forming a dielectric layer on the sacrificial layer; forming a first electrode layer on the dielectric layer; disposing the first substrate on the second substrate in such a way that the first electrode layer is bonded to a top of a second substrate; decomposing the sacrificial layer by irradiating a laser beam onto the sacrificial layer through the first substrate; separating the first substrate from the second substrate; and forming a second electrode layer on the dielectric layer.

Abstract: The invention provides (1) a jig for producing capacitors, which stabilizes multiple long plates in order to simultaneously form dielectric layers on a plurality of conductors connected to the long plates and subsequently simultaneously form semiconductor layers thereon, wherein two edge-receiving portions to receive and fix the edges of each plate are electrically insulated from each other, (2) an apparatus comprising the jig for producing capacitors, having feeding terminals for forming dielectric layer and for forming semiconductor layer and long plates comprising a mechanism connecting multiple conductors, and a method for producing capacitors. According to the invention, capacitors each having semiconductor layer as one electrode, narrow in variation of capacitance, and excellent in the ESR value, can be produced at a time.

Abstract: A ferroelectric capacitor includes: an electrode including a platinum film; a seed layer that is formed above the electrode and is composed of oxide having a perovskite structure expressed by a general formula, A(B1-xCx)O3; and a ferroelectric layer formed above the seed layer, wherein A is composed of at least one of Sr and Ca, B is composed of at least one of Ti, Zr and Hf, C is composed of at least one of Nb and Ta, and X is in a range of 0<X<1.

Abstract: The present invention relates to a semiconductor device, and more particularly to a method for forming a metal/insulator/metal (MIM). The method comprises the steps of: forming a metal wiring surrounded by the inter-metal dielectric film; forming a plurality of insulating film on the metal wiring in sequence; and forming a metal barrier film on the insulating film, whereby the insulating film functioning as a buffer film can mitigate the stress between the films.

Abstract: Provided is a method of manufacturing a capacitor embedded printed circuit board. In the method, a laminated body is prepared, including a laminated plate having first and second copper films on both sides thereof, where at least one bottom electrode is provided on at least one side. A dielectric layer is formed on the at least one bottom electrode. A metal layer is formed on a top surface of the dielectric layer where a capacitor is to be formed. A conductive paste layer is formed on at least one region of a top surface of the metal layer, where the conductive paste layer and the metal layer is provided as a top electrode. An insulation resin layers are formed on both sides of the laminated plate, respectively. A conductive via is formed in the insulation resin layer such that it is connected to the conductive paste layer.

Abstract: A multi value capacitor is constructed in a single can having a core with three capacitor elements. The capacitor elements are chosen to provide a selectable range of discrete capacitance values when connected in various combinations. The capacitor elements are each connected to a common terminal. The first capacitor element is connected to a first cam contact, the second capacitor element is connected to a second cam contact, and the third capacitor element is connected to a third cam contact. A dial switch mechanism is mounted to the can and connected to a switched terminal, and includes a dial shaft and a rotating contact connected thereto. Rotating the dial switch mechanism will cause the rotating contact, which has three wiper contacts, to engage raised portions of the various cam contacts in various combinations to create various capacitance values between the switched terminal and the common terminal.

Abstract: A high voltage input apparatus for a magnetron, in which first protrusions formed on lead conductors are caught by insulators and an insulating case, a ground metal is bonded to the insulating case, and expanded portions formed on the insulators are caught by the insulating case and the ground metal, thereby firmly fixing the lead conductors and preventing the lead conductors from being undesirably separated from the insulators and the insulating case.

Abstract: A capacitor includes a hollow capacitor element formed by rolling a pair of flat sheet-like electrodes and, with separators interposed therebetween, a bottom-closed metallic casing receiving the capacitor element and a drive electrolyte therein, and an opening-sealing plate sealing an opening portion of the metallic casing, the opening-sealing plate having an external connection terminal. A rubber-like elastic member is provided on a surface of the opening-sealing plate at a peripheral edge portion thereof, and an electrically-insulating layer is formed on the metallic casing to cover at least a region extending from the open end of the metallic casing to a recess provided for fixing the opening-sealing plate, and the rubber-like elastic member is pressed by the open end portion of the metallic casing.

Abstract: A case molded capacitor has a metallized film capacitor, a pair of bus bars, a resin-made internal case, molding resin, a metal external case, and a buffer material layer. The bus bars are each connected to respective one of electrodes of the metallized film capacitor. The internal case contains the metallized film capacitor. The metallized film capacitor is submerged with molding resin in the internal case so as to expose parts of the bus bars. The external case contains the internal case and both cases are connected at a connecting part. A buffer material layer is put in a gap made at least at a part between the internal case and the external case.

Abstract: A semiconductor capacitor structure includes a first metal layer, a second metal layer, a first set of via plugs, a second set of via plugs, and a dielectric layer. The first metal layer includes a first portion, a plurality of parallel-arranged second portions, a third portion, and a plurality of parallel-arranged fourth portions. The second metal layer includes a fifth section, a plurality of sixth sections, a seventh section, and a plurality of eighth sections. The first set of via plugs electrically connects the plurality of second sections to the plurality of sixth sections. The second set of via plugs electrically connects the plurality of fourth sections to the plurality of eighth sections.

Abstract: A method for manufacturing a wiring board, comprising the steps of: forming a first electrode layer having first and second opening portions, forming a dielectric layer formed on the first electrode layer and having third and fourth opening portions, forming a second electrode layer formed on the dielectric layer and having fifth and sixth opening portions, wherein the first electrode layer, the dielectric layer, and the second electrode layer form a capacitor; forming an insulating layer inside a first opening defined by the first, third, and fifth opening portions, and a second opening defined by the second, fourth, and sixth opening portions; using a laser beam having a processing diameter to form first and second via holes extending through the insulating layer formed inside the first and second openings, respectively; and forming first and second via wiring portions in the first and second via holes, respectively.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A multilayer ceramic substrate with a cavity includes a multilayer composite member including a plurality of ceramic layers disposed one on another. A cavity is formed in the multilayer composite member such that an opening of the cavity is located in one principal surface of the multilayer composite member. A bottom-surface conductive film is disposed on the bottom surface of the cavity. A capacitor conductive film is disposed in the multilayer composite member such that the capacitor conductive film faces the bottom-surface conductive film via one of the ceramic layers, thereby forming a capacitor.

Abstract: A capacitor provides a plurality of selectable capacitance values, by selective connection of six concentrically wound capacitor sections of a capacitive element each having a capacitance value. The capacitor sections each have a respective section element terminal at a first end of the capacitive element and the capacitor sections have a common element terminal at a second end of the capacitive element. A pressure interrupter cover assembly is sealingly secured to the open end a case for the element and has a deformable cover with a centrally mounted common cover terminal and a plurality of section cover terminals mounted at spaced apart locations. A conductor frangibly connects the common element terminal of the capacitive element to the common cover terminal and conductors respectively frangibly connect the capacitor section terminals to the section cover terminals.

Abstract: A capacitor capable of being incorporated into a packaging substrate, which capacitor includes a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract: A capacitance type humidity sensor includes: a detection substrate including a detection portion on a first side of the detection substrate; and a circuit board including a circuit portion. The detection portion detects humidity on the basis of capacitance change of the detection portion. The circuit portion processes the capacitance change as an electric signal. The detection substrate further includes a sensor pad on a second side of the detection substrate. The sensor pad is electrically connected to the detection portion through a conductor in a through hole of the detection substrate.

Abstract: A chip-type electronic component comprises a chip element body including an inner circuit element, and a pair of terminal electrodes electrically connected to the inner circuit element. The pair of terminal electrodes are positioned at respective end portions of the chip element body. The chip element body has one side face acting as a mounting surface opposing a circuit substrate. The pair of terminal electrodes include an electrode portion formed on the mounting surface. Here, it is assumed that a first direction is a direction orthogonal to the mounting surface, a second direction is a direction along which the pair of terminal electrodes oppose each other on the mounting surface, and a third direction is a direction orthogonal to the first and second directions.

Abstract: An on-chip bypass capacitor and method of manufacturing the same, the on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including a first layer connecting the at least two capacitor arrays in series, each capacitor array including a plurality of capacitors, each of the plurality of capacitors including a second layer connecting the plurality of capacitors in parallel. The on-chip bypass capacitor may be part of a chip which also includes a memory cell array including at least one cell capacitor.

Abstract: A substrate has a base, an intermediate layer, a conductive layer, and conductive films. The base is a ceramic insulator. The intermediate layer is on a main surface of the base. The conductive layer is on the intermediate layer. The conductive films are on the conductive layer, covering an exposed portion of the conductive layer.

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Abstract: A sheet capacitor of the invention has a contact portion formed in a through-hole requiring electrical connection with an IC connection pin among the through-holes in which the IC connection pins are inserted, and a capacitor element connected to the contact portion. Another sheet capacitor of the invention includes an insulating board and a capacitor element mounted on the insulating board. The insulating board has a connection land with an IC at the upper side, and a connection land with a printed wiring board at the lower side. The capacitor element and connection lands at the upper and lower side of the insulating board are connected with each other electrically. In any one of these configurations, a capacitor element of large capacity and low ESL is connected closely to the IC, and the mounting area of the peripheral circuits of the IC can be increased.

Abstract: A laminated electronic actuator includes a pole-like laminate obtained by alternately laminating a plurality of dielectric layers and a plurality of internal electrode layers one upon the other, and two external electrode plates provided on the opposing side surfaces of the pole-like laminate, the two external electrode plates being electrically connected to every other internal electrode layer, and the one external electrode plate and the other external electrode plate being electrically connected to the different internal electrode layers. The side surfaces of the pole-like laminate on where no external electrode plate is proved have ion concentrations that are suppressed to be not higher than 10 ?g/cm2. Even when the actuator is operated by applying a high voltage, the internal electrodes are not short-circuited, effectively suppressing a change in the amount of displacement.

Abstract: A system for electronically actuating valves in an engine. The system includes first and second voltage sources, and a plurality of valve actuator subsystems coupled therebetween. Each valve actuator subsystem has a valve actuator and a switch configured to selectively control application of voltage to the valve actuator to thereby selectively control energization of the valve actuator. The system also includes a dissipation switch operatively coupled with the valve actuator subsystems, the dissipation switch being selectively operable to control dissipation of energy from any of the valve actuators.

Abstract: A multi-layered unit according to the present invention includes a support substrate formed of platinum (Pt), a buffer layer formed on the support substrate and formed of a dielectric material containing a bismuth layer structured compound having an excellent orientation characteristic and a composition represented by Bi4Ti3O12 and oriented in the c axis direction, and a dielectric layer formed on the buffer layer, formed of a dielectric material containing a bismuth layer structured compound having an excellent characteristic as a capacitor material and a composition represented by SrBi4T4O15 and containing the bismuth layer structured compound oriented in the c axis direction.

Abstract: Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

Abstract: A decoupling capacitor is formed in a semiconductor substrate that includes a strained silicon layer. A substantially flat bottom electrode is formed in a portion of the strained silicon layer and a capacitor dielectric overlying the bottom electrode. A substantially flat top electrode overlies said capacitor dielectric. The top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Abstract: A multi-layer capacitor is highly downsized and increased in capacity. A method for manufacturing the multi-layer capacitor includes, in the same vacuum chamber, forming a dielectric layer, treating a surface of the dielectric layer, forming a pattern in a metal electrode, forming the metal electrode on the dielectric layer, and treating a surface of the metal electrode. In this method, etching of the dielectric layer flattens a recessed part generated by an electrical insulation part.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film comprising an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film comprising an electrically conductive polymer located on the pentoxide layer.

Abstract: The present invention provides a technique which permits the withstand voltage measurement of a laminate web for capacitor layer manufactured by a continuous laminating method in a roll state wound around a core tube. The invention provides a roll of laminate for capacitor layer which is obtained by manufacturing a laminate web for capacitor layer by laminating a first electrically conductive layer, a dielectric layer and a second electrically conductive layer and winding this laminate web for capacitor layer from a start end side to a terminal end side thereof around a core tube.

Abstract: Provided is a method for manufacturing a metal powder by providing a reducing solution by dispersing caustic alkali, and hydrazine and/or hydrazine hydrate into a solvent; providing a metal salt solution comprising a salt of electroconductive metal, a rare earth metal salt and a solvent; and mixing the reducing solution with the metal salt solution to form a metal powder by depositing a hydroxide derived from the rare earth metal salt and by reducing the salt of electroconductive metal. With this metal powder manufacturing method, the sintering of the metal powder is restricted at a low temperature, the sintering initiation temperature is shifted to a higher level, and rapid sintering shrinkage is restricted, while ceramic grain growth is not accelerated.

Abstract: A capacitor structure having a re-oxide layer on a nitride layer, wherein an interface between the nitride layer and the re-oxide layer includes electron traps. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a consistent voltage is output for a plurality of currents.

Abstract: A signal line and a pixel capacitor wire that doubles as a pixel capacitor electrode are fabricated parallel to each other from the same electrode layer through patterning thereof. Therefore, no additional steps are required to form the pixel capacitor wire. In such an arrangement, the pixel capacitor wire and the signal line are disposed parallel to each other; therefore, delays of signal transmission in the signal line and crosstalk between pixels are prevented from occurring. The active matrix substrate incorporating this arrangement is suitably used in liquid crystal display devices, image sensors, and the like. Similar advantages are available with an arrangement in which the signal line and the pixel capacitor wire are disposed parallel to each other, and the storage capacitor electrode, which will constitute a storage capacitor with the pixel electrode therebetween, and the scanning line are fabricated from the same electrode layer through patterning thereof.

Abstract: An electronic component includes: a dielectric element formed by layering dielectric layers; two types of internal conductors, which have a plurality of extended portions, respectively, that are extended toward a plurality of side surfaces of the dielectric element, respectively; two types of terminal electrodes, of which one of the two types of terminal electrodes is connected to a plurality of extended portions of one of the two types of internal conductors, and the other of the two types of terminal electrodes is connected to the remaining plurality of extended portions; and a pair of metallic terminals, of which one of the metallic terminals is connected to one of the two types of terminal electrodes, and the other of the metallic terminals is connected to the remaining terminal electrodes. Accordingly, ESR can be reduced while allowing for sufficient absorption of stress.

Abstract: A non-contact obstacle detection system utilizing ultra sensitive capacitive techniques. In an exemplary embodiment, the system includes a sensing element disposed in proximity to a moveable panel and a proximity detection circuit in communication with the sensing element. The proximity detection circuit generates a differential output signal reflective of whether a foreign object is in proximity to the sensing element. In addition, a central control module is in communication with the sensing element. The central control module determines whether the differential output signal is reflective of a foreign object in proximity to the sensing element. If the central control module determines that the differential output signal is reflective of a foreign object in proximity to the sensing element, and the moveable panel is moving toward a closed position, then the central control module generates a control output signal to stop the moveable panel from moving toward the closed position.